CN115441866B

CN115441866B - Phase tracking loop and method based on frequency division acceleration and electronic equipment

Info

Publication number: CN115441866B
Application number: CN202211129272.2A
Authority: CN
Inventors: 刘览琦; 把傲; 柯毅; 刘德珩
Original assignee: Wuhan Silicon Integrated Co Ltd
Current assignee: Wuhan Silicon Integrated Co Ltd
Priority date: 2022-09-16
Filing date: 2022-09-16
Publication date: 2023-09-01
Anticipated expiration: 2042-09-16
Also published as: CN115441866A

Abstract

The invention relates to a phase tracking loop and a method based on frequency division acceleration and an electronic device. A phase tracking loop may include: the frequency divider is used for carrying out frequency division processing on the clock signal to obtain a carrier signal; a phase detector for comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal; a frequency division ratio control module for adjusting a frequency division ratio of the frequency divider based on the phase indication signal; and a phase tuning module for adjusting the phase of the clock signal based on the phase indication signal.

Description

Phase tracking loop and method based on frequency division acceleration and electronic equipment

Technical Field

The invention relates to a phase tracking loop and a method based on frequency division acceleration and an electronic device.

Background

In the field of wireless communications, phase tracking is sometimes required for received signals. For example, in a Near Field Communication (NFC) scenario, since amplitude modulation is used, the reader needs to track the phase of the signal read from the NFC card, and when the phase difference between the two is large, amplitude information may be lost. The signal read by the card reader from the NFC card comes from the signal generated by the load modulation of the NFC card, and the NFC card can generally adopt one of two schemes of Passive Load Modulation (PLM) and Active Load Modulation (ALM). When the passive load modulation scheme is adopted, the NFC card is completely dependent on the radio frequency signal provided by the card reader to generate a passive reading signal, so that no phase difference exists, but the generated passive reading signal has smaller energy, the communication distance is limited, and the NFC card is easy to interfere. When an active load modulation scheme is employed, an NFC device (e.g., a cell phone) in a card emulation role may simulate the load modulation process, actively transmitting a carrier signal that is phase-aligned with the reader device. Active load modulation schemes can provide greater signal power and better anti-interference characteristics, but may present phase bias issues because the carrier signal actively transmitted by the NFC device is not the same source as the reader signal.

Disclosure of Invention

The present invention generally provides a frequency division acceleration-based phase tracking loop and method, and an electronic device including such a phase tracking loop, which is capable of tracking a target phase quickly and with high accuracy over a large phase difference range.

According to an embodiment, a phase tracking loop may comprise: the frequency divider is used for carrying out frequency division processing on the clock signal to obtain a carrier signal; a phase detector for comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal; a frequency division ratio control module for adjusting a frequency division ratio of the frequency divider based on the phase indication signal; and a phase tuning module for adjusting the phase of the clock signal based on the phase indication signal.

In an embodiment, the phase detector is a binary phase detector that outputs a first indication signal when the phase of the carrier signal is advanced relative to the phase of the reference clock signal, and outputs a second indication signal when the phase of the carrier signal is retarded relative to the phase of the reference clock signal.

In one embodiment, the frequency division ratio control module includes: a dynamic detection adjustment unit for detecting the phase indication signal generated by the phase detector and generating a frequency division ratio adjustment signal; and a frequency division ratio control unit for controlling the frequency division ratio of the frequency divider based on the frequency division ratio adjustment signal.

In an embodiment, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit generates a first division ratio adjustment signal, and the division ratio control unit increases the division gear of the frequency divider until the highest gear is reached in response to the first division ratio adjustment signal. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates a second division ratio adjustment signal, and the division ratio control unit decreases the division gear of the frequency divider in response to the second division ratio adjustment signal until a base gear is reached. The frequency divider has the basic gear having a basic frequency division ratio N, and at least one higher gear having a higher frequency division ratio n+x or a lower frequency division ratio N-x, N being a preset positive integer, x being a smaller positive integer than N and the higher the gear, the larger the value of x, the higher gear having the higher frequency division ratio n+x when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and the higher gear having the lower frequency division ratio N-x when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

In an embodiment, the base divide ratio N is such that the frequency of the carrier signal is equal to the frequency of the reference clock signal.

In one embodiment, the phase tuning module comprises: a digital loop filter for generating a selection indication signal based on the phase indication signal; and a multi-phase clock selection unit for selecting one clock signal from the multi-phase clock signals based on the selection indication signal.

In one embodiment, the multiphase clock signal includes M clock signals of different phases, M being an integer greater than one. The selection indication signal generated by the digital loop filter indicates one of M index values to instruct the multiphase clock selection unit to select a corresponding clock signal from the M clock signals of different phases.

In an embodiment, when the phase indication signal generated by the phase detector indicates that the phase of the carrier signal is advanced from the phase of the reference clock signal for a predetermined period, the selection indication signal generated by the digital loop filter indicates that the multiphase clock selection unit selects one clock signal from the multiphase clock signals that is more retarded than the currently selected clock signal. When the phase indication signal generated by the phase detector indicates that the phase of the carrier signal lags behind the phase of the reference clock signal and lasts for a predetermined period, the selection indication signal generated by the digital loop filter indicates that the multiphase clock selection unit selects one clock signal from the multiphase clock signals, which is more advanced than the currently selected clock signal.

In one embodiment, the digital loop filter includes: a proportional path for generating a first proportional signal that is a first proportion to the phase indication signal; an integration path for generating a second proportion signal in a second proportion to the phase indication signal, and performing integration processing on the second proportion signal to generate an integration signal; an adder for adding the first proportional signal and the integral signal to output a sum of the two; and a remainder unit for performing a remainder operation on the sum value received from the adder with respect to a predetermined value to generate the selection instruction signal representing a remainder.

In an embodiment, the predetermined value is equal to the number of clock signals having different phases included in the multiphase clock signal.

In an embodiment, the digital loop filter further comprises at least one of: a first proportion adjusting unit provided in the proportion path for adjusting the first proportion; and a second proportion adjusting unit provided in the integrating path for adjusting the second proportion.

In an embodiment, the first and second ratio adjustment units use the same adjustment coefficient to perform an equal ratio adjustment of the first and second ratios.

In an embodiment, the phase tracking loop further comprises: and a coefficient control unit configured to control an adjustment coefficient that adjusts at least one of the first ratio and the second ratio. When the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit generates a first coefficient adjustment signal, and the coefficient control unit increases the adjustment coefficient to increase the at least one of the first proportion and the second proportion in response to the first coefficient adjustment signal until a maximum proportion is reached. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates a second coefficient adjustment signal, and the coefficient control unit decreases the adjustment coefficient in response to the second coefficient adjustment signal to decrease the at least one of the first proportion and the second proportion until a base proportion is reached.

In an embodiment, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit generates the first coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, and then generates the first division ratio adjustment signal to increase the division gear of the frequency divider until a highest gear is reached. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates the second division ratio adjustment signal to reduce the division gear of the frequency divider until a base gear is reached, and then generates the second coefficient adjustment signal to reduce the at least one of the first ratio and the second ratio until a base ratio is reached.

According to one embodiment, a phase tracking method may include: frequency division processing is carried out on the clock signal to obtain a carrier signal; comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal; the phase of the clock signal and the frequency division ratio of the frequency division process are adjusted based on the phase indication signal so that the phase of the carrier signal is closer to the phase of the reference clock signal.

In an embodiment, adjusting the frequency division ratio of the frequency division process based on the phase indication signal comprises: when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, increasing the frequency division gear of the frequency division process until the highest gear is reached; or when the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the frequency division gear of the frequency division process is lowered until a base gear is reached. The frequency division process has the basic gear and at least one higher gear, the basic gear has a basic frequency division ratio N, the higher gear has a higher frequency division ratio n+x or a lower frequency division ratio N-x, N is a preset positive integer, x is a smaller positive integer than N, and the higher the gear is, the larger the value of x is, the higher gear has the higher frequency division ratio n+x when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and the higher gear has a lower frequency division ratio N-x when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

In an embodiment, adjusting the phase of the clock signal based on the phase indication signal comprises: generating a selection indication signal based on the phase indication signal; and selecting one clock signal from the multiphase clock signals based on the selection indication signal. Wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, the selection indication signal indicates that one clock signal which is more retarded than the currently selected clock signal is selected from the multiphase clock signals; when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal, the selection indication signal indicates that one of the multiphase clock signals is selected to be more advanced than the currently selected clock signal.

In an embodiment, generating the selection indication signal based on the phase indication signal comprises: generating a first proportional signal in a first proportion to the phase indication signal; generating a second proportion signal which is in a second proportion with the phase indication signal; integrating the second proportional signal to obtain an integrated signal; performing addition operation on the first proportional signal and the integral signal to obtain a sum of the first proportional signal and the integral signal; and taking the sum value for a remainder operation with respect to a preset value to generate the selection indication signal.

In an embodiment, the method further comprises: at least one of the first ratio and the second ratio is adjusted based on the phase indication signal.

In an embodiment, adjusting at least one of the first ratio and the second ratio comprises: increasing said at least one of said first and second ratios until a maximum ratio is reached when said phase indication signal indicates that the phase of said carrier signal is more advanced or more retarded than the phase of said reference clock signal and for a predetermined period; or decreasing the at least one of the first ratio and the second ratio until a base ratio is reached when the phase indication signal indicates that the phase of the carrier signal transitions between being more advanced and more retarded than the phase of the reference clock signal and the transition reaches a predetermined number of times.

In an embodiment, when the phase indication signal indicates that the phase of the carrier signal is advanced or retarded from the phase of the reference clock signal and continues for a predetermined period, the at least one of the first ratio and the second ratio is increased first until the maximum ratio is reached, and then the frequency-divided gear of the frequency-dividing process is increased until the highest gear is reached. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the frequency division gear of the frequency division process is first lowered until a base gear is reached, and then the at least one of the first ratio and the second ratio is reduced until the base ratio is reached.

According to another embodiment, an electronic device is provided that includes the phase tracking loop described above.

The foregoing and other features and advantages of the invention will be apparent from the following description of exemplary embodiments, as illustrated in the accompanying drawings.

Drawings

Fig. 1 shows a schematic diagram of a phase tracking loop according to an embodiment of the invention.

Fig. 2 shows a schematic diagram of a phase tracking loop according to an embodiment of the invention.

Fig. 3 shows a schematic diagram of a digital loop filter according to an embodiment of the invention.

Fig. 4 shows a schematic diagram of adjusting phase by changing the frequency division ratio according to an embodiment of the invention.

Fig. 5 shows a schematic diagram of a frequency-divided gear design according to an embodiment of the invention.

Fig. 6 shows a flow chart of a phase tracking method according to an embodiment of the invention.

Fig. 7 shows a flowchart of a frequency-divided gear adjustment process according to an embodiment of the present invention.

Fig. 8 shows a flow chart of a clock phase adjustment process according to an embodiment of the invention.

Fig. 9 shows a flowchart of a method of generating a clock selection indication signal according to an embodiment of the invention.

Fig. 10 shows a flow chart of a coefficient and divider ratio adjustment process according to an embodiment of the present invention.

Fig. 11 shows a schematic diagram of an electronic device according to an embodiment of the invention.

Detailed Description

Some exemplary embodiments of the present invention will be described below with reference to the accompanying drawings. In order to clearly and fully describe these exemplary embodiments, the following description provides some specific details. It should be understood, however, that the invention is not limited to the specific details of these exemplary embodiments. Rather, embodiments of the invention may be practiced without these specific details or in other alternative ways, without departing from the spirit and principles of the invention, which are defined by the claims.

Currently, phase tracking techniques for NFC card analog devices in Active Load Modulation (ALM) mode include passive matching network based solutions and solutions using an all-digital phase locked loop (ADPLL). The adjustment of the passive matching network is not linear, the steps of phase adjustment are inconsistent at different resistance values, and high-precision adjustment is difficult to realize within a large phase difference range (for example, 0 degrees to 180 degrees). In addition, the impedance of the chip can be changed by adjusting the resistance value, so that certain adverse effects are generated on wireless communication. The all-digital phase-locked loop has a complex design and high cost, and the frequency and phase information generated in the card analog mode comes entirely from the clock recovered from the reader signal, which is often intermittent. For example, when the reader transmits a signal, the magnetic field disappears when the data is at a low level; also, for example, when the NFC card emulation device itself transmits a signal, an excessive transmitted signal will drown out the magnetic field signal of the reader. Thus, under intermittent reference clock conditions, the loop lock speed requirement for a phase locked loop is very high, as only a very short time is used for frequency and phase locking, which is difficult to solve. In conventional designs, fast locking means that the loop bandwidth is larger, bringing more phase noise introduced by the reference clock, which can affect circuit performance; on the other hand, reducing the loop bandwidth, while partially improving the phase noise performance, is difficult to achieve with fast lock requirements.

Fig. 1 shows a schematic diagram of a phase tracking loop 100 according to an embodiment of the application. As shown in fig. 1, the phase tracking loop 100 includes a frequency divider 110, a phase detector 120, a phase tuning module 130, and a division ratio control module 140.

The frequency divider 110 may divide the high frequency clock signal to obtain a low frequency clock signal, i.e., a carrier signal, at the same clock frequency as recovered from the reader magnetic field. It should be understood that in the present application both "high frequency" and "low frequency" are relative concepts describing the relative magnitude of the frequencies, but the absolute magnitude of the frequencies, i.e. the frequency range, is not limited in any sense.

The phase detector 120 may compare phases of the carrier signal and the reference clock signal output from the frequency divider 110 and output a phase indication signal. Here, the reference clock signal may be a clock signal recovered from the NFC reader, and the phase tracking loop 100 is used to keep the phase of the carrier signal consistent with the phase of the reference clock signal.

The phase tuning module 130 may adjust the phase of the high frequency clock signal provided to the divider 110 based on the phase indication signal output by the phase detector 120 such that the phase of the carrier signal output by the divider 110 tracks/is closer to the phase of the reference clock signal.

The division ratio control module 140 may adjust the division ratio of the frequency divider 110 based on the phase indication signal output by the phase detector 120 to thereby rapidly adjust the phase of the carrier signal, as will be described in further detail below.

Fig. 2 illustrates an exemplary embodiment of phase tracking loop 100, wherein an exemplary configuration of phase tuning module 130 and divide ratio control module 140 is shown. Referring to fig. 2, the phase tuning module 130 may include a Digital Loop Filter (DLF) 132 and a multi-phase clock selection unit 134, and may optionally further include a coefficient control unit 136. The frequency division ratio control module 140 may include a dynamic detection adjustment unit 142 and a frequency division ratio control unit 144.

The phase detector 120 may be a binary phase detector (BBPD), and the phase detector 120 may output a high level "1" when the phase of the carrier signal (or referred to as the divided clock signal) is advanced from the phase of the reference clock signal; when the phase of the carrier signal lags the phase of the reference clock signal, the phase detector 120 may output a low level "-1", or vice versa. When the enable signal of the phase detector 120 is off (e.g., en=0, not shown), the phase detector 120 may output 0.

A Digital Loop Filter (DLF) 132 may detect the phase indication signal output by the phase detector 120 and control the multiphase clock selection unit 134 to select a clock signal of an appropriate phase from among the multiphase clock signals based on the relative phases of the carrier signal and the reference clock signal it indicates. For example, when the phase detector 120 indicates that the phase of the carrier signal is advanced from the phase of the reference clock signal, the digital loop filter 132 may instruct the multiphase clock selection unit 134 to select a clock signal having a more retarded phase from among the multiphase clock signals; when the phase detector 120 indicates that the phase of the carrier signal lags the phase of the reference clock signal, the digital loop filter 132 may instruct the multiphase clock selection unit 134 to select a clock signal having a more advanced phase from among the multiphase clock signals. When the phase indication signal output by the phase detector 120 indicates that the phase of the carrier signal transitions back and forth between leading and lagging phases of the reference clock signal, the clock signal selected by the multiphase clock selection unit 134 transitions back and forth between the two signals, which is generally equivalent to a constant phase, and the loop reaches a locked state.

Fig. 3 shows a schematic diagram of a digital loop filter 200 according to an embodiment of the invention, and the digital loop filter 200 may be implemented as the digital loop filter 132 shown in fig. 2.

Referring to fig. 3, the digital loop filter 200 may include a proportional path 210 and an integral path 220 that receive as inputs the phase indication signal output by the phase detector 120 at a first input port In-1. The proportional path 210 and the integral path 220 may generate a first proportional signal at a first proportion "a" to the phase indication signal and a second proportional signal at a second proportion "p" to the phase indication signal, respectively. For example, the proportional path 210 may include a first register 212 in which a first proportional coefficient "a" is stored to output a first proportional signal; the integrating path 220 may include a second register 222 in which a second scaling factor "p" is stored to output a second scaling signal. For example, when the output of the phase detector 120 is "1", the first proportional signal generated by the proportional path 210 is "a", and the second proportional signal generated by the integral path 220 is "p"; when the output of the phase detector 120 changes from "1" to "-1", the first proportional signal changes from "a" to "-a" and the second proportional signal changes from "p" to "-p" by a change of "-2a" and a change of "-2 p". Similarly, when the output of the phase detector 120 changes from "-1" to "1", the first proportional signal produces a change in "+2a" from "-a" to "a", and the second proportional signal produces a change in "+2p" from "-p" to "p".

In an embodiment, the first scaling signal generated by scaling path 210 and the second scaling signal generated by integrating path 220, or the first scaling factor "a" and the second scaling factor "p", may also be adjusted. For example, the scaling path 210 may include a first scaling unit, such as a multiplier 214, that multiplies the first scaling signal using an adjustment factor to generate an adjusted first scaling signal; the integrating path 220 may include a second scaling unit, such as a multiplier 224, that multiplies the second scaling signal using an adjustment factor to generate an adjusted second scaling signal. In the embodiment shown In fig. 3, the first and second scaling units 214 and 224 receive the same scaling factor from the second input port In-2, thereby performing an equal scaling of the first and second scaling signals. In other embodiments, the first and second scaling units 214 and 224 may also receive different adjustment factors to differently adjust the first and second scaling signals, or only one of the first and second scaling units 214 and 224 may be provided to adjust one of the first and second scaling signals.

The adjusted second proportional signal may be subjected to an integration process in integrator 226 to generate an integrated signal. The integrator 226 may receive the integration clock signal from the third input port In-3 to integrate the adjusted second proportional signal according to the integration clock.

Then, the integrated signal output by the integrator 226 of the integrating path 220 and the first proportional signal output by the proportional path 210 may perform addition processing in the adder 232 to obtain a sum value of the two, and the sum value may be subjected to a remainder operation with respect to a predetermined value M in the remainder (Mod) unit 234, thereby generating a clock selection indication signal representing the remainder, which is output at the output port Out. When the signal output from the phase detector 120 is "1", the integral value output from the integrator 226 gradually increases, and the remainder value indicated by the clock selection indication signal output from the remainder unit 234 increases from 0 to 1 after a predetermined period, then increases to 2 again after the predetermined period, increases to M-1, and then increases back to 0 again, thus cyclically changing. In contrast, if the signal output from the phase detector 120 is "-1", the integrated value output from the integrator 226 gradually decreases, and the remainder value indicated by the clock selection indication signal output from the remainder unit 234 decreases from 0 to M-1 after a predetermined period, then decreases to M-2, and decreases to 0, thus cyclically decreasing. Here, the remainder value indicated by the clock selection instruction signal is used as an index for the multiphase clock selection unit 134 to select a clock signal corresponding to the index value from the M clock signals of different phases.

In some embodiments, the proportional path 210 may be omitted, and only the integral path 220 may be used, and the clock selection indication signal including the index value (i.e., remainder) may be generated for selecting a corresponding clock signal from the M multiphase clock signals. It will be appreciated that by providing the proportional path 210, which corresponds to introducing a reference zero in the loop, the loop is prevented from ringing and generating noise. Thus, the phase tracking loop 100 may have improved phase noise performance after introducing the proportional path 210.

Referring back to fig. 2, the multiphase clock selection unit 134 selects one clock signal from the M clock signals of different phases based on the clock selection instruction signal output from the digital loop filter 132. The M clock signals of different phases may have a phase difference of 360 °/M, for example, when m=12, the phases of the M clock signals may be 0 °, 30 °, 60 °, 90 °, 120 °, 150 °, 180 °, 210 °, 240 °, 270 °, 300 °, and 330 °, respectively.

For example, when the output of the phase detector 120 is "1", it indicates that the phase of the carrier signal (i.e., the divided signal) provided by the frequency divider 110 is advanced from the phase of the reference clock signal. At this time, as the integrated value output from the integrator 226 gradually increases, the remainder represented by the clock selection instruction signal output from the digital loop filter 132 gradually increases, so that the multi-phase clock selection unit 134 selects a clock signal with a more retarded phase from among the M (M is an integer greater than 1) clock signals, and thus the phase of the carrier signal supplied from the frequency divider 110 also moves backward. When the phase of the carrier signal becomes more retarded than the phase of the reference clock signal, the output of the phase detector 120 becomes "-1". At this time, the integrated value output from the integrator 226 gradually decreases, and the remainder indicated by the clock selection instruction signal output from the digital loop filter 132 also gradually decreases, so that the multi-phase clock selection unit 134 selects a clock signal whose phase is more advanced from the M clock signals, and thus the phase of the carrier signal supplied from the frequency divider 110 also moves forward. When the output of the phase detector 120 varies back and forth between "1" and "-1", indicating that the clock signal selected by the multiphase clock selection unit 134 varies between a clock signal that is phase-advanced from the reference clock signal and a clock signal that is phase-retarded from the reference clock signal, the overall equivalent is that the phase of the carrier signal is equal to or closest to the phase of the reference clock signal, and the loop reaches a locked state.

Here, the phase step between the M clock signals selected by the multiphase clock selection unit 134 is 360 °/M, but when the frequency divider 110 performs the frequency division process, the phase step (i.e., the phase difference) between adjacent divided signals becomes 360 °/(m×n), where N is the frequency division ratio of the frequency divider 110, because the pulse width of the divided signal is N times the pulse width of the clock signal before the frequency division. For example, the signal frequency of the NFC reader is 13.56MHz, the frequency of the multiphase clock signal is 867.84MHz, and the frequency divider 110 with the frequency division ratio of n=64 may be used. Of course, other frequency division ratios may be used, such as a frequency division ratio of n=40 when the frequency of the multiphase clock signal is 542.4 MHz.

If m=12, the phase steps between the multiphase clock signals are 30 °, the phase steps of the divided signals become 0.46875 °, so that accurate phase adjustment and tracking can be achieved. When the index value represented by the clock selection instruction signal increases from 0 to 11, the phase of the clock signal selected by the multiphase clock selection unit 134 is retarded by 330 °, and the phase of the clock signal after frequency division is retarded by 5.15625 °; then the index value changes from 11 to 0, the phase of the clock signal selected by the multiphase clock selection unit 134 continues to be delayed by 30 °, and the phase of the divided clock signal continues to be delayed by 0.46875 °. Similarly, cyclically reducing the index value may cause the phase of the divided signal to be continually shifted forward. In this way, the phase of the divided signal (i.e., the carrier signal) can be changed over a wide range.

This scheme greatly improves the accuracy of the phase adjustment, i.e., the phase tracking accuracy of the phase tracking loop 100, by employing a frequency division process. However, the speed of adjusting the phase is slow, and the step of each adjustment is 360 °/(m×n), so it may take a long time to achieve loop lock. In order to shorten the lock time, the embodiment of the present invention also increases the phase adjustment speed by adjusting the frequency division ratio N of the frequency divider 110.

Fig. 4 schematically shows a schematic diagram of the adjustment of the phase by changing the frequency division ratio. Referring to fig. 4, it is assumed that the frequency division ratio n=64 of the system design, where the high level and the low level correspond to 32 pulses of the high frequency clock signal before frequency division, respectively. Here, the design frequency division ratio is a frequency division ratio such that the frequency of the carrier signal is equal to the frequency of the reference clock signal, and thus the design frequency division ratio is also referred to as a base frequency division ratio. When the frequency division ratio is changed from 64 to 63, then the start of the 63-divided signal of the next period is advanced by one short/high frequency pulse from the start of the 64-divided signal, that is, 1/64 of the period of the 64-divided signal, and thus the phase is advanced by 360 °/64=5.625 °; the next cycle, the frequency divided signal 63 is 11.25 degrees earlier than the frequency divided signal 64, and so on. When the division ratio is changed from 64 to 65, then the start of the 65 divided signal of the next period is one short/high frequency pulse after the start of the 64 divided signal, that is, 1/64 of the period of the 64 divided signal, and thus the phase is retarded by 360 °/64=5.625 °; the next cycle, the divide by 65 signal is phase retarded by 11.25 from the divide by 64 signal, and so on. It will be appreciated that when the division ratio is changed from N to n±x, the value of x may be set as desired, as compared to (360×x)/N, which is a step forward or backward. Therefore, by changing the frequency division ratio, the phase of the carrier signal can be quickly adjusted, thereby increasing the phase adjustment speed.

Referring back to fig. 2, the dynamic detection adjustment unit 142 may detect the phase indication signal generated by the phase detector 120 and generate the frequency division ratio adjustment signal. The frequency division ratio control unit 144 may control the frequency division ratio of the frequency divider 110 based on the frequency division ratio adjustment signal provided by the dynamic detection adjustment unit 142. In an embodiment, the division ratio of divider 110 may be set to a plurality of gears, an example of which is shown in fig. 5. Fig. 5 shows a total of four gears 0-3, but more or fewer gears may be used, such as two gears, three gears, five gears, etc. Gear 0, also referred to as a base gear, corresponds to a base frequency division ratio N. The frequency division ratio of the higher gear is N+/-x, and the higher the gear is, the larger the value of x is, wherein N and x are positive integers, and N is larger than x. For example, the frequency division ratio for gear 1 may be n±1, the frequency division ratio for gear 2 may be n±2, the frequency division ratio for gear 3 may be n±3, and so on. When the phase indication signal indicates that the phase of the carrier signal is advanced from the phase of the reference clock signal, the frequency division ratio of the gear may be n+x to use a larger frequency division ratio so that the phase of the carrier signal is retarded; when the phase indication signal indicates that the phase of the carrier signal lags the phase of the reference clock signal, the frequency division ratio of the gear may be N-x to use a smaller frequency division ratio so that the phase of the carrier signal is advanced.

In an embodiment, when the phase detector 120 indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal (the phase indication signal is "1" or "-1") and lasts for a predetermined number of periods, indicating that the phase difference between the carrier signal and the reference clock signal is large, the dynamic detection adjustment unit 142 may generate a first division ratio adjustment signal, and the division ratio control unit 144 may increase the division ratio of the frequency divider 110 in response to the first division ratio adjustment signal. This operation may be repeated to continuously increase the phase adjustment step of the carrier signal until the highest gear is reached. When the phase detector 120 indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal (the phase indication signal jumps between "1" and "-1") and jumps up to a predetermined number of times, indicating that the phase of the carrier signal has been adjusted around the phase of the reference clock signal, the dynamic detection adjustment unit 142 may generate a second frequency division ratio adjustment signal, and the frequency division ratio control unit 144 decreases the frequency division gear of the frequency divider 110 in response to the second frequency division ratio adjustment signal to decrease the phase adjustment step of the carrier signal until the base gear is reached. It will be appreciated that dynamic detection adjustment unit 142, in addition to directing frequency division ratio control unit 144 to frequency division ratio adjustment signal to increase or decrease the frequency division gear of frequency divider 110, directs frequency division ratio control unit 144 to the current carrier signal phase state, i.e., whether to advance or retard the phase of the reference clock signal, so that frequency division ratio control unit 144 can control whether the frequency division ratio of frequency divider 110 at each frequency division gear is n+x or N-x.

The following exemplifies the adjustment process of the frequency division shift stage. For example, initially, divider 110 is in the base gear, at which time the division ratio is 64. When the dynamic detection adjustment unit 142 detects that the output of the phase detector 120 is "1" and continues for, for example, 4 cycles, it instructs the division ratio control unit 144 to increase the division ratio of the frequency divider 110 to the gear 1, at which time the division ratio of the frequency divider 110 becomes 65. When the dynamic detection adjustment unit 142 again detects that the output of the phase detector 120 is still "1" and continues for, for example, 4 cycles, it instructs the division ratio control unit 144 to increase the division ratio of the frequency divider 110 to the gear 2, at which point the division ratio of the frequency divider 110 becomes 66. This operation may be repeated until the frequency divider 110 reaches the highest gear 3, at which point the frequency division ratio of the frequency divider 110 becomes 67 and the phase adjustment step reaches the maximum. Through the above operation, the phase of the carrier signal is continuously shifted backward, and when it becomes later than the phase of the reference clock signal, the output of the phase detector 120 is changed from "1" to "-1", while the frequency divider 110 is still kept at the highest gear 3, but the frequency division ratio is changed from 67 to 61, the phase of the carrier signal is shifted forward, resulting in that the phase thereof again becomes earlier than the phase of the reference clock signal, the output of the phase detector 120 is changed from "-1" to "1", and the frequency division ratio of the frequency divider 110 is changed from 61 to 67. When the dynamic detection adjustment unit 142 detects that the output of the phase detector 120 jumps between "1" and "-1" a predetermined number of times, for example, 6 times, it instructs the division ratio control unit 144 to decrease the division gear of the frequency divider 110, changing from gear 3 to gear 2, the phase adjustment step decreases. This operation may be repeated until divider 110 reaches the base gear, the division ratio is 64, at which point the division ratio no longer affects the phase of the carrier signal, and the frequency of the carrier signal is equal to the reference clock signal.

In addition to controlling the phase adjustment speed by the frequency division ratio, it will be appreciated that the phase adjustment speed also depends on the speed at which the digital loop filter 132 changes its output clock selection indication signal, i.e., the speed at which the sum value output by the adder 232 changes, in accordance with the phase indication signal output by the phase detector 120. It is understood that when the first scaling factor a and the second scaling factor p become larger, the rate of change of the sum value output by the adder 232 also increases. Thus, by adjusting at least one of the first scaling factor a and the second scaling factor p, preferably at least the second scaling factor p (since it can change the sum value output by the adder 232 more quickly by an integration operation), the phase adjustment speed can be changed.

With continued reference to fig. 2, the coefficient control unit 136 may control the magnitude of the adjustment coefficient provided to the second input port In-2 of the digital loop filter 132/200 for adjusting at least one of the first scaling coefficient a and the second scaling coefficient p. For example, when the dynamic detection adjustment unit 142 detects that the phase detector 120 indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal (the phase indication signal is "1" or "-1") and continues for a predetermined number of cycles (which may be the same or different from the number of cycles used for the frequency division control), the dynamic detection adjustment unit 142 may generate a first coefficient adjustment signal, and the coefficient control unit 136 may increase the adjustment coefficient in response to the first coefficient adjustment signal to increase at least one of the first and second scaling coefficients a and p, thereby increasing the phase adjustment speed. This operation may be repeated until the maximum scaling factor is reached. When the dynamic detection adjustment unit 142 detects that the phase detector 120 indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal (the phase indication signal jumps between "1" and "-1") and the jump reaches a predetermined number of times (which may be the same or different from the number of jumps used for frequency division control), the dynamic detection adjustment unit 142 may generate a second coefficient adjustment signal, and the coefficient control unit 136 may decrease the adjustment coefficient in response to the second coefficient adjustment signal to decrease at least one of the first scaling coefficient a and the second scaling coefficient p, thereby decreasing the phase adjustment speed until the base ratio is reached. It will be appreciated that increasing and decreasing the scaling factors a and p may change the phase adjustment speed, but does not affect the phase adjustment accuracy.

The phase adjustment speed control by frequency division ratio adjustment and the phase adjustment speed control by scaling factor adjustment may be used in combination. It will be appreciated that the phase adjustment steps caused by the frequency division ratio change of the frequency divider 110 are generally much larger than the phase adjustment steps caused by the clock selection indication signal change of the digital loop filter 132, and thus the frequency division ratio adjustment of the frequency divider 110 may be referred to as coarse adjustment, and the scaling factor adjustment of the digital loop filter 132 may be referred to as fine adjustment. In an embodiment, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit 142 may generate the first coefficient adjustment signal to increase at least one of the first and second proportional coefficients a and p until the maximum proportional coefficient is reached, and then generate the first division ratio adjustment signal to increase the division gear of the frequency divider 110 until the highest gear is reached. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and jumps by a predetermined number of times, the dynamic detection adjustment unit 142 may generate the second division ratio adjustment signal to lower the division gear of the frequency divider 110 until the base gear is reached, and then generate the second coefficient adjustment signal to reduce the at least one of the first scaling factor a and the second scaling factor p until the base ratio is reached.

Although the above description has been made taking the example in which the phase tuning module 130 includes the digital loop filter 132 and the multiphase clock selection unit 134, it should be understood that the present invention is not limited thereto. The phase tuning module 130 may be implemented as any module or device that can adjust the phase of the clock signal, and the coefficient control unit 136 may be omitted.

Fig. 6 shows a flow chart of a phase tracking method 300 according to an embodiment of the invention. The method 300 may be implemented using the phase tracking loop 100 described above with reference to fig. 1-5. Referring to fig. 6, the phase tracking method 300 may include: step 310, frequency division processing is performed on the clock signal to obtain a carrier signal; step 320, comparing the phases of the carrier signal and the reference clock signal to generate a phase indication signal; and step 330 of adjusting the phase of the clock signal and the frequency division ratio of the frequency division process based on the phase indication signal so that the phase of the carrier signal is closer to the phase of the reference clock signal.

Fig. 7 shows a flowchart of a frequency-divided gear adjustment process according to an embodiment of the present invention, which can be applied in step 330 of the method 300 shown in fig. 6. In one embodiment, the frequency division process may have a base gear with a base frequency division ratio N and at least one higher gear with a higher frequency division ratio n+x or a lower frequency division ratio N-x, where N is a predetermined positive integer, x is a smaller positive integer than N and the higher the gear, the larger the value of x. When the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, the higher gear has a higher frequency division ratio n+x; when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal, the higher gear has a lower frequency division ratio N-x. The base frequency division ratio N is such that the frequency of the carrier signal obtained after frequency division is equal to the frequency of the reference clock signal.

Referring to fig. 7, adjusting the frequency division ratio of the frequency division process based on the phase indication signal may include: in step 331, it is determined whether the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and jumps up to a predetermined number of times based on the phase indication signal. If yes (Y), the frequency division gear of the frequency division process is lowered in step 333. Steps 331 and 333 may be repeated until the assigned gear reaches the base gear.

If it is determined in step 331 that the transition has not occurred or the transition has not reached a predetermined number of times, it is determined in step 335 whether the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and for a predetermined period. If it is determined that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for the predetermined period, the frequency division gear of the frequency division process may be increased in step 337. Steps 335 and 337 may be repeatedly performed until the frequency division gear of the frequency division process reaches the highest gear.

Fig. 8 shows a flow chart of a clock phase adjustment process according to an embodiment of the invention, which can be applied in step 330 of the method 300 shown in fig. 6. Referring to fig. 8, adjusting the phase of the clock signal based on the phase indication signal may include: at step 332, generating a selection indication signal based on the phase indication signal; and selecting one clock signal from the multiphase clock signals based on the selection indication signal at step 334. Wherein the generated selection indication signal may indicate that a clock signal having a phase more retarded than a currently selected clock signal is selected from the multiphase clock signals when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal. When the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal, the generated selection indication signal may indicate that one of the multiphase clock signals is selected to be more advanced than the currently selected clock signal.

Fig. 9 shows a flowchart of a method of generating a clock selection indication signal according to an embodiment of the invention, which may be applied in step 332 shown in fig. 8, for example. Referring to fig. 9, at step 412, a first proportional signal may be generated that is a first proportion to the phase indication signal; at step 414, a second ratio signal may be generated that is a second ratio to the phase indication signal.

Optionally, in step 416, at least one of the first ratio and the second ratio may also be adjusted based on the phase indication signal. For example, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, at least one of the first ratio and the second ratio may be increased until the maximum ratio is reached. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, at least one of the first ratio and the second ratio may be reduced until the base ratio is reached.

With continued reference to fig. 9, at step 418, the second proportional signal may be integrated to obtain an integrated signal. The first proportional signal and the integral signal may then be summed 420 to obtain a sum of the two. At step 422, the sum may be subjected to a remainder operation with respect to a predetermined value to generate the selection indication signal. The predetermined value may be equal to the number of clock signals having different phases included in the multiphase clock signals to be selected.

Fig. 10 shows a flowchart of a coefficient and frequency shift adjustment process according to an embodiment of the present invention, in which the execution sequence of the coefficient adjustment and frequency shift adjustment is shown. Referring to fig. 10, in step 501, it may be determined whether the phase of the carrier signal hops between being more advanced and more retarded than the phase of the reference clock signal and up to a predetermined number of times based on the phase indication signal. If no transitions occur or the transitions do not reach a predetermined number of times, a determination is made at step 503 as to whether the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period. If it is not detected that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal by a predetermined period, the scaling factor of the digital loop filter and the frequency division gear of the frequency divider may be maintained at step 521 and then returned to step 501.

If it is determined at step 503 that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal by a predetermined period, it may be determined at step 505 whether the scaling factor (first scaling factor and/or second scaling factor) of the digital loop filter to be adjusted reaches a maximum value. If the maximum value has not been reached, the scaling factor of the digital loop filter to be adjusted may be increased in step 507 and then returned to step 501.

If it is determined at step 505 that the scaling factor of the digital loop filter to be adjusted has reached a maximum value, then a determination may be made at step 509 as to whether the frequency division gear of the frequency divider has reached a maximum gear. If the maximum gear has not been reached, the frequency division gear of the frequency divider may be increased in step 511 and then step 501 is returned. If the frequency division level of the frequency divider has reached the maximum level, the scaling factor of the digital loop filter and the frequency division level of the frequency divider may be maintained at step 521 and then returned to step 501.

On the other hand, if it is determined at step 501 that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and jumps up to a predetermined number of times, it may be determined at step 513 whether the frequency-dividing gear of the frequency divider is in the lowest/base gear. If the frequency divider's frequency division ratio is not the lowest ratio, then the frequency divider's frequency division ratio may be reduced at step 515 and then returned to step 501.

If it is determined at step 513 that the frequency division gear of the frequency divider is at the lowest gear, it may be determined at step 517 whether the scaling factor (first scaling factor and/or second scaling factor) of the digital loop filter to be adjusted is at a minimum. If not, the scaling factor of the digital loop filter to be adjusted may be reduced in step 519 and then returned to step 501. If the scaling factor of the digital loop filter to be adjusted is already at a minimum, the scaling factor of the digital loop filter and the frequency divider's frequency division gear may be left unchanged at step 521 and then return to step 501.

The embodiments of the phase tracking loop and the phase tracking method of the present invention have been described above with reference to the accompanying drawings, and it can be seen that the phase tracking loop and the phase tracking method of the present invention can achieve fast and high-precision phase locking over a large phase difference range and have improved phase noise performance. For example, taking the case where the frequency division ratio n=64 and the multiphase clock signal have a 30 ° phase difference (m=12), the conventional phase adjustment step is 0.46875 °, and if there is a 180 ° phase difference between the carrier signal and the reference clock signal, the phase lock time is typically around 100 μs. If there is a certain frequency deviation between the carrier signal and the reference clock signal, the phase lock time is above 100 mus. By using the dynamic detection and adjustment technology of the invention, the dynamic adjustment of the frequency division ratio can be started in the initial stage of phase tracking, the phase adjustment step is improved ten times according to the frequency division ratio adjustment gear number, and the locking time is greatly shortened. And the frequency dividing ratio is reduced to adjust the gear when the lock is closed until the lock is deactivated, and the stepping is restored to 0.46875 degrees, so that the phase adjustment precision is not lost. The overall settling time can be reduced to within 10 us.

Fig. 11 shows a schematic diagram of an electronic device 600 according to an embodiment of the invention. The electronic device 600 may include a phase tracking loop 620 in accordance with an embodiment of the present invention. For example, the electronic device 600 may have an NFC module 610 that may operate in a card emulation mode. NFC module 610 may include a phase tracking loop 620 to track the phase of the signal of the NFC reader. Examples of such an electronic device 600 include, but are not limited to, a cell phone, tablet, portable personal digital assistant, wearable electronic device, and the like.

The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not intended to be limiting, and these advantages, benefits, effects, etc. are not to be considered as essential to the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not necessarily limited to practice with the above described specific details.

The block diagrams of the devices, apparatuses, devices, systems referred to in the present application are only illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.

It is also noted that in the apparatus, devices and methods of the present application, the components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered as equivalent aspects of the present application.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit embodiments of the application to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.

Claims

1. A phase tracking loop, comprising:

the frequency divider is used for carrying out frequency division processing on the clock signal to obtain a carrier signal;

A phase detector for comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal;

a frequency division ratio control module for adjusting a frequency division ratio of the frequency divider based on the phase indication signal; and

a phase tuning module for adjusting the phase of the clock signal based on the phase indication signal,

the frequency divider performs frequency division processing on the clock signal based on the frequency division ratio adjusted by the frequency division ratio control module.

2. The phase tracking loop of claim 1, wherein the phase detector is a binary phase detector that outputs a first indication signal when the phase of the carrier signal is advanced relative to the phase of the reference clock signal, and outputs a second indication signal when the phase of the carrier signal is retarded relative to the phase of the reference clock signal.

3. The phase tracking loop of claim 1, wherein the divide ratio control module comprises:

a dynamic detection adjustment unit for detecting the phase indication signal generated by the phase detector and generating a frequency division ratio adjustment signal; and

and the frequency dividing ratio control unit is used for controlling the frequency dividing ratio of the frequency divider based on the frequency dividing ratio adjustment signal.

4. The phase tracking loop of claim 3 wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and for a predetermined period, the dynamic detection adjustment unit generates a first division ratio adjustment signal, the division ratio control unit increases the division gear of the frequency divider in response to the first division ratio adjustment signal until a highest gear is reached,

when the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates a second division ratio adjustment signal, the division ratio control unit decreases the division gear of the frequency divider in response to the second division ratio adjustment signal until reaching a base gear,

the frequency divider has the basic gear having a basic frequency division ratio N, and at least one higher gear having a higher frequency division ratio n+x or a lower frequency division ratio N-x, N being a preset positive integer, x being a smaller positive integer than N and the higher the gear, the larger the value of x, the higher gear having the higher frequency division ratio n+x when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and the higher gear having the lower frequency division ratio N-x when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

5. The phase tracking loop of claim 4 wherein the base divide ratio N is such that the frequency of the carrier signal is equal to the frequency of the reference clock signal.

6. The phase tracking loop of claim 4 wherein the phase tuning module comprises:

a digital loop filter for generating a selection indication signal based on the phase indication signal; and

and the multiphase clock selection unit is used for selecting one clock signal from multiphase clock signals based on the selection indication signal.

7. The phase tracking loop of claim 6 wherein said multiphase clock signal comprises M clock signals of different phases, M being an integer greater than one,

the selection indication signal generated by the digital loop filter indicates one of M index values to instruct the multiphase clock selection unit to select a corresponding clock signal from the M clock signals of different phases.

8. The phase tracking loop of claim 6, wherein the selection indication signal generated by the digital loop filter instructs the multiphase clock selection unit to select one of the multiphase clock signals having a phase that is later than a currently selected clock signal when the phase indication signal generated by the phase detector indicates that the phase of the carrier signal is advanced from the phase of the reference clock signal for a predetermined period,

When the phase indication signal generated by the phase detector indicates that the phase of the carrier signal lags behind the phase of the reference clock signal and lasts for a predetermined period, the selection indication signal generated by the digital loop filter indicates that the multiphase clock selection unit selects one clock signal from the multiphase clock signals, which is more advanced than the currently selected clock signal.

9. The phase tracking loop of claim 6, wherein the digital loop filter comprises:

a proportional path for generating a first proportional signal that is a first proportion to the phase indication signal;

an integration path for generating a second proportion signal in a second proportion to the phase indication signal, and performing integration processing on the second proportion signal to generate an integration signal;

an adder for adding the first proportional signal and the integral signal to output a sum of the two; and

and a remainder unit for performing a remainder operation on the sum value received from the adder with respect to a predetermined value to generate the selection instruction signal representing a remainder.

10. The phase tracking loop of claim 9, wherein the predetermined value is equal to a number of clock signals having different phases included in the multiphase clock signal.

11. The phase tracking loop of claim 9, wherein the digital loop filter further comprises at least one of:

a first proportion adjusting unit provided in the proportion path for adjusting the first proportion; and

and a second proportion adjusting unit arranged in the integrating path and used for adjusting the second proportion.

12. The phase tracking loop of claim 11, wherein the first and second scaling units use the same scaling factor to perform an equal scaling of the first and second scales.

13. The phase tracking loop of claim 11, further comprising:

a coefficient control unit for controlling an adjustment coefficient for adjusting at least one of the first ratio and the second ratio,

wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit generates a first coefficient adjustment signal, the coefficient control unit increases the adjustment coefficient in response to the first coefficient adjustment signal to increase the at least one of the first proportion and the second proportion until a maximum proportion is reached,

When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates a second coefficient adjustment signal, and the coefficient control unit decreases the adjustment coefficient in response to the second coefficient adjustment signal to decrease the at least one of the first proportion and the second proportion until a base proportion is reached.

14. The phase tracking loop of claim 13 wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and for a predetermined period, the dynamic detection adjustment unit first generates the first coefficient adjustment signal to increase the at least one of the first and second ratios until a maximum ratio is reached, then generates the first division ratio adjustment signal to increase the divided gear of the divider until a highest gear is reached,

when the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates the second division ratio adjustment signal to reduce the division gear of the frequency divider until a base gear is reached, and then generates the second coefficient adjustment signal to reduce the at least one of the first ratio and the second ratio until a base ratio is reached.

15. A phase tracking method, comprising:

frequency division processing is carried out on the clock signal to obtain a carrier signal;

comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal;

adjusting the phase of the clock signal and the frequency division ratio of the frequency division process based on the phase indication signal so that the phase of the carrier signal is closer to the phase of the reference clock signal,

wherein the frequency division processing of the clock signal is performed using a frequency division ratio adjusted based on the phase indication signal.

16. The method of claim 15, wherein adjusting the division ratio of the division process based on the phase indication signal comprises:

when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, increasing the frequency division gear of the frequency division process until the highest gear is reached; or alternatively

When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the frequency-divided gear of the frequency-dividing process is lowered until a base gear is reached,

The frequency division process has the basic gear and at least one higher gear, the basic gear has a basic frequency division ratio N, the higher gear has a higher frequency division ratio n+x or a lower frequency division ratio N-x, N is a preset positive integer, x is a smaller positive integer than N, and the higher the gear is, the larger the value of x is, the higher gear has the higher frequency division ratio n+x when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and the higher gear has a lower frequency division ratio N-x when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

17. The method of claim 16, wherein the base divide ratio N is such that the frequency of the carrier signal is equal to the frequency of the reference clock signal.

18. The method of claim 16, wherein adjusting the phase of the clock signal based on the phase indication signal comprises:

generating a selection indication signal based on the phase indication signal; and

selecting one clock signal from the multiphase clock signals based on the selection indication signal,

wherein the selection indication signal indicates that one of the multiphase clock signals is selected to be more retarded than the currently selected clock signal when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and indicates that one of the multiphase clock signals is selected to be more advanced than the currently selected clock signal when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

19. The method of claim 18, wherein generating a selection indication signal based on the phase indication signal comprises:

generating a first proportional signal in a first proportion to the phase indication signal;

generating a second proportion signal which is in a second proportion with the phase indication signal;

integrating the second proportional signal to obtain an integrated signal;

performing addition operation on the first proportional signal and the integral signal to obtain a sum of the first proportional signal and the integral signal;

and taking the sum value for a remainder operation with respect to a preset value to generate the selection indication signal.

20. The method of claim 19, wherein the predetermined value is equal to a number of clock signals having different phases included in the multiphase clock signal.

21. The method of claim 19, further comprising:

at least one of the first ratio and the second ratio is adjusted based on the phase indication signal.

22. The method of claim 21, wherein adjusting at least one of the first ratio and the second ratio comprises:

increasing said at least one of said first and second ratios until a maximum ratio is reached when said phase indication signal indicates that the phase of said carrier signal is more advanced or more retarded than the phase of said reference clock signal and for a predetermined period; or alternatively

When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the at least one of the first ratio and the second ratio is reduced until a base ratio is reached.

23. The method of claim 22, wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the at least one of the first ratio and the second ratio is increased first until a maximum ratio is reached, and then the divided gear of the divided process is increased again until a highest gear is reached; or alternatively

When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the frequency division gear of the frequency division process is first lowered until a base gear is reached, and then the at least one of the first ratio and the second ratio is reduced until the base ratio is reached.

24. An electronic device comprising the phase tracking loop of any one of claims 1-14.