CN115441866A

CN115441866A - Phase tracking loop and method based on frequency division acceleration and electronic equipment

Info

Publication number: CN115441866A
Application number: CN202211129272.2A
Authority: CN
Inventors: 刘览琦; 把傲; 柯毅; 刘德珩
Original assignee: Wuhan Silicon Integrated Co Ltd
Current assignee: Wuhan Silicon Integrated Co Ltd
Priority date: 2022-09-16
Filing date: 2022-09-16
Publication date: 2022-12-06
Anticipated expiration: 2042-09-16
Also published as: CN115441866B

Abstract

The invention relates to a phase tracking loop and a method based on frequency division acceleration and an electronic device. A phase tracking loop may include: a frequency divider for performing frequency division processing on the clock signal to obtain a carrier signal; a phase detector for comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal; a division ratio control module for adjusting the division ratio of the frequency divider based on the phase indication signal; and a phase tuning module for adjusting a phase of the clock signal based on the phase indication signal.

Description

Phase tracking loop and method based on frequency division acceleration and electronic equipment

Technical Field

The invention relates to a phase tracking loop and a method based on frequency division acceleration and an electronic device.

Background

In the field of wireless communications, it is sometimes desirable to perform phase tracking on a received signal. For example, in a Near Field Communication (NFC) scenario, since amplitude modulation is used, the card reader needs to track the phase of the signal read from the NFC card, and when the phase difference between the two is large, amplitude information may be lost. The signal read by the card reader from the NFC card is a signal generated by load modulation performed by the NFC card, and the NFC card can generally adopt one of two schemes, namely Passive Load Modulation (PLM) and Active Load Modulation (ALM). When a passive load modulation scheme is adopted, the NFC card completely depends on a radio frequency signal provided by a card reader to generate a passive read signal, so that there is no phase difference, but the generated passive read signal has small energy, the communication distance is limited, and the NFC card is easily interfered. When an active load modulation scheme is employed, an NFC device (e.g., a cell phone) in a card emulation role can emulate the load modulation process, actively transmitting a carrier signal that is in phase with the reader device. Active load modulation schemes can provide greater signal power and better interference rejection characteristics, but phase skew problems may exist due to the different sources of the carrier signal actively transmitted by the NFC device and the reader signal.

Disclosure of Invention

The present invention generally provides a fractional acceleration-based phase tracking loop and method, and an electronic device including such a phase tracking loop, which is capable of tracking a target phase quickly and with high accuracy over a large phase difference range.

According to an embodiment, a phase tracking loop may comprise: a frequency divider for performing frequency division processing on the clock signal to obtain a carrier signal; a phase detector for comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal; a division ratio control module for adjusting the division ratio of the frequency divider based on the phase indication signal; and a phase tuning module for adjusting a phase of the clock signal based on the phase indication signal.

In one embodiment, the phase detector is a binary phase detector that outputs a first indication signal when the phase of the carrier signal is advanced with respect to the phase of the reference clock signal and outputs a second indication signal when the phase of the carrier signal is retarded with respect to the phase of the reference clock signal.

In one embodiment, the frequency division ratio control module includes: a dynamic detection adjusting unit, configured to detect the phase indication signal generated by the phase discriminator and generate a frequency division ratio adjusting signal; and a division ratio control unit for controlling the division ratio of the frequency divider based on the division ratio adjustment signal.

In one embodiment, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit generates a first division ratio adjustment signal, and the division ratio control unit increases the division step of the frequency divider in response to the first division ratio adjustment signal until the highest step is reached. When the phase indicating signal indicates that the phase of the carrier signal jumps between more advanced and more delayed than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates a second division ratio adjustment signal, and the division ratio control unit decreases the division step of the frequency divider in response to the second division ratio adjustment signal until a base step is reached. The frequency divider has the basic gear and at least one higher gear, the basic gear has a basic frequency dividing ratio N, the higher gear has a higher frequency dividing ratio N + x or a lower frequency dividing ratio N-x, N is a preset positive integer, x is a positive integer smaller than N, and the higher the gear is, the larger the value of x is, the higher gear has the higher frequency dividing ratio N + x when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and the higher gear has the lower frequency dividing ratio N-x when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

In one embodiment, the base division ratio N is such that the frequency of the carrier signal is equal to the frequency of the reference clock signal.

In one embodiment, the phase tuning module comprises: a digital loop filter for generating a selection indication signal based on the phase indication signal; and a multi-phase clock selection unit for selecting one clock signal from the multi-phase clock signals based on the selection indication signal.

In one embodiment, the multiphase clock signals include M clock signals of different phases, M being an integer greater than one. The selection indication signal generated by the digital loop filter represents one of the M index values to indicate to the multiphase clock selection unit to select a corresponding one of the M clock signals of different phases.

In one embodiment, the selection indication signal generated by the digital loop filter instructs the multiphase clock selection unit to select a clock signal from the multiphase clock signals that is more in phase lag than a currently selected clock signal when the phase indication signal generated by the phase detector indicates that the phase of the carrier signal is ahead of the phase of the reference clock signal for a predetermined period. When the phase detector generates a phase indication signal indicating that the phase of the carrier signal lags the phase of the reference clock signal for a predetermined period, the digital loop filter generates a selection indication signal indicating that the multiphase clock selection unit selects a clock signal from the multiphase clock signals that is more advanced in phase than the currently selected clock signal.

In one embodiment, the digital loop filter comprises: a proportional path for generating a first proportional signal in a first proportion to the phase indication signal; an integration path for generating a second proportional signal in a second proportion to the phase indicating signal and performing integration processing on the second proportional signal to generate an integrated signal; an adder for adding the first proportional signal and the integral signal to output a sum of the first proportional signal and the integral signal; and a remainder unit configured to perform a remainder operation on the sum value received from the adder with respect to a predetermined value to generate the selection indication signal representing a remainder.

In one embodiment, the predetermined value is equal to the number of clock signals having different phases included in the multiphase clock signals.

In an embodiment, the digital loop filter further comprises at least one of: a first proportion adjusting unit provided in the proportion path, for adjusting the first proportion; and a second proportion adjusting unit provided in the integration path, for adjusting the second proportion.

In one embodiment, the first proportion adjusting unit and the second proportion adjusting unit perform equal proportion adjustment on the first proportion and the second proportion by using the same adjusting coefficient.

In one embodiment, the phase tracking loop further comprises: a coefficient control unit for controlling an adjustment coefficient for adjusting at least one of the first proportion and the second proportion. The dynamic detection adjustment unit generates a first coefficient adjustment signal when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the coefficient control unit increasing the adjustment coefficient in response to the first coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates a second coefficient adjustment signal, and the coefficient control unit decreases the adjustment coefficient in response to the second coefficient adjustment signal to decrease the at least one of the first ratio and the second ratio until a base ratio is reached.

In one embodiment, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and lasts for a predetermined period, the dynamic detection adjustment unit first generates the first coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until the maximum ratio is reached, and then generates the first frequency division ratio adjustment signal to increase the frequency division step of the frequency divider until the highest step is reached. When the phase indicating signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit first generates the second division ratio adjustment signal to lower the division step of the frequency divider until a base step is reached, and then generates the second coefficient adjustment signal to decrease the at least one of the first ratio and the second ratio until the base ratio is reached.

According to an embodiment, a method of phase tracking may comprise: performing frequency division processing on the clock signal to obtain a carrier signal; comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal; adjusting the phase of the clock signal and the division ratio of the frequency division process based on the phase indication signal so that the phase of the carrier signal is closer to the phase of the reference clock signal.

In an embodiment, adjusting the division ratio of the division process based on the phase indication signal comprises: increasing the frequency division step of the frequency division process until the highest step is reached when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period; or when the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, decreasing the frequency division step of the frequency division process until the base step is reached. Wherein the frequency dividing process has the basic shift stage and at least one higher shift stage, the basic shift stage has a basic frequency dividing ratio N, the higher shift stage has a higher frequency dividing ratio N + x or a lower frequency dividing ratio N-x, N is a preset positive integer, x is a positive integer smaller than N and the higher shift stage, the larger the value of x, the higher shift stage has the higher frequency dividing ratio N + x when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and the higher shift stage has the lower frequency dividing ratio N-x when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

In an embodiment, adjusting the phase of the clock signal based on the phase indication signal comprises: generating a selection indication signal based on the phase indication signal; and selecting one clock signal from the multi-phase clock signals based on the selection indication signal. Wherein the selection indication signal indicates to select one of the multiphase clock signals having a phase more lagging than a currently selected clock signal when the phase indication signal indicates that the phase of the carrier signal is more leading than the phase of the reference clock signal; the selection indication signal indicates selection of a clock signal from the multiphase clock signals having a phase that is more advanced than a currently selected clock signal when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

In an embodiment, generating the selection indication signal based on the phase indication signal comprises: generating a first ratio signal in a first ratio to the phase indicating signal; generating a second proportion signal in a second proportion to the phase indication signal; integrating the second proportional signal to obtain an integrated signal; adding the first proportional signal and the integral signal to obtain a sum of the first proportional signal and the integral signal; and performing a remainder operation on the sum value with respect to a predetermined value to generate the selection indication signal.

In an embodiment, the method further comprises: adjusting at least one of the first and second ratios based on the phase indication signal.

In an embodiment, adjusting at least one of the first proportion and the second proportion comprises: increasing the at least one of the first and second ratios until a maximum ratio is reached when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal for a predetermined period; or decreasing said at least one of said first and second ratios until a base ratio is reached when said phase indication signal indicates that the phase of said carrier signal transitions between leading and lagging than the phase of said reference clock signal and said transition reaches a predetermined number of times.

In one embodiment, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the at least one of the first ratio and the second ratio is increased until the maximum ratio is reached, and then the frequency division step of the frequency division process is increased until the highest step is reached. When the phase indicating signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the frequency division step of the frequency division process is first reduced until a base step is reached, and then the at least one of the first ratio and the second ratio is reduced until the base ratio is reached.

According to another embodiment, an electronic device is provided, which comprises the above-mentioned phase tracking loop.

The above and other features and advantages of the present invention will become apparent from the following description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

Drawings

Fig. 1 shows a schematic diagram of a phase tracking loop according to an embodiment of the invention.

Fig. 2 shows a schematic diagram of a phase tracking loop according to an embodiment of the invention.

Fig. 3 shows a schematic diagram of a digital loop filter according to an embodiment of the invention.

Fig. 4 shows a schematic diagram of adjusting the phase by changing the division ratio according to an embodiment of the present invention.

Fig. 5 shows a schematic diagram of a crossover step design according to an embodiment of the present invention.

Fig. 6 shows a flow chart of a phase tracking method according to an embodiment of the invention.

Fig. 7 shows a flowchart of a frequency-division step adjustment process according to an embodiment of the present invention.

Fig. 8 shows a flow diagram of a clock phase adjustment process according to an embodiment of the invention.

Fig. 9 shows a flow diagram of a method of generating a clock selection indication signal according to an embodiment of the invention.

Fig. 10 shows a flowchart of a coefficient and division step adjustment process according to an embodiment of the present invention.

FIG. 11 shows a schematic diagram of an electronic device according to an embodiment of the invention.

Detailed Description

Some exemplary embodiments of the present invention will be described below with reference to the accompanying drawings. The following description provides some specific details for a clear and complete description of these exemplary embodiments. It should be understood, however, that the invention is not limited to the specific details of these exemplary embodiments. Rather, embodiments of the invention may be practiced without these specific details or with other alternatives without departing from the spirit and principles of the invention as defined by the claims.

Currently, the phase tracking technology for NFC card analog devices in Active Load Modulation (ALM) mode includes a passive matching network based solution and a solution using an All Digital Phase Locked Loop (ADPLL). The adjustment of the passive matching network is not linear, and the step of the phase adjustment is not consistent when the resistance values are different, so that the high-precision adjustment in a larger phase difference range (for example, 0 degree to 180 degrees) is difficult to realize. In addition, the resistance adjustment also changes the impedance of the chip, which has a certain adverse effect on wireless communication. The adpll has a complex design and high cost, and the frequency and phase information generated in the card emulation mode comes entirely from the clock recovered from the reader signal, which tends to be discontinuous. For example, when the reader transmits a signal, the magnetic field disappears when the data is at a low level; for another example, when the NFC card simulation apparatus itself transmits a signal, an excessive transmission signal will drown out the magnetic field signal of the card reader. Therefore, under intermittent reference clock conditions, the loop locking speed requirement for the phase locked loop is very high, because only a very short time is used for frequency and phase locking, which is difficult to solve. In conventional designs, fast locking means that the loop bandwidth is larger, bringing more phase noise introduced by the reference clock, which affects circuit performance; on the other hand, reducing the loop bandwidth can partially improve the phase noise performance, but it is difficult to achieve the requirement of fast locking.

Fig. 1 shows a schematic diagram of a phase tracking loop 100 according to an embodiment of the invention. As shown in fig. 1, phase tracking loop 100 includes a frequency divider 110, a phase detector 120, a phase tuning module 130, and a divide ratio control module 140.

The frequency divider 110 may divide the high frequency clock signal to obtain a low frequency clock signal, i.e., a carrier signal, having the same frequency as the clock recovered from the reader magnetic field. It should be understood that "high frequency" and "low frequency" are relative concepts in this application, describing the relative magnitude of frequencies, but are not intended to limit the absolute magnitude of frequencies, i.e., the frequency range, in any sense.

Phase detector 120 may compare the phases of the carrier signal output by frequency divider 110 and the reference clock signal and output a phase indication signal. Here, the reference clock signal may be a clock signal recovered from the NFC reader, and the phase tracking loop 100 is used to keep the phase of the carrier signal consistent with the phase of the reference clock signal.

Phase tuning module 130 may adjust the phase of the high frequency clock signal provided to frequency divider 110 based on the phase indication signal output by phase detector 120 such that the phase of the carrier signal output by frequency divider 110 tracks/is closer to the phase of the reference clock signal.

The division ratio control module 140 may adjust the division ratio of the frequency divider 110 based on the phase indication signal output by the phase detector 120 to quickly adjust the phase of the carrier signal, which will be described in further detail below.

Fig. 2 illustrates an exemplary implementation of the phase tracking loop 100, in which one exemplary structure of the phase tuning module 130 and the division ratio control module 140 is shown. Referring to fig. 2, the phase tuning module 130 may include a Digital Loop Filter (DLF) 132 and a multiphase clock selection unit 134, and may optionally further include a coefficient control unit 136. The division ratio control module 140 may include a dynamic detection adjustment unit 142 and a division ratio control unit 144.

The phase detector 120 may be a binary phase detector (BBPD), and when the phase of the carrier signal (alternatively referred to as a frequency-divided clock signal) is advanced with respect to the phase of the reference clock signal, the phase detector 120 may output a high level "1"; phase detector 120 may output a low level of "-1" when the phase of the carrier signal lags the phase of the reference clock signal, or vice versa. When the enable signal of phase detector 120 is off (e.g., EN =0, not shown), phase detector 120 may output 0.

Digital Loop Filter (DLF) 132 may detect the phase indication signal output by phase detector 120 and control multiphase clock selection unit 134 to select a clock signal of an appropriate phase from the multiphase clock signals based on the relative phases of the carrier signal and the reference clock signal that it indicates. For example, when phase detector 120 indicates that the phase of the carrier signal is leading than the phase of the reference clock signal, digital loop filter 132 may instruct multiphase clock selection unit 134 to select a clock signal with a more lagging phase from the multiphase clock signals; when phase detector 120 indicates that the phase of the carrier signal is lagging the phase of the reference clock signal, digital loop filter 132 may instruct multiphase clock selection unit 134 to select a clock signal with a more advanced phase from the multiphase clock signals. When the phase indication signal output by the phase detector 120 indicates that the phase of the carrier signal transitions back and forth between leading and lagging the phase of the reference clock signal, the clock signal selected by the multiphase clock selection unit 134 transitions back and forth between the two signals, which is generally equivalent to a constant phase, and the loop reaches a locked state.

Fig. 3 shows a schematic diagram of a digital loop filter 200 according to an embodiment of the invention, the digital loop filter 200 may be implemented as the digital loop filter 132 shown in fig. 2.

Referring to fig. 3, digital loop filter 200 may include a proportional path 210 and an integral path 220 that receive as inputs the phase indication signal output by phase detector 120 at a first input port In-1. Proportional path 210 and integral path 220 may generate a first proportional signal having a first proportion "a" to the phase indicating signal and a second proportional signal having a second proportion "p" to the phase indicating signal, respectively. For example, the proportional path 210 may include a first register 212 having a first proportional coefficient "a" stored therein to output a first proportional signal; the integration path 220 may include a second register 222 having a second scaling factor "p" stored therein to output a second proportional signal. For example, when the output of phase detector 120 is "1", the first proportional signal generated by proportional path 210 is "a", and the second proportional signal generated by integral path 220 is "p"; when the output of the phase detector 120 changes from "1" to "-1", the first proportional signal produces a change of "-2a" from "a" to "-a", and the second proportional signal produces a change of "-2p" from "p" to "-p". Similarly, when the output of phase detector 120 changes from "-1" to "1", the first proportional signal produces a change of "+2a", from "-a" to "a", and the second proportional signal produces a change of "+2p", from "-p" to "p".

In an embodiment, the first proportional signal generated by the proportional path 210 and the second proportional signal generated by the integral path 220, or the first scaling factor "a" and the second scaling factor "p", may also be adjusted. For example, the proportional path 210 may include a first proportional adjustment unit, such as a multiplier 214, that multiplies the first proportional signal with an adjustment factor to generate an adjusted first proportional signal; the integration path 220 may include a second proportional adjustment unit, such as a multiplier 224, that multiplies the second proportional signal with an adjustment factor to generate an adjusted second proportional signal. In the embodiment shown In fig. 3, the first and

second scaling units

214 and 224 receive the same scaling factor from the second input port In-2, thereby scaling the first and second proportional signals In equal proportion. In other embodiments, the first scale adjusting unit 214 and the second scale adjusting unit 224 may also receive different adjustment factors to perform different adjustments on the first scale signal and the second scale signal, or only one of the first scale adjusting unit 214 and the second scale adjusting unit 224 may be provided to perform an adjustment on one of the first scale signal and the second scale signal.

The adjusted second proportional signal may be integrated in the integrator 226 to generate an integrated signal. The integrator 226 may receive the integration clock signal from the third input port In-3 to integrate the adjusted second proportional signal according to the integration clock.

The integrated signal output by integrator 226 of integrating path 220 and the first proportional signal output by proportional path 210 may then be summed in adder 232 to obtain a sum of the two, which may be remainder-subtracted with respect to a predetermined value M in a remainder-subtracting (Mod) unit 234 to generate a clock select indication signal representing the remainder, which is output at output port Out. When the signal output by the phase detector 120 is "1", the integral value output by the integrator 226 gradually increases, and the remainder value represented by the clock selection indication signal output by the remainder unit 234 increases from 0 to 1 after a predetermined period, then increases to 2 after the predetermined period, increases to M-1, and then increases back to 0, and so on cyclically changes. Conversely, if the signal output by phase detector 120 is "-1", the value of the integration output by integrator 226 gradually decreases, and the remainder value indicated by the clock selection indication signal output by remainder unit 234 decreases from 0 to M-1, then decreases to M-2, and decreases to 0 after a predetermined period, and so on cyclically decreases. Here, the remainder value indicated by the clock selection instruction signal is used as an index for the multiphase clock selection unit 134 to select a clock signal corresponding to the index value from among the M clock signals of different phases.

In some embodiments, proportional path 210 may be omitted and only integral path 220 may be used, as may clock selection indication signals containing index values (i.e., remainders) for selecting a corresponding clock signal from the M multiphase clock signals. It should be appreciated that by providing proportional path 210, which is equivalent to introducing a reference zero in the loop, the loop can be prevented from ringing and generating noise. Thus, the phase tracking loop 100 may have improved phase noise performance with the introduction of the proportional path 210.

Referring back to fig. 2, the multiphase clock selection unit 134 selects one clock signal from M clock signals of different phases based on the clock selection indication signal output from the digital loop filter 132. The M clock signals of different phases may have a phase difference of 360 °/M, for example, when M =12, the phases of the M clock signals may be 0 °, 30 °, 60 °, 90 °, 120 °, 150 °, 180 °, 210 °, 240 °, 270 °, 300 °, and 330 °, respectively.

For example, when the output of phase detector 120 is "1", it indicates that the phase of the carrier signal (i.e., the frequency-divided signal) provided by frequency divider 110 is ahead of the phase of the reference clock signal. At this time, as the integrated value output by the integrator 226 gradually increases, the remainder indicated by the clock selection instruction signal output by the digital loop filter 132 gradually increases, so that the multiphase clock selection unit 134 selects a clock signal whose phase is more delayed from among the M (M is an integer greater than 1) clock signals, and the phase of the carrier signal supplied from the frequency divider 110 also shifts backward. When the phase of the carrier signal becomes more delayed than the phase of the reference clock signal, the output of phase detector 120 becomes "-1". At this time, the integrated value output from the integrator 226 gradually decreases, and the remainder indicated by the clock selection instruction signal output from the digital loop filter 132 also gradually decreases, so that the multiphase clock selection unit 134 selects a clock signal whose phase is more advanced from the M clock signals, and the phase of the carrier signal supplied from the frequency divider 110 also shifts forward. When the output of phase detector 120 toggles between "1" and "-1", indicating that the clock signal selected by multiphase clock select unit 134 varies between a clock signal that is in phase advance of the reference clock signal and a clock signal that is in phase retard of the reference clock signal, the overall equivalent is that the phase of the carrier signal is equal to or closest to the phase of the reference clock signal and the loop reaches a locked state.

Here, the phase step between the M clock signals selected by the multiphase clock selection unit 134 is 360 °/M, but after the frequency division process by the frequency divider 110, the phase step (i.e., phase difference) between adjacent frequency-divided signals becomes 360 °/(M × N), where N is the frequency dividing ratio of the frequency divider 110 because the pulse width of the frequency-divided signal is N times the pulse width of the clock signal before frequency division. For example, the frequency of the signal of the NFC reader is 13.56MHz, the frequency of the multiphase clock signal is 867.84MHz, and the frequency divider 110 with the frequency dividing ratio N =64 may be adopted. Of course, other division ratios may be used, for example, when the frequency of the multiphase clock signal is 542.4MHz, a division ratio of N =40 may be used.

If M =12 and the phase step between the multiphase clock signals is 30 °, the phase step of the divided signal becomes 0.46875 °, and thus accurate phase adjustment and tracking can be achieved. When the index value indicated by the clock selection indication signal increases from 0 to 11, the phase of the clock signal selected by the multiphase clock selection unit 134 is delayed by 330 °, and the phase of the divided clock signal is delayed by 5.15625 °; then the index value changes from 11 to 0, the phase of the clock signal selected by the multiphase clock selection unit 134 continues to be retarded by 30 °, and the phase of the divided clock signal continues to be retarded by 0.46875 °. Similarly, cyclically decreasing the index value may cause the phase of the divided signal to move forward continuously. In this way, the phase of the frequency-divided signal (i.e., the carrier signal) can be changed over a wide range.

This scheme greatly improves the accuracy of the phase adjustment, i.e., the phase tracking accuracy of the phase tracking loop 100, by using frequency division processing. However, it is slow to adjust the phase, and each adjustment is stepped by 360 °/(M × N), so that it may take a long time to achieve loop lock. In order to shorten the locking time, the embodiments of the present invention also increase the phase adjustment speed by adjusting the frequency dividing ratio N of the frequency divider 110.

Fig. 4 schematically shows a schematic diagram of adjusting the phase by changing the division ratio. Referring to fig. 4, assuming that the system is designed with a frequency division ratio N =64, the high level and the low level at this time correspond to 32 pulses of the high frequency clock signal before frequency division, respectively. Here, the designed frequency division ratio is a frequency division ratio such that the frequency of the carrier signal is equal to the frequency of the reference clock signal, and therefore the designed frequency division ratio is also referred to as a base frequency division ratio. When the division ratio is changed from 64 to 63, then the start of the divided-by-63 signal of the next cycle is advanced by one short/high-frequency pulse from the start of the divided-by-64 signal, that is, 1/64 of the cycle of the divided-by-64 signal, and thus the phase is advanced by 360 °/64=5.625 °; in the next cycle, the divided-63 signal is 11.25 ° out of phase with the divided-64 signal, and so on. When the division ratio is changed from 64 to 65, then the start of the divided-by-65 signal for the next cycle is one short/high frequency pulse after the start of the divided-by-64 signal, i.e., 1/64 of the cycle of the divided-by-64 signal, and thus the phase lags by 360 °/64=5.625 °; in the next cycle, the divided 65 signal is 11.25 ° later in phase than the divided 64 signal, and so on. It will be appreciated that when the division ratio is changed from N to N ± x, the value of x may be set as desired, with an advance or retard step of (360 ° × x)/N. Therefore, by changing the frequency dividing ratio, the phase of the carrier signal can be adjusted quickly, thereby speeding up the phase adjustment.

Referring back to fig. 2, the dynamic detection adjustment unit 142 may detect the phase indication signal generated by the phase detector 120 and generate a frequency division ratio adjustment signal. The division ratio control unit 144 may control the division ratio of the frequency divider 110 based on the division ratio adjustment signal provided by the dynamic detection adjustment unit 142. In one embodiment, the division ratio of the divider 110 may be set to a plurality of steps, an example of which is shown in fig. 5. Fig. 5 shows a total of four gears 0-3, but more or fewer gears may be used, such as two gears, three gears, five gears, etc. The shift stage 0 is also referred to as a base shift stage, and corresponds to the base frequency dividing ratio N. The frequency dividing ratio of higher gears is N +/-x, the higher the gear is, the larger the value of x is, wherein N and x are both positive integers, and N is larger than x. For example, the division ratio for gear 1 may be N + -1, the division ratio for gear 2 may be N + -2, the division ratio for gear 3 may be N + -3, and so on. When the phase indication signal indicates that the phase of the carrier signal is ahead of the phase of the reference clock signal, the frequency division ratio of the gear may be N + x to use a larger frequency division ratio so that the phase of the carrier signal is delayed; when the phase indication signal indicates that the phase of the carrier signal is lagging the phase of the reference clock signal, the division ratio of the gear may be N-x to use a smaller division ratio to advance the phase of the carrier signal.

In an embodiment, when the phase detector 120 indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal (the phase indication signal is "1" or "-1") and continues for a predetermined number of cycles, indicating that the phase difference between the carrier signal and the reference clock signal is large, the dynamic detection adjustment unit 142 may generate a first division ratio adjustment signal, and the division ratio control unit 144 may increase the division step of the frequency divider 110 in response to the first division ratio adjustment signal. This operation may be repeated to continually increase the phase adjustment step of the carrier signal until the highest gear is reached. When the phase detector 120 indicates that the phase of the carrier signal has hopped between more lead and more lag than the phase of the reference clock signal (the phase indication signal hopped between "1" and "-1") and hopped a predetermined number of times, indicating that the phase of the carrier signal has been adjusted to around the phase of the reference clock signal, the dynamic detection adjustment unit 142 may generate a second division ratio adjustment signal, and the division ratio control unit 144 may decrease the division step of the frequency divider 110 in response to the second division ratio adjustment signal to decrease the phase adjustment step of the carrier signal until the base step is reached. It can be understood that, in addition to instructing the division ratio control unit 144 to increase or decrease the division step of the divider 110, the dynamic detection adjustment unit 142 also instructs the division ratio control unit 144 on the current phase state of the carrier signal, i.e., whether to lead or lag the phase of the reference clock signal, so that the division ratio control unit 144 can control whether the division ratio of the divider 110 is N + x or N-x at each division step.

The adjustment procedure of the frequency division step is exemplified below. For example, initially, the frequency divider 110 is in the base gear, and the frequency division ratio is 64. When the dynamic detection adjustment unit 142 detects that the output of the phase detector 120 is "1" and lasts for, for example, 4 cycles, it instructs the frequency division ratio control unit 144 to increase the frequency division position of the frequency divider 110 to the position 1, at which time the frequency division ratio of the frequency divider 110 becomes 65. When the dynamic detection adjustment unit 142 detects that the output of the phase detector 120 is still "1" and lasts for 4 cycles, for example, it instructs the division ratio control unit 144 to increase the division position of the frequency divider 110 to the position 2, and the division ratio of the frequency divider 110 becomes 66. This operation may be repeated until the divider 110 reaches the highest tap 3, at which point the divide ratio of the divider 110 becomes 67 and the phase adjustment step reaches a maximum. Through the above operation, the phase of the carrier signal is continuously shifted backward, and when it becomes later than the phase of the reference clock signal, the output of the phase detector 120 changes from "1" to "-1", at which time the frequency divider 110 remains at the highest shift 3, but the division ratio changes from 67 to 61, the phase of the carrier signal changes to shift forward, causing the phase thereof to again become ahead of the phase of the reference clock signal, the output of the phase detector 120 changes from "-1" to "1", and the division ratio of the frequency divider 110 changes from 61 to 67. When the dynamic detection adjustment unit 142 detects that the output of the phase detector 120 jumps between "1" and "-1" for a predetermined number of times, for example, 6 times, it instructs the frequency division ratio control unit 144 to decrease the frequency division position of the frequency divider 110, from position 3 to position 2, and the phase adjustment step decreases. This operation may be repeated until the divider 110 reaches the base gear, the divide ratio is 64, at which point the divide ratio no longer affects the phase of the carrier signal, and the frequency of the carrier signal is equal to the reference clock signal.

In addition to controlling the phase adjustment speed by the frequency division ratio, it will be appreciated that the phase adjustment speed is also dependent upon the speed at which digital loop filter 132 changes its output clock selection indication signal, i.e., the sum value output by adder 232, in accordance with the phase indication signal output by phase detector 120. It is understood that as the first scaling factor a and the second scaling factor p become larger, the change speed of the sum value output by the adder 232 also increases. Therefore, by adjusting at least one of the first scaling factor a and the second scaling factor p, preferably at least the second scaling factor p (since it is possible to change the sum value output by the adder 232 faster by the integration operation), the phase adjustment speed can be changed.

With continued reference to fig. 2, the coefficient control unit 136 may control the magnitude of an adjustment coefficient provided to the second input port In-2 of the digital loop filter 132/200 for adjusting at least one of the first scaling coefficient a and the second scaling coefficient p. For example, when the dynamic detection adjustment unit 142 detects that the phase detector 120 indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal (the phase indication signal is "1" or "-1") and continues for a predetermined number of cycles (which may be the same as or different from the number of cycles used for the frequency division control), the dynamic detection adjustment unit 142 may generate a first coefficient adjustment signal, and the coefficient control unit 136 may increase the adjustment coefficient in response to the first coefficient adjustment signal to increase at least one of the first scaling coefficient a and the second scaling coefficient p, thereby accelerating the phase adjustment speed. This operation may be repeated until the maximum scale factor is reached. When the dynamic detection adjustment unit 142 detects that the phase detector 120 indicates that the phase of the carrier signal jumps between more lead and more lag than the phase of the reference clock signal (the phase indication signal jumps between "1" and "-1") and jumps a predetermined number of times (which may or may not be the same as the number of jumps used for frequency division control), the dynamic detection adjustment unit 142 may generate a second coefficient adjustment signal, and the coefficient control unit 136 may decrease the adjustment coefficient in response to the second coefficient adjustment signal to decrease at least one of the first scaling coefficient a and the second scaling coefficient p to decrease the phase adjustment speed until the base scale is reached. It is understood that increasing and decreasing the scaling factors a and p can change the phase adjustment speed, but does not affect the phase adjustment accuracy.

The phase adjustment speed control by the division ratio adjustment and the phase adjustment speed control by the scale factor adjustment may be used in combination. It is understood that the phase adjustment step caused by the change of the division ratio of the divider 110 is generally much larger than the phase adjustment step caused by the change of the clock selection indication signal of the digital loop filter 132, so the division ratio adjustment manner of the divider 110 can be referred to as coarse adjustment, and the scaling factor adjustment manner of the digital loop filter 132 can be referred to as fine adjustment. In one embodiment, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more delayed than the phase of the reference clock signal and lasts for a predetermined period, the dynamic detection adjustment unit 142 may first generate the first coefficient adjustment signal to increase at least one of the first scaling factor a and the second scaling factor p until the maximum scaling factor is reached, and then generate the first frequency division ratio adjustment signal to increase the frequency division step of the frequency divider 110 until the highest step is reached. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and jumps up to the predetermined number of times, the dynamic detection adjustment unit 142 may first generate the second division ratio adjustment signal to lower the division step of the frequency divider 110 until the base step is reached, and then generate the second coefficient adjustment signal to decrease the at least one of the first scaling coefficient a and the second scaling coefficient p until the base ratio is reached.

Although the phase tuning module 130 is described above as including the digital loop filter 132 and the multiphase clock selection unit 134, it should be understood that the present invention is not limited thereto. The phase tuning module 130 may be implemented as any module or device that can adjust the phase of the clock signal, and the coefficient control unit 136 may be omitted.

Fig. 6 shows a flow diagram of a phase tracking method 300 according to an embodiment of the invention. The method 300 may be implemented using the phase tracking loop 100 described above with reference to fig. 1-5. Referring to fig. 6, the phase tracking method 300 may include: step 310, performing frequency division processing on the clock signal to obtain a carrier signal; step 320, comparing the phases of the carrier signal and the reference clock signal to generate a phase indication signal; and a step 330 of adjusting the phase of the clock signal and the division ratio of the division process based on the phase indication signal so that the phase of the carrier signal is closer to the phase of the reference clock signal.

Fig. 7 shows a flowchart of a frequency division step adjustment procedure, which may be applied in step 330 of the method 300 shown in fig. 6, according to an embodiment of the invention. In an embodiment, the frequency division process may have a basic gear with a basic division ratio N and at least one higher gear with a higher division ratio N + x or a lower division ratio N-x, where N is a preset positive integer, x is a positive integer smaller than N and the higher the gear, the larger the value of x. When the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, the higher gear has a higher frequency dividing ratio N + x; higher gears have a lower division ratio N-x when the phase indication signal indicates that the phase of the carrier signal is more lagging than the phase of the reference clock signal. The basic division ratio N is such that the frequency of the carrier signal obtained after division is equal to the frequency of the reference clock signal.

Referring to fig. 7, adjusting the division ratio of the division process based on the phase indication signal may include: at step 331, it is determined whether the phase of the carrier signal transitions between being more advanced and more retarded than the phase of the reference clock signal and transitions up to a predetermined number of times based on the phase indication signal. If so, the frequency division step of the frequency division process is reduced in step 333. Steps 331 and 333 may be repeatedly executed until the assigned gear reaches the base gear.

If it is determined in step 331 that the transition has not occurred or does not occur more than the predetermined number of times, it is determined in step 335 whether the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and lasts for a predetermined period. If it is determined that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal for a predetermined period, the frequency-dividing step of the frequency-dividing process may be increased in step 337. Steps 335 and 337 may be repeated until the divided gear of the frequency dividing process reaches the highest gear.

Fig. 8 shows a flow chart of a clock phase adjustment process according to an embodiment of the invention, which may be applied in step 330 of the method 300 shown in fig. 6. Referring to fig. 8, adjusting the phase of the clock signal based on the phase indication signal may include: at step 332, generating a selection indication signal based on the phase indication signal; and at step 334, selecting one clock signal from the plurality of phase clock signals based on the selection indication signal. Wherein the generated selection indication signal may indicate that a clock signal having a phase more retarded than a currently selected clock signal is selected from the multi-phase clock signals when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal. The generated selection indication signal may indicate selection of a clock signal from the multi-phase clock signals having a phase that is more advanced than a currently selected clock signal when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

Fig. 9 shows a flowchart of a method of generating a clock selection indication signal according to an embodiment of the invention, which may be applied, for example, in step 332 shown in fig. 8. Referring to fig. 9, in step 412, a first proportional signal may be generated that is in a first proportion to the phase indication signal; at step 414, a second ratio signal may be generated that is a second ratio to the phase indicating signal.

Optionally, in step 416, at least one of the first ratio and the second ratio may also be adjusted based on the phase indication signal. For example, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal for a predetermined period, at least one of the first ratio and the second ratio may be increased until the maximum ratio is reached. When the phase indication signal indicates that the phase of the carrier signal transitions between leading and lagging the phase of the reference clock signal and the transition reaches a predetermined number of times, at least one of the first and second ratios may be reduced until the base ratio is reached.

With continued reference to fig. 9, at step 418, the second proportional signal may be integrated to obtain an integrated signal. The first proportional signal and the integrated signal may then be added to obtain a sum of the two at step 420. At step 422, the sum may be subjected to a remainder operation with respect to a predetermined value to generate the selection indication signal. The predetermined value may be equal to the number of clock signals having different phases included in the multiphase clock signals to be selected.

Fig. 10 shows a flowchart of a coefficient and frequency-division step adjustment process according to an embodiment of the present invention, in which the execution order of the coefficient adjustment and the frequency-division step adjustment is shown. Referring to fig. 10, in step 501, it may be determined whether the phase of the carrier signal transitions between being more advanced and more retarded than the phase of the reference clock signal and transitions up to a predetermined number of times based on the phase indication signal. If no transition occurs or the transition has not occurred a predetermined number of times, then a determination is made in step 503 as to whether the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and for a predetermined period. If it is not detected that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal by the predetermined period, the scaling factor of the digital loop filter and the frequency division step of the frequency divider may be kept unchanged at step 521, and then return to step 501.

If it is determined in step 503 that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal by a predetermined period, it may be determined in step 505 whether the scaling coefficients (first scaling coefficients and/or second scaling coefficients) of the digital loop filter to be adjusted reach a maximum value. If the maximum value has not been reached, the scaling factor of the digital loop filter to be adjusted may be increased in step 507 and then returned to step 501.

If it is determined in step 505 that the scaling factor of the digital loop filter to be adjusted has reached the maximum value, then it may be determined in step 509 whether the frequency-dividing step of the frequency divider has reached the maximum step. If the maximum gear has not been reached, the frequency-division gear of the frequency divider may be increased in step 511, and then return to step 501. If the divide-down step of the divider has reached the maximum step, the scaling factor of the digital loop filter and the divide-down step of the divider may be kept unchanged in step 521, and then return is made to step 501.

On the other hand, if it is determined in step 501 that the phase of the carrier signal jumps between more lead and more lag than the phase of the reference clock signal and jumps up to a predetermined number of times, it may be determined in step 513 whether the frequency-division step of the frequency divider is at the lowest/base step. If the frequency division step of the frequency divider is not the lowest step, the frequency division step of the frequency divider may be reduced at step 515 and then returned to step 501.

If it is determined in step 513 that the frequency division step of the frequency divider is at the lowest step, it may be determined in step 517 whether the scaling factor (first scaling factor and/or second scaling factor) to be adjusted of the digital loop filter is at a minimum value. If not, the scaling factor of the digital loop filter to be adjusted may be reduced 519 and then returned to 501. If the scaling factor of the digital loop filter to be adjusted is already a minimum value, the scaling factor of the digital loop filter and the frequency division step of the frequency divider may be kept unchanged in step 521 and then returned to step 501.

Having described the embodiments of the phase tracking loop and the phase tracking method of the present invention with reference to the drawings, it can be seen that the phase tracking loop and the phase tracking method of the present invention can achieve fast and highly accurate phase locking within a large phase difference range and have improved phase noise performance. For example, taking the example that the division ratio N =64 and the multiphase clock signal have a 30 ° phase difference (M = 12), the conventional phase adjustment step is 0.46875 °, and if a 180 ° phase difference exists between the carrier signal and the reference clock signal, the phase locking time is typically around 100 μ s. If there is a certain frequency deviation between the carrier signal and the reference clock signal, the phase lock time is above 100 mus. By utilizing the dynamic detection and adjustment technology, the dynamic adjustment of the frequency division ratio can be started in the initial stage of phase tracking, the phase adjustment step is increased by tens of times according to the adjustment gear of the frequency division ratio, and the locking time is greatly shortened. And when the locking is approached, the frequency division ratio adjusting gear is reduced until the locking is stopped, and the stepping is recovered to 0.46875 DEG, so that the phase adjusting precision is not lost. The whole stabilization time can be shortened to be within 10 us.

FIG. 11 shows a schematic diagram of an electronic device 600 according to an embodiment of the invention. The electronic device 600 may include a phase tracking loop 620 according to an embodiment of the present invention. For example, the electronic device 600 may have an NFC module 610, which may operate in a card emulation mode. NFC module 610 may include a phase tracking loop 620 to track the signal phase of the NFC reader. Examples of such electronic devices 600 include, but are not limited to, cell phones, tablets, portable personal digital assistants, wearable electronic devices, and the like.

The basic principles of the present application have been described above with reference to specific embodiments, but it should be noted that advantages, effects, etc. mentioned in the present application are only examples and are not limiting, and the advantages, effects, etc. must not be considered to be possessed by various embodiments of the present application. Furthermore, the foregoing disclosure of specific details is provided for purposes of illustration and understanding only, and is not intended to limit the application to the details which are set forth in order to provide a thorough understanding of the present application.

The block diagrams of devices, apparatuses, devices, systems referred to in this application are only used as illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by one skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably herein. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".

It should also be noted that in the devices, apparatuses, and methods of the present application, the components or steps may be decomposed and/or recombined. These decompositions and/or recombinations are to be considered as equivalents of the present application.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the application to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.

Claims

1. A phase tracking loop, comprising:

a frequency divider for performing frequency division processing on the clock signal to obtain a carrier signal;

a phase detector for comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal;

a division ratio control module for adjusting the division ratio of the frequency divider based on the phase indication signal; and

a phase tuning module to adjust a phase of the clock signal based on the phase indication signal.

2. A phase tracking loop as claimed in claim 1, wherein said phase detector is a binary phase detector, said binary phase detector outputting a first indication signal when the phase of said carrier signal is leading than the phase of said reference clock signal and outputting a second indication signal when the phase of said carrier signal is lagging than the phase of said reference clock signal.

3. The phase tracking loop of claim 1, wherein the divide ratio control module comprises:

a dynamic detection adjusting unit, configured to detect the phase indication signal generated by the phase discriminator and generate a frequency division ratio adjusting signal; and

a frequency division ratio control unit for controlling the frequency division ratio of the frequency divider based on the frequency division ratio adjustment signal.

4. The phase tracking loop of claim 3, wherein the dynamic detection adjustment unit generates a first division ratio adjustment signal when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal for a predetermined period, the division ratio control unit increasing the division step of the frequency divider in response to the first division ratio adjustment signal until a highest step is reached,

the dynamic detection adjustment unit generates a second division ratio adjustment signal when the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the division ratio control unit decreases the division step of the frequency divider in response to the second division ratio adjustment signal until reaching a basic step,

the frequency divider has the basic gear and at least one higher gear, the basic gear has a basic frequency dividing ratio N, the higher gear has a higher frequency dividing ratio N + x or a lower frequency dividing ratio N-x, N is a preset positive integer, x is a positive integer smaller than N, and the higher the gear is, the larger the value of x is, the higher gear has the higher frequency dividing ratio N + x when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and the higher gear has the lower frequency dividing ratio N-x when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

5. The phase tracking loop of claim 4, wherein the base divide ratio N is such that the frequency of the carrier signal is equal to the frequency of the reference clock signal.

6. The phase tracking loop of claim 4, wherein the phase tuning module comprises:

a digital loop filter for generating a selection indication signal based on the phase indication signal; and

a multi-phase clock selection unit for selecting one clock signal from the multi-phase clock signals based on the selection indication signal.

7. The phase tracking loop of claim 6, wherein the multi-phase clock signals comprise M clock signals of different phases, M being an integer greater than one,

the selection indication signal generated by the digital loop filter represents one of the M index values to indicate to the multiphase clock selection unit to select a corresponding one of the M clock signals of different phases.

8. The phase tracking loop of claim 6 wherein the selection indication signal generated by the digital loop filter instructs the multiphase clock selection unit to select a clock signal from the multiphase clock signals that is more phase lagging than a currently selected clock signal when the phase indication signal generated by the phase detector indicates that the phase of the carrier signal is leading than the phase of the reference clock signal and for a predetermined period,

when the phase indication signal generated by the phase detector indicates that the phase of the carrier signal lags the phase of the reference clock signal for a predetermined period, the selection indication signal generated by the digital loop filter indicates that the multiphase clock selection unit selects one of the multiphase clock signals having a phase more advanced than the currently selected clock signal.

9. The phase tracking loop of claim 6, wherein the digital loop filter comprises:

a proportional path for generating a first proportional signal in a first proportion to the phase indication signal;

an integration path for generating a second proportional signal in a second proportion to the phase indication signal and for integrating the second proportional signal to generate an integrated signal;

an adder for adding the first proportional signal and the integral signal to output a sum of the first proportional signal and the integral signal; and

a remainder unit configured to perform a remainder operation on the sum value received from the adder with respect to a predetermined value to generate the selection indication signal representing a remainder.

10. The phase tracking loop of claim 9, wherein the predetermined value is equal to a number of clock signals having different phases included in the multi-phase clock signals.

11. The phase tracking loop of claim 9, wherein the digital loop filter further comprises at least one of:

a first proportion adjusting unit provided in the proportion path, for adjusting the first proportion; and

a second proportion adjustment unit provided in the integration path for adjusting the second proportion.

12. The phase tracking loop of claim 11, wherein the first scale adjustment unit and the second scale adjustment unit use the same adjustment coefficient to make equal-scale adjustments to the first scale and the second scale.

13. The phase tracking loop of claim 11, further comprising:

a coefficient control unit for controlling an adjustment coefficient for adjusting at least one of the first proportion and the second proportion,

wherein the dynamic detection adjustment unit generates a first coefficient adjustment signal when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the coefficient control unit increasing the adjustment coefficient in response to the first coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached,

when the phase indicating signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates a second coefficient adjustment signal, the coefficient control unit decreases the adjustment coefficient in response to the second coefficient adjustment signal to decrease the at least one of the first and second ratios until a base ratio is reached.

14. The phase tracking loop of claim 13, wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal for a predetermined period, the dynamic detection adjustment unit first generates the first coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, and then generates the first division ratio adjustment signal to increase the division step of the frequency divider until a highest step is reached,

when the phase indicating signal indicates that the phase of the carrier signal jumps between leading and lagging than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit first generates the second division ratio adjustment signal to lower the division step of the frequency divider until a base step is reached, and then generates the second coefficient adjustment signal to decrease the at least one of the first ratio and the second ratio until the base ratio is reached.

15. A method of phase tracking, comprising:

performing frequency division processing on the clock signal to obtain a carrier signal;

comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal;

adjusting the phase of the clock signal and the division ratio of the frequency division process based on the phase indication signal so that the phase of the carrier signal is closer to the phase of the reference clock signal.

16. The method of claim 15, wherein adjusting a divide ratio of the divide process based on the phase indication signal comprises:

increasing the frequency division step of the frequency division process until the highest step is reached when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period; or

Lowering the frequency division step of the frequency division process until a base step is reached when the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times,

wherein the frequency dividing process has the basic shift stage and at least one higher shift stage, the basic shift stage has a basic frequency dividing ratio N, the higher shift stage has a higher frequency dividing ratio N + x or a lower frequency dividing ratio N-x, N is a preset positive integer, x is a positive integer smaller than N and the higher shift stage, the larger the value of x, the higher shift stage has the higher frequency dividing ratio N + x when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and the higher shift stage has the lower frequency dividing ratio N-x when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

17. The method of claim 16, wherein the base divide ratio N is such that the frequency of the carrier signal is equal to the frequency of the reference clock signal.

18. The method of claim 16, wherein adjusting the phase of the clock signal based on the phase indication signal comprises:

generating a selection indication signal based on the phase indication signal; and

selecting one clock signal from the multi-phase clock signals based on the selection indication signal,

wherein the selection indication signal indicates to select one of the clock signals having a phase more retarded than a phase of a currently selected clock signal from among the multiphase clock signals when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and the selection indication signal indicates to select one of the clock signals having a phase more advanced than the phase of the currently selected clock signal from among the multiphase clock signals when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

19. The method of claim 18, wherein generating a selection indication signal based on the phase indication signal comprises:

generating a first ratio signal in a first ratio to the phase indication signal;

generating a second proportion signal in a second proportion to the phase indication signal;

integrating the second proportional signal to obtain an integrated signal;

adding the first proportional signal and the integral signal to obtain a sum of the first proportional signal and the integral signal;

and performing a remainder operation on the sum value with respect to a predetermined value to generate the selection indication signal.

20. The method of claim 19, wherein the predetermined value is equal to a number of clock signals having different phases included in the multi-phase clock signals.

21. The method of claim 19, further comprising:

adjusting at least one of the first ratio and the second ratio based on the phase indication signal.

22. The method of claim 21, wherein adjusting at least one of the first and second ratios comprises:

increasing the at least one of the first and second ratios until a maximum ratio is reached when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal for a predetermined period; or

When the phase indication signal indicates that the phase of the carrier signal transitions between leading and lagging the phase of the reference clock signal and the transition reaches a predetermined number of times, decreasing the at least one of the first and second ratios until a base ratio is reached.

23. The method of claim 22, wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal for a predetermined period, the at least one of the first and second ratios is increased until a maximum ratio is reached, and then the frequency division step of the frequency division process is increased until a highest step is reached; or

When the phase indicating signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the frequency division step of the frequency division process is first reduced until a base step is reached, and then the at least one of the first ratio and the second ratio is reduced until the base ratio is reached.

24. An electronic device comprising the phase tracking loop of any one of claims 1-14.