KR100249321B1 - Plug forming method of semiconductor device - Google Patents
Plug forming method of semiconductor device Download PDFInfo
- Publication number
- KR100249321B1 KR100249321B1 KR1019980007058A KR19980007058A KR100249321B1 KR 100249321 B1 KR100249321 B1 KR 100249321B1 KR 1019980007058 A KR1019980007058 A KR 1019980007058A KR 19980007058 A KR19980007058 A KR 19980007058A KR 100249321 B1 KR100249321 B1 KR 100249321B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- plug
- metal film
- wiring
- contact hole
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 63
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 33
- 239000010937 tungsten Substances 0.000 claims abstract description 33
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 9
- 230000008021 deposition Effects 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
다층금속 배선 형성시 적용될 수 있는 반도체 소자의 플러그 형성 방법에 관한 것으로, 다층금속 배선 형성시 텅스텐 막과 알루미늄 막 사이에 선택비가 상이한 질화 티타늄 막을 적층하여 텅스텐 플러그를 형성함으로써 콘택트 홀 내에 플러그 리세스가 형성되지 않으며, 배선과 배선사이에 발생하는 단선 단락을 방지하여 반도체 소자의 신뢰성을 향상시킨다.The present invention relates to a method for forming a plug of a semiconductor device which can be applied when forming a multilayer metal wiring. In forming a multilayer metal wiring, a tungsten plug is formed by stacking a titanium nitride film having a different selectivity between a tungsten film and an aluminum film to form a plug recess in a contact hole. It is not formed, and it prevents the disconnection short circuit which arises between wiring and wiring, and improves the reliability of a semiconductor element.
Description
본 발명은 다층금속 배선기술에 관한 것으로, 보다 더 상세하게는 다층금속 배선 형성시 적용될 수 있는 반도체 소자의 플러그 형성방법에 관한 것이다.The present invention relates to a multi-layer metal wiring technology, and more particularly to a method of forming a plug of a semiconductor device that can be applied when forming a multi-layer metal wiring.
일반적으로 다층금속배선은 집적회로에서 배선을 다층화하여, 기판 내에 배치된 각 소자간의 조합에 자유도를 주어, 고밀도의 디바이스를 형성시키기 위한 것이다.In general, multi-layered metal wiring is to form a high-density device by multiplying the wiring in an integrated circuit, giving a degree of freedom to the combination between the elements disposed in the substrate.
특히, 다층금속배선은 칩 위에 배선을 통과시키는 스페이스를 고려하지 않고 각 소자가 레이아웃되기 때문에 집적도 및 밀도가 향상되어 칩 사이즈가 축소되며, 배선의 자유도가 증가하고, 패턴 설계가 용이해짐과 함께 배선 저항이나 전류 용량 등의 설정을 여유를 가지고 할 수 있게 된다.In particular, since multi-layered metal wiring is laid out without considering the space for passing wiring on the chip, the degree of integration and density are improved, chip size is reduced, wiring freedom is increased, and pattern design is facilitated. It is possible to set the resistance and the current capacity with a margin.
그러나, 다층금속배선은 단층금속배선에 비해 리소그래피 공정 및 증착 공정이 추가되므로 공정이 복잡하며, 특히 층간 배선을 위한 콘택트 홀 내에 금속막과 금속막을 전기적으로 연결하는 플러그 형성시 오버 에칭에 의한 플러그 리세서(plug recess)가 발생하며, 이러한 현상에 의해 소자 동작시 층간 배선의 단선등이 발생하여 소자의 신뢰성을 저하시킬수 있다는 문제점이 있다.However, the multilayer metal wiring has a complicated process because the lithography process and the deposition process are added compared to the single layer metal wiring, and the plug reset by over etching during the formation of the plug electrically connecting the metal film and the metal film in the contact hole for interlayer wiring. There is a problem that a plug recess occurs, and thus, a phenomenon such as disconnection of interlayer wiring occurs during operation of the device, thereby lowering the reliability of the device.
이하, 첨부된 도면을 참고로하여 종래 공정에 의한 플러그 리세스 형성과정을 도1a 내지 도1f를 참조로 설명하면 다음과 같다.Hereinafter, a plug recess forming process according to a conventional process will be described with reference to FIGS. 1A to 1F with reference to the accompanying drawings.
먼저, 도1a와 같이 제1배선 상부(1)에 절연막을 증착하고, 이 절연막(2)의 상부에 감광막(미도시)를 도포한 다음, 금속배선을 형성하기 위한 감광막패턴(미도시)을 형성하고, 이 감광막 패턴을 마스크로 하여 절연막(2)을 식각한 후, 감광막을 제거하여 콘택트 홀(3)을 형성한다.First, as shown in FIG. 1A, an insulating film is deposited on the upper portion 1 of the first wiring, a photosensitive film (not shown) is coated on the insulating film 2, and then a photosensitive film pattern (not shown) for forming metal wiring is formed. The insulating film 2 is etched using this photosensitive film pattern as a mask, and then the photosensitive film is removed to form the contact hole 3.
그 다음, 도1b와 같이 콘택트 홀(3)이 형성되어 있는 절연막(2) 상부에 식각 베리어로서 티타늄, 또는 질화 티타늄과 같은 금속을 스퍼터링하여 글로층(4)을 형성한다. 이때, 콘택트 홀(3)의 폭이 좁기 때문에 임의의 방향으로 스퍼터된 티타늄 또는 질화티타늄 입자는 콘택트 홀(3)의 우물 안쪽보다 위쪽 모서리 부분에서 상대적으로 두껍게 형성된다.Next, as shown in FIG. 1B, a glow layer 4 is formed by sputtering a metal such as titanium or titanium nitride as an etching barrier on the insulating film 2 on which the contact hole 3 is formed. At this time, since the width of the contact hole 3 is narrow, the titanium or titanium nitride particles sputtered in any direction are formed relatively thicker at the upper edge portion than the inside of the well of the contact hole 3.
이어서, 화학 기상 증착(chemical vapor deposition ) 방법으로 텅스텐 막(5)을 증착하여 콘택트 홀(3)을 메운다. 이때 콘택트 홀(3) 상단에서의 증착 속도의 증가에 의해 텅스텐이 완전히 채워지지 않은 채 콘택트 홀(3)의 입구가 막혀 도1b와 같이 텅스텐 막(5)에 공공(void, 6)이 생성될 수 있으며, 또한 콘택트 홀(4)의 상단 중앙부에 텅스텐 막(5)이 집중되어 콘택트 홀 상부에 증착되는 텅스텐 막(5)에는 보조개 같이 우품 들어간 딤플(dimple, 7)이 형성된다.Then, the tungsten film 5 is deposited by chemical vapor deposition to fill the contact holes 3. At this time, the inlet of the contact hole 3 is blocked while the tungsten is not completely filled due to the increase of the deposition rate at the top of the contact hole 3, so that voids 6 are formed in the tungsten film 5 as shown in FIG. In addition, the tungsten film 5 is concentrated in the upper center portion of the contact hole 4 so that dimples 7 dimpled like dimples are formed in the tungsten film 5 deposited on the contact hole.
이후, 텅스텐 막(5)을 식각하는 경우 도1c와 같이 콘택트 홀(3) 상부의 텅스텐 막(5)에 형성되어 있는 딤플(7)의 결정입계를 따라 급속히 식각되어 콘택트 홀(3) 상부의 텅스텐 막(5)이 먼저 식각되고 소자영역 상부에는 일정두께의 텅스텐 막(5)이 잔류하게 된다. 이때, 잔류하는 텅스텐 막(5)을 제거하기 위해 반복해서 식각하는 경우 콘택트 홀(3) 내부에 채워져 있는 텅스텐 막(5)이 과도하게 식각되어 도1d와 같이 콘택트 홀(3) 내부에 플러그 리세스(8)가 형성되며, 경우에 따라서는 플러그 리세스(8)가 콘택트 홀(3) 내부의 텅스텐 막(5)에 존재하는 공공(6)과 연결되기도 한다.Subsequently, when the tungsten film 5 is etched, as shown in FIG. 1C, the tungsten film 5 is rapidly etched along the grain boundaries of the dimples 7 formed in the tungsten film 5 on the contact hole 3. The tungsten film 5 is etched first, and the tungsten film 5 having a predetermined thickness remains on the device region. At this time, when repeatedly etching to remove the remaining tungsten film 5, the tungsten film 5 filled in the contact hole 3 is excessively etched, and as shown in FIG. A recess 8 is formed, and in some cases, the plug recess 8 is connected to the cavity 6 present in the tungsten film 5 inside the contact hole 3.
다음, 도1e와 같이 절연막(2) 상부를 질화티타늄과 같은 금속막을 스퍼터링하여 금속배선에 전류가 집중되는 것을 막기 위한 배리어용 금속막(9)을 증착한다. 이때, 배리어용 금속막(9)은 콘택트 홀(3) 상부에 형성되어 있는 플러그 리세스(8)를 따라 증착되므로 텅스턴 막 증착시 형성되는 딤플(7)과 같이 우품들어간 또 다른 딤플(10)이 형성된다.Next, as shown in FIG. 1E, a metal film such as titanium nitride is sputtered on the upper portion of the insulating film 2 to deposit a barrier metal film 9 for preventing current from being concentrated in the metal wiring. At this time, the barrier metal film 9 is deposited along the plug recess 8 formed on the contact hole 3, so that another dimple 10 is formed, such as the dimple 7 formed when the tungsten film is deposited. ) Is formed.
이어서, 도1f와 같이 배리어용 금속막(9) 상부에 알루미늄(Al)과 같은 배선용 금속막(11)을 증착하여 금속배선을 형성한 다음, 이 배선용 금속막(11) 상부에 금속배선의 난반사를 차단하기 위한 ARC막(anti reflective coating, 11)막을 증착한다. 이때, 배선용 금속막(11)은 배리어용 금속막(9)의 표면을 따라 증착되므로 배리어용 금속막(9)의 증착시 형성되는 딤플(10) 보다 더 깊은 딤플(13)이 콘택트 홀(3) 상부에 형성된다.Subsequently, as shown in FIG. 1F, a wiring metal film 11 such as aluminum (Al) is deposited on the barrier metal film 9 to form metal wiring, and then diffuse reflection of the metal wiring on the wiring metal film 11 is performed. ARC film (anti reflective coating, 11) film to block the deposition. At this time, since the wiring metal film 11 is deposited along the surface of the barrier metal film 9, the dimple 13 deeper than the dimple 10 formed during the deposition of the barrier metal film 9 is formed in the contact hole 3. ) Is formed on top.
따라서, 다층 금속배선을 형성하기 위한 후속공정에서, 플러그를 형성하기 위한 홀의 깊이는 딤플의 영향으로 평균 층간 절연막 두께보다 더 깊어야만 연결 적층이 가능하고, 이러한 영향에 따라 다층배선의 경우 층이 증가할 때 마다 딤플의 영향이 더욱 심각해 질수 있으며, 경우에 따라 콘택트 홀이 완전히 형성되지 않는 에치 스톱(etch stop)이 발생할 수 있으며, 플러그와 금속배선과의 접합성이 떨어져 반도체 소자의 신뢰성이 감소한다는 문제점이 있다. 특히 반도체 소자의 크기를 축소하기 위해 층간 플러그들을 일직선상에 배치하는 경우 플러그와 금속배선과의 접합성이 더욱 감소한다는 문제점이 있다.Therefore, in the subsequent process for forming the multi-layered metal wiring, the depth of the hole for forming the plug must be deeper than the average interlayer insulating film thickness under the influence of dimples, so that the connection stacking is possible. Each time, the effect of the dimple may become more serious, and in some cases, an etch stop may occur in which contact holes are not completely formed, and the reliability of the semiconductor device may be reduced due to the lack of bonding between the plug and the metal wiring. There is this. In particular, when the interlayer plugs are arranged in a straight line to reduce the size of the semiconductor device, there is a problem in that the bonding between the plug and the metal wiring is further reduced.
본 발명은 전술한 바와 같은 문제점을 감안하여 안출한 것으로, 그 목적은 금속 배선간의 연결에 있어 플러그 리세스 없이 배선을 적층함으로써 금속배선 층간의 단락 및 단선을 방지하고, 반도체 소자의 신뢰성을 향상시키기 위한 것이다.SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to stack wires without plug recesses in connection between metal wires, thereby preventing short circuits and disconnection between metal wire layers, and improving reliability of semiconductor devices. It is for.
도1a 내지 도1f는 종래의 공정에 의한 플러그 리세스 발생과정을 도시한 단면도이다.1A to 1F are cross-sectional views illustrating a plug recess generation process according to a conventional process.
도2a 내지 도2g는 본 발명의 실시예에서 반도체 소자의 플러그 형성방법을 도시한 단면도이다.2A to 2G are cross-sectional views illustrating a plug forming method of a semiconductor device in an embodiment of the present invention.
상기와 같은 목적을 달성하기 위한 본 발명은 다층금속 배선 형성시 텅스텐 막 증착후 질화 티타늄 막을 적층한 다음 반도체 소자 내의 플러그를 형성하는 것을 특징으로 한다. 이를 위하여 본 발명은 콘택트 홀이 형성되어 있는 절연막 상부에 글로층을 형성하고, 상기 글로층 상부에 텅스텐 막을 증착하며, 상기 텅스텐막 상부에 질화 티타늄막을 증착한 다음, 이를 식각하여 콘택트 홀 상부에 원구형의 텡스텐 막을 남기는 것을 특징으로 한다.The present invention for achieving the above object is characterized in that when forming a multi-layered metal wiring to form a plug in a semiconductor device after the deposition of a titanium nitride film after tungsten film deposition. To this end, the present invention forms a glow layer on top of the insulating film on which the contact hole is formed, deposits a tungsten film on the glow layer, deposits a titanium nitride film on the tungsten film, and then etches the circle to form a circle on the contact hole It is characterized by leaving a spherical tungsten membrane.
여기서, 상기 텅스텐 막은 2000Å~ 3000Å로 증착하는 것이 적당하다.Herein, the tungsten film is suitably deposited at 2000 kPa to 3000 kPa.
또한, 상기 질화 티타늄막은 브레이크드로 스텝 공정으로 일부가 제거되는 것이 바람직하다.In addition, it is preferable that a part of the titanium nitride film is removed by a step process with a brake.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 일 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도2a 내지 도2g는 본 발명의 실시예에서 반도체 소자내의 플레그 형성방법을 도시한 단면도이다.2A to 2G are cross-sectional views showing a method of forming a flag in a semiconductor device in an embodiment of the present invention.
먼저, 도2a와 같이 제1배선 상부(21)에 절연막을 증착하고, 이 절연막(22)의 상부에 감광막(미도시)를 도포한 다음, 금속배선을 형성하기 위한 감광막패턴(미도시)을 형성하고, 이 감광막 패턴을 마스크로 하여 절연막(22)을 식각한 후, 감광막을 제거하여 실리콘과 금속막, 금속막과 금속막을 전기적으로 연결하는 플러그를 형성하기 위한 콘택트 홀(23)을 형성한다.First, as shown in FIG. 2A, an insulating film is deposited on the upper portion of the first wiring 21, a photosensitive film (not shown) is applied on the insulating film 22, and then a photosensitive film pattern (not shown) for forming metal wiring is formed. After etching the insulating film 22 using this photosensitive film pattern as a mask, the photoresist film is removed to form a contact hole 23 for forming a plug for electrically connecting the silicon and the metal film and the metal film and the metal film. .
그 다음, 도2b와 같이 콘택트 홀(23)이 형성되어 있는 절연막(22) 상부에 식각 배리어로서 티타늄, 또는 질화 티타늄과 같은 글로층(24)을 형성한다. 이때, 임의의 방향으로 스퍼터된 티타늄 또는 질화티타늄 입자는 콘택트 홀(23)의 폭이 좁기 때문에 콘택트 홀(23)의 우물 안쪽보다 위쪽 모서리 부분에서 상대적으로 두껍게 형성된다.Next, as shown in FIG. 2B, a glow layer 24, such as titanium or titanium nitride, is formed as an etching barrier on the insulating layer 22 on which the contact holes 23 are formed. At this time, the titanium or titanium nitride particles sputtered in any direction is formed relatively thicker in the upper corner portion than the inside of the well of the contact hole 23 because the width of the contact hole 23 is narrow.
이어서, 화학 기상 증착 방식으로 텅스텐 막(25)을 약 2000Å ~ 3000Å로 증착하여 콘택트 홀(13)을 완전히 메운다. 이때, 콘택트 홀(13) 상단에서의 증착 속도의 증가에 의해 텅스텐이 완전히 채워지지 않은 채 콘택트 홀(13)의 입구가 막혀 도2b와 같이 텅스텐 막(25)에 구멍(26)이 생기며, 텅스텐 막(25)이 상기와 같은 두께로 얇게 증착되므로 콘택트 홀(23) 상단에는 보조개와 같이 움푹들어간 딤플(27)이 형성된다.Subsequently, the tungsten film 25 is deposited at about 2000 kPa to 3000 kPa by chemical vapor deposition to completely fill the contact hole 13. At this time, the inlet of the contact hole 13 is blocked by the increase of the deposition rate at the upper end of the contact hole 13 and the hole 26 is formed in the tungsten film 25 as shown in FIG. 2B. Since the film 25 is thinly deposited to the thickness as described above, a dimple 27 recessed like a dimple is formed on the top of the contact hole 23.
그 다음, 텅스텐 막(25) 상부에 질화티타늄과 같은 금속을 스퍼터링하여 제1배리어용 금속막(28)을 증착한다. 그러나 텅스턴 막(25) 증착시 콘택트 홀(23)의 상단에 형성되어 있는 딤플(27)이 우선적인 핵생성 영역(nucleation)으로 작용하여 제1배리어용 금속막(28)은 텅스텐 막(25) 표면에 균일하게 증착되지 않고 도2c와 같이 딤플(27)영역에 더 많이 증착된다.Then, the first barrier metal film 28 is deposited by sputtering a metal such as titanium nitride on the tungsten film 25. However, when the tungsten film 25 is deposited, the dimples 27 formed at the upper end of the contact hole 23 serve as a preferential nucleation region, so that the first barrier metal film 28 is a tungsten film 25. It is not deposited uniformly on the surface, and more is deposited in the dimple 27 region as shown in FIG. 2C.
다음, 식각 배리어으로 작용하는 글로층(24)이 드러나도록 제1배리어용 금속막(28) 상부를 전면식각한다. 그러나, 제1배리어용 금속막(28)은 식각이 잘 이루어지지 않으므로 식각 전 단계로 브레이크드로 스텝(breakthrough step)공정을 식각기에서 실시한다. 이때, 식각기에서 사용되는 가스는 SF6, Cl2, Ar의 혼합가스이다. 따라서, 브레이크드로 스텝공정으로 제1배리어용 금속막(28)은 제거되어 도2d와 같이 콘택트 홀(23) 상부의 딤플(27)영역에 제1배리어용 금속막(28)의 일부만 남게된다. 이후 SF6, Ar을 이용하여 전면식각공정을 실시하면 딤플(27)영역에 남아있는 제1배리어용 금속막(28)은 텅스텐 막(25)보다 선택비가 낮기 때문에 도2e와 같이 콘택트 홀(23) 상부에 원구형으로 일정두께의 텅스텐 막(25)이 잔류하게 된다. 따라서, 콘택트 홀에 형성되어 있던 딤플에 의해 텅스텐 막이 과도하게 식각되어 플러그 리세서를 형성하는 종래와 달리 텅스텐 막(25)과 제1배리어용 금속막(28)의 선택비에 의해 플러그 리세서가 형성되지 않는다. 이때, 전면식각의 조건은 식각되는 물질의 밀도차에 의해 식각속도의 차가 발생하는 로딩 이펙터(loading effect)를 고려하여 실리콘이 위치하는 캐소드의 온도를 15도 이하로 유지한다.Next, the entire surface of the first barrier metal film 28 is etched to expose the glow layer 24 serving as an etching barrier. However, since the first barrier metal film 28 is not etched well, a breakthrough step is performed in the etcher as a pre-etch step. At this time, the gas used in the etching machine is a mixed gas of SF6, Cl2, Ar. Therefore, the first barrier metal film 28 is removed by the break-step step, so that only a part of the first barrier metal film 28 remains in the dimple 27 region above the contact hole 23 as shown in FIG. 2D. Subsequently, when the entire surface etching process is performed using SF6 and Ar, the first barrier metal film 28 remaining in the dimple 27 region has a lower selectivity than the tungsten film 25, so that the contact hole 23 as shown in FIG. The tungsten film 25 of a certain thickness remains in a spherical shape on the top. Therefore, unlike the conventional method in which the tungsten film is excessively etched by the dimples formed in the contact hole to form the plug receiver, the plug receiver is not formed by the selectivity between the tungsten film 25 and the first barrier metal film 28. Do not. At this time, the condition of the front side etching maintains the temperature of the cathode at which the silicon is located at 15 degrees or less in consideration of a loading effect in which the difference in the etching rate occurs due to the density difference of the material to be etched.
다음, 도2f와 같이 절연막(22) 상부에 질화티타늄과 같은 금속을 스퍼터링하여 금속배선에 전류가 집중되는 것을 막기 위한 제2배리어용 금속막(29)을 증착한다. 이때, 제2배리어용 금속막(29)은 콘택트 홀(23) 상부에 형성되어 있는 반구형의 텅스텐 막(25)을 따라 증착되어 콘택트 홀(23)의 상부에 반구형의 제2배리어용 금속막(28)을 형성한다.Next, as shown in FIG. 2F, a metal such as titanium nitride is sputtered on the insulating film 22 to deposit a second barrier metal film 29 to prevent current from being concentrated in the metal wiring. At this time, the second barrier metal film 29 is deposited along the hemispherical tungsten film 25 formed on the contact hole 23 to form a semi-spherical second barrier metal film on the contact hole 23 ( 28).
이어서, 도2g와 같이 제2배리어용 메탈막(29) 상부에 알루미늄과 같은 배선용 금속막(30)을 증착하여 제2금속배선을 형성한 다음, 이 배선용 금속막(30) 상부에 금속배선의 난반사를 차단하기 위한 ARC막(31)을 증착한다.Subsequently, as shown in FIG. 2G, a second metal wiring is formed by depositing a wiring metal film 30 such as aluminum on the second barrier metal film 29, and then the metal wiring is formed on the wiring metal film 30. An ARC film 31 is deposited to block diffuse reflection.
이상에서 설명한 바와 같이 본 발명은 텅스텐 막과 배선용 금속막 사이에 선택비가 상이한 배리어용 금속막을 적층한 다음 플러그를 형성함으로써 콘택트 홀 내에서 플러그 리세스가 형성되는 것을 최대한 억제하며, 배선과 배선사이의 단락 및 단선을 방지하여 반도체 소자의 신뢰성을 향상시킨다.As described above, according to the present invention, by forming a plug after stacking a barrier metal film having a different selectivity between the tungsten film and the wiring metal film, the plug recess is formed in the contact hole as much as possible. The short circuit and disconnection are prevented to improve the reliability of the semiconductor device.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980007058A KR100249321B1 (en) | 1998-03-04 | 1998-03-04 | Plug forming method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980007058A KR100249321B1 (en) | 1998-03-04 | 1998-03-04 | Plug forming method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990073859A KR19990073859A (en) | 1999-10-05 |
| KR100249321B1 true KR100249321B1 (en) | 2000-03-15 |
Family
ID=19534191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980007058A KR100249321B1 (en) | 1998-03-04 | 1998-03-04 | Plug forming method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100249321B1 (en) |
-
1998
- 1998-03-04 KR KR1019980007058A patent/KR100249321B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990073859A (en) | 1999-10-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6884710B2 (en) | Semiconductor device having multi-layer copper line and method of forming same | |
| US5284799A (en) | Method of making a metal plug | |
| US7312532B2 (en) | Dual damascene interconnect structure with improved electro migration lifetimes | |
| US7056823B2 (en) | Backend metallization method and device obtained therefrom | |
| JP2007150367A (en) | Constitutional body and method of forming enlarged head of plug used for eliminating enclosure requirement | |
| KR20100124894A (en) | Semiconductor device having deep contact structure and method of manufaturing the same | |
| US8030779B2 (en) | Multi-layered metal interconnection | |
| US6359329B1 (en) | Embedded wiring structure and method for forming the same | |
| KR100249321B1 (en) | Plug forming method of semiconductor device | |
| US6545358B2 (en) | Integrated circuits having plugs in conductive layers therein and related methods | |
| KR20030000118A (en) | Forming method for metal line of semiconductor device | |
| JP2004335721A (en) | Semiconductor device and method of manufacturing the same | |
| KR100352304B1 (en) | Semiconductor device and method of manufacturing the same | |
| KR100373706B1 (en) | a manufacturing method for wires of semiconductor devices | |
| KR100226786B1 (en) | Method for forming metal interconnection layer of semiconductor device | |
| KR100579856B1 (en) | Metal line formation method of semiconductor device | |
| KR20020086100A (en) | a forming method of a contact for multi-level interconnects | |
| KR100857989B1 (en) | Metal line formation method of semiconductor device | |
| KR100478487B1 (en) | Semiconductor device and fabrication method thereof | |
| KR100271402B1 (en) | A manufacturing method of contact holes for semiconductor devices | |
| KR100279048B1 (en) | Metal line layer formation method in semiconductor devices | |
| KR100686450B1 (en) | Method for fabricating the dual damascen interconnection in semiconductor device | |
| KR20090056685A (en) | Method for forming plug | |
| KR19980058406A (en) | Method of forming multi-layered metal wiring of semiconductor device | |
| KR19990039605A (en) | Interlayer connection method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20111121 Year of fee payment: 13 |
|
| LAPS | Lapse due to unpaid annual fee |