KR100248801B1 - Apparatus for detectiong frequency - Google Patents

Abstract

The present invention relates to a frequency detection device capable of detecting a frequency higher and lower than the operating frequency of the microprocessor, the low frequency detection unit for detecting a frequency lower than the lower frequency band of the desired frequency band and outputs a periodic clock frequency; A high frequency detector for detecting a frequency higher than a higher frequency band of a desired frequency subband and outputting a periodic clock frequency; and a periodic clock frequency input from a low frequency or high frequency detector by being enabled by a signal input from a low frequency or high frequency detector And a set signal output stage for outputting a set signal, and an error signal output means for outputting an error signal indicating that a frequency detected by being enabled by the set signal input from the set signal output means is not a desired frequency.

Description

Frequency detection device {Apparatus for detectiong frequency}

The present invention relates to a frequency detection device, and more particularly, to a frequency detection device capable of detecting a frequency higher and lower than the operating frequency of the microprocessor.

In general, a microprocessor malfunctions when the clock frequency is input at a frequency lower or higher than the operating frequency. Therefore, in order to prevent this, it is necessary to control the operation of the microprocessor by detecting a lower frequency and a higher frequency than the operating frequency through the frequency detection device.

The conventional frequency detection device is composed of a frequency sensing circuit, a buffer circuit and a register, and detects a clock frequency when it is input at a frequency lower than an operating frequency.

A conventional frequency detection apparatus will be described with reference to FIG. 1.

1 is a circuit diagram of a conventional frequency detection device, which includes a frequency detection circuit 1 for detecting a frequency lower than an operating frequency of a clock signal, and a buffering circuit for buffering and outputting a signal output from the frequency detection circuit 1 ( 2) and an error signal of a high state indicating that a frequency lower than an operating frequency has been detected by the signal buffered by the buffering circuit 2 and outputted to the output terminal OUT through an output error. The register 3 is provided.

In the frequency detection circuit 1, a clock signal is applied to a gate terminal through an input terminal IN, a PMOS transistor PM1 having a power supply voltage VDD connected to a source terminal, and a power supply voltage VDD is applied to a gate terminal. The NMOS transistor NM1 connected between the drain terminal and the ground of the PMOS transistor PM1, the diode PMOS transistor PM2 to which the power supply voltage VDD is applied to the source terminal, and the gate terminal thereof are the PMOS transistor PM1. An NMOS transistor NM2 connected to the drain terminal of the diode PMOS transistor PM2 and the ground terminal, and a capacitor CA connected between the gate terminal of the NMOS transistor NM2 and ground.

The buffer circuit 2 consists of inverters IV1 and IV2 connected in series.

The operation of the conventional frequency detection device having the structure as described above is as follows.

When a clock signal having a frequency lower than the operating frequency is applied to the gate terminal of the PMOS transistor PM1 and the PMOS transistor PM1 is turned off in the high period of the clock signal, the NMOS transistor NM1 turned on by the low frequency. Discharge operation of the capacitor CA through the N s occurs sufficiently, and the voltage of the node N1 is lowered below the threshold voltage of the NMOS transistor NM2, so that the NMOS transistor NM2 is turned off. At this time, the signal of the output node N2 becomes high by the power supply voltage VDD applied through the PMOS transistor PM2.

Subsequently, when the PMOS transistor PM1 is turned on in the low period of the clock signal, since the channel length of the NMOS transistor NM1 is larger than that of the PMOS transistor PM1, the capacitor CA is supplied with power through the PMOS transistor PM1. Charged by the voltage VDD, and the voltage of the node N1 is raised above the threshold voltage of the NMOS transistor NM2, so that the NMOS transistor NM2 is turned on. At this time, the output node N2 is turned low because a voltage is applied to the ground through the NMOS transistor NM2.

That is, when a clock signal having a frequency lower than the operating frequency is input as described above, the output node N2 of the frequency detection circuit 1 repeats the high and low states, wherein the frequency detection circuit 1 outputs the output node ( When the high signal of N2) is output to the buffer circuit 2, the buffer circuit 2 buffers the input signal and inputs it to the set terminal of the register 3, and then the register 3 receives the set terminal ( According to the high signal input to the set), a high state error signal indicating that a frequency lower than the operating frequency is inputted is outputted to the output terminal OUT through an error output terminal error.

Next, when a clock signal having a frequency higher than the operating frequency is applied to the gate terminal of the PMOS transistor PM1, the voltage of the node N1 maintains a high voltage state of a predetermined level or more, which is a high period of the clock signal. Sufficient discharge operation while the PMOS transistor PM1 is turned off due to the high frequency, even though the charge of the capacitor CA has to be sufficiently discharged through the NMOS transistor NM1 when the PMOS transistor PM1 is turned off at. This is because the PMOS transistor PM1 is turned on in the low period of the clock signal in this state to charge the voltage of the node N1. When the voltage of the node N1 is higher than the threshold voltage of the NMOS transistor NM2, the NMOS transistor NM2 is turned on so that the voltage of the output node N2 becomes low. At this time, the voltage of the output node N2 is kept high by the PMOS transistor PM2, but the channel length of the PMOS transistor PM2 is designed to be large so that the output node N2 is turned on when the NMOS transistor NM2 is turned on. The voltage goes low. At this time, when the frequency detection circuit 1 outputs the low signal of the output node N2 to the buffer circuit 2, the buffer circuit 2 buffers it and inputs it to the set terminal of the register 3. The register 3 then outputs an error signal in a low state to the output terminal OUT according to a low signal input to the set terminal set, indicating that the register 3 is in a normal frequency state even though a frequency higher than an operating frequency is input.

Therefore, the conventional frequency detection device as described above detects a clock signal having a frequency lower than the operating frequency and outputs an error signal in a high state through the register 3, whereby the microprocessor malfunctions due to the low frequency. However, when a clock signal of a frequency higher than the operating frequency is input, the microprocessor may malfunction due to a high frequency by not detecting the signal and recognizing it as a clock signal of a normal frequency.

Accordingly, an object of the present invention is to provide a frequency detecting apparatus capable of detecting a clock signal of a high frequency as well as a frequency lower than an operating frequency.

1 is a circuit diagram of a conventional frequency detection device.

2 is a circuit diagram of a frequency detection device according to an embodiment of the present invention.

3A to 3E are characteristic views of a frequency detection device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: low frequency detection unit 11: low frequency detection circuit

12: inverter 20: high frequency detection unit

21: high frequency detection circuit 22; inverter

23: sampling unit 24: NAND gate

30: set signal output unit 40: error signal output unit

A frequency detecting device of the present invention for achieving the above object comprises a frequency detecting device for detecting whether a clock signal has a frequency within an operating frequency band between a first frequency and a second frequency, wherein the clock signal is the first signal; Low frequency detection means for detecting when input at a frequency lower than the frequency; High frequency detecting means for detecting when the clock signal is input at a frequency higher than the second frequency; Outputting a set signal enabled when the clock signal is input at a frequency lower than the first frequency or at a frequency higher than the second frequency in response to the signals output from the low frequency detecting means and the high frequency detecting means, respectively. Set signal output means for; And an error signal output means for outputting an error signal indicating that the frequency of the clock signal is out of the operating frequency band in response to the set signal output from the set signal output means.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a circuit diagram of a frequency detection device according to an embodiment of the present invention.

Referring to FIG. 2, the frequency detecting apparatus of the present invention includes a low frequency detector 10 for detecting when a clock signal is input at a frequency lower than f1 when an operating frequency band of a desired clock signal is f1 to f2; When the clock signal is input at a frequency higher than f2, a signal is output from the high frequency detector 20, the low frequency detector 10, and the high frequency detector 20 for detecting the signal, and outputs a set signal. To output an error signal indicating that the frequency of the clock signal which is enabled and inputted in response to the set signal output unit 30 and the set signal output from the set signal output unit 30 is not a desired frequency. It consists of an error signal output unit 40.

Specifically, the low frequency detector 10 detects a frequency lower than the desired frequency f1 and outputs a periodic clock frequency, and the low frequency detector 10 for inverting the clock frequency output from the low frequency detector circuit 11. It consists of an inverter 12.

The low frequency detection circuit 11 has a PMOS transistor PM11 having a clock signal applied to the gate terminal, a source terminal connected to the power supply voltage VDD, a power supply voltage VDD applied to the gate terminal, and a PMOS transistor PM11. NMOS transistor (NM11) connected between the drain terminal of the () and the ground, the source PMOS transistor (PM12) connected to the power supply voltage (VDD), the gate terminal is connected to the drain terminal of the PMOS transistor (PM11) And an NMOS transistor NM12 connected between the drain terminal of the diode PMOS transistor PM12 and ground, and a capacitor CA11 connected between the gate terminal of the NMOS transistor NM12 and ground, which is a conventional frequency detection circuit. Same as the configuration.

Next, the high frequency detector 20 detects a frequency higher than the desired frequency f2 and outputs a periodic clock frequency, and inverts the clock frequency output from the high frequency detection circuit 21. Of the inverter 22, the sampling unit 23 for sampling the clock frequency output from the inverter 22 in response to the clock signal input through the input terminal IN, and the sampling unit 23 input to the one input terminal. It is composed of a NAND gate 24 that is enabled by an output signal and outputs a clock signal input to the type force stage.

In the high frequency detection circuit 21, a clock signal is applied to a gate terminal, a PMOS transistor PM21 is connected to a power source voltage VDD, a power supply voltage VDD is applied to a gate end, and a PMOS transistor PM21 is applied. NMOS transistor (NM21) connected between the drain terminal and ground of the (), the source terminal is connected to the power supply voltage (VDD) diode PMOS transistor (PM22), the gate terminal is connected to the drain terminal of the PMOS transistor (PM21) , NMOS transistor NM22 connected between the drain terminal of the diode PMOS transistor PM22 and ground, and a capacitor CA21 connected between the gate terminal of the NMOS transistor NM22 and ground, which is a conventional frequency detection circuit. Same as the configuration.

The sampling unit 23 of the high frequency detector 20 samples and outputs the clock frequency from the inverter 22 input to the input terminal D in response to the falling edge of the clock signal input to the clock terminal CK. D flip-flop (D f / f) output to the terminal (Q).

Next, the set signal output unit 30 is provided as a NAND gate that receives an output signal of the low frequency detector 10 to one input terminal and receives an output signal of the high frequency detector 20 to a type force terminal. .

Finally, the error signal output unit 40 includes a register RG for outputting a high error signal to an output terminal in response to a signal output from a NAND gate input to a set terminal. do.

Referring to the operation of the frequency detection device of the present invention having the above structure is as follows.

When the frequency band of the desired clock signal is f1-f2, and the frequency of the clock signal input through the input terminal IN is lower than f1, the low frequency detector 10 detects this and sets the periodic clock frequency to the set signal output unit 30. ), And the high frequency detector 20 outputs an output signal in a low state to the set signal output unit 30. Subsequently, the set signal output unit 30 receives and outputs the output signals of the low frequency detector 10 and the high frequency detector 20 to one input terminal and a type force terminal, respectively, to register the register RG of the error signal output unit 40. The set signal set for setting is output to the error signal output unit 40, and the error signal output unit 40 then indicates that a clock signal having a frequency lower than a desired frequency is input by the input set signal set. Send an error signal (error) to the output (OUT).

On the other hand, if the frequency of the clock signal input through the input terminal (IN) is higher than f2, the high frequency detector 20 detects it and outputs a periodic clock frequency to the set signal output unit 30, the low frequency detector 10 The output signal in the low state is output to the set signal output unit 30. Subsequently, the set signal output unit 30 receives and outputs the output signals of the low frequency detector 10 and the high frequency detector 20 to one input terminal and a type force terminal, respectively, to register the register RG of the error signal output unit 40. A set signal set for setting is output to the error signal output unit 40, and the error signal output unit 40 then outputs an error signal indicating that a clock signal having a frequency higher than a desired frequency is inputted by the input set signal. error) to the output (OUT).

3A to 3E, the operation of the frequency detection device of the present invention will be described in more detail.

3A illustrates an operating characteristic of the high frequency detector 20 when the frequency of the clock signal input through the input terminal IN is higher than f2 when the frequency band of the desired clock signal is f1 to f2. The signal waveform of the clock signal input through the input terminal IN, (a2) is the output signal waveform of the high frequency detection circuit 21, (a3) is the output signal waveform of the inverter 22, (a4) is the sampling section 23 (A5) shows the characteristics of the output signal waveform of the NAND gate 24, respectively.

In Fig. 3A, the output signal a2 of the high frequency detection circuit 21 goes low in the high frequency band (frequency of the clock signal higher than f2) by the operation described above in the prior art, and is inverted through the inverter 22. The output signal of the inverter 22 is then turned high (a3). Subsequently, the output signal of the inverter 22 in the high state is sampled by the D flip-flop D f / f which operates in response to the falling edge of the clock signal, so that the high state signal is D flip-flop D f / f. Output signal a4, and the NAND gate 24 is enabled accordingly, so that the clock signal input through the input terminal IN is sent to the output signal a5 of the NAND gate 24 as it is. It is input as a set signal. Therefore, the register RG outputs an error signal of a high state indicating that a frequency higher than an operating frequency is input to the output terminal OUT through an error output terminal error.

3B illustrates an operating characteristic of the high frequency detector 20 when the frequency of the clock signal input through the input terminal IN is lower than f2 when the frequency band of the desired clock signal is f1 to f2, (b1) Is a signal waveform of the clock signal input through the input terminal IN, (b2) is an output signal waveform of the high frequency detection circuit 21, (b3) is an output signal waveform of the inverter 22, (b4) is a sampling unit ( An output signal waveform of 23) (b5) shows characteristics of the output signal waveform of the NAND gate 24, respectively.

As shown in the figure, the high frequency detection circuit 21 outputs a signal of a periodic clock frequency at a frequency lower than the reference frequency f2 by the operation as described above in the prior art, while the capacitor in the high frequency detection circuit 21 ( A signal equal to the clock signal is output after a predetermined time as a delay time by the charge / discharge time of CA21) (b2). The output signal b2 of the high frequency detection circuit 21 is inverted through the inverter 22 and applied to the input of the D flip-flop D f / f. Subsequently, the D flip-flop D f / f samples the output signal from the inverter 22 in response to the falling edge of the clock signal to output the low signal b4, and receives the low signal. The NAND gate 24 continues to output the high signal b5.

3C illustrates an operating characteristic of the frequency detecting apparatus of the present invention when the frequency of the clock signal input through the input terminal IN is lower than f1 when the frequency band of the desired clock signal is f1 to f2. ) Is a signal waveform of a clock signal input through the input terminal IN, (c2) is an output signal waveform of the high frequency detection circuit 21, (c3) is an output signal waveform of the inverter 22, and (c4) is a sampling unit. The output signal waveform of (23), (c5) is the output signal waveform of the NAND gate 24, (c6) is the output signal waveform of the low frequency detection circuit 11, (c7) is the output signal waveform of the inverter 12, (c8) shows the output signal waveform of the set signal output section 30, and (c9) shows the characteristics of the output signal waveform of the error signal output section 40, respectively.

As shown in FIG. 3C, when the frequency of the input clock signal is lower than f1, the high frequency detector 20 outputs the signal c5 in a high state to enable the NAND gate NAND, and the low frequency detector 10. ) Generates a periodic clock frequency signal (c6, c7), and outputs a high-level error signal through the error output terminal (error) indicating that the register 40 is set by this signal, indicating that the frequency of the abnormal clock signal is abnormal. Will be exported to (OUT).

3D illustrates an operating characteristic of the frequency detecting apparatus of the present invention in a normal state where a frequency of a clock signal input through the input terminal IN is higher than f1 and lower than f2 when the frequency band of the desired clock signal is f1 to f2. , (d1) is the signal waveform of the clock signal input through the input terminal IN, (d2) is the output signal waveform of the high frequency detection circuit 21, (d3) is the output signal waveform of the inverter 22, (d4) Is an output signal waveform of the sampling unit 23, (d5) is an output signal waveform of the NAND gate 24, (d6) is an output signal waveform of the low frequency detection circuit 11, (d7) is an output of the inverter 12 The signal waveform (d8) represents the output signal waveform of the set signal output section 30, and (d9) represents the characteristics of the output signal waveform of the error signal output section 40, respectively.

Referring to FIG. 3D, when the frequency of the input clock signal is between the frequency bands f1 to f2 of the normal state, the low frequency detector 10 and the high frequency detector 20 respectively output a high state signal to register 40. The low level signal is output to the output terminal OUT through an error output terminal (error) by outputting a low level signal to the set terminal of.

3E illustrates an operating characteristic of the frequency detecting apparatus of the present invention when the frequency of the clock signal input through the input terminal IN is higher than f2 when the frequency band of the desired clock signal is f1 to f2, (e1 ) Is the signal waveform of the clock signal input through the input terminal IN, (e2) is the output signal waveform of the high frequency detection circuit 21, (e3) is the output signal waveform of the inverter 22, and (e4) is the sampling unit. The output signal waveform of (23), (e5) is the output signal waveform of the NAND gate 24, (e6) is the output signal waveform of the low frequency detection circuit 11, (e7) is the output signal waveform of the inverter 12, (e8) shows the output signal waveform of the set signal output section 30, and (e9) shows the characteristics of the output signal waveform of the error signal output section 40, respectively.

Referring to FIG. 3E, when the frequency of the input clock signal is greater than f2, the low frequency detector 10 outputs a high state signal e7 to enable the NAND gate NAND, and the high frequency detector 20 By generating a signal e5 of a periodic clock frequency, the register 40 is set by this signal, and an error signal of a high state indicating the frequency of an abnormal clock signal is transmitted to the output terminal OUT through an error output terminal error. Will be exported.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

As described above, the frequency detection device of the present invention detects frequencies of the upper band and the lower band of the frequency band detected through the input terminal through the low frequency detector and the high frequency detector, respectively, thereby lowering the frequency lower than the driving frequency of the microprocessor. And a high frequency can be detected, thereby preventing malfunction of the microprocessor operating on a clock signal of an incorrect frequency.

Claims (6)

A frequency detection device for detecting whether a clock signal has a frequency within an operating frequency band between a first frequency and a second frequency, Low frequency detection means for detecting when the clock signal is input at a frequency lower than the first frequency; High frequency detecting means for detecting when the clock signal is input at a frequency higher than the second frequency; Outputting a set signal enabled when the clock signal is input at a frequency lower than the first frequency or at a frequency higher than the second frequency in response to the signals output from the low frequency detecting means and the high frequency detecting means, respectively. Set signal output means for; And Error signal output means for outputting an error signal indicating that the frequency of the clock signal is outside the operating frequency band in response to the set signal output from the set signal output means; Frequency detection device comprising a. The low frequency detection means of claim 1, A low frequency detection circuit unit outputting a periodic clock frequency of the clock signal when the frequency of the clock signal is lower than the first frequency in response to the clock signal, The low frequency detection circuit unit, A first PMOS transistor having the clock signal applied to a gate terminal and a source terminal connected to a power supply voltage terminal; A first NMOS transistor connected to a drain terminal and a ground power supply terminal of the first PMOS transistor by applying a power supply voltage to a gate terminal; A second PMOS transistor diode-connected to a power supply voltage terminal; A second NMOS transistor having a gate end connected to a drain end of the first PMOS transistor, and connected between a drain end of the second PMOS transistor and a ground power supply end; And A capacitor connected between the gate terminal and the ground of the second NMOS transistor Frequency detection device comprising a. The method of claim 1, wherein the high frequency detection means, A high frequency detection circuit unit outputting a periodic clock frequency of the clock signal when the frequency of the clock signal is higher than the second frequency in response to the clock signal; Sampling means for sampling a periodic clock frequency of the clock signal output from the high frequency detection circuit portion in response to the clock signal; And NAND means for receiving the output signal of the sampling means and the clock signal NAND, The high frequency detection circuit unit, A first PMOS transistor having the clock signal applied to a gate terminal and a source terminal connected to a power supply voltage terminal; A first NMOS transistor connected to a drain terminal and a ground power supply terminal of the first PMOS transistor by applying a power supply voltage to a gate terminal; A second PMOS transistor diode-connected to a power supply voltage terminal; A second NMOS transistor having a gate end connected to a drain end of the first PMOS transistor, and connected between a drain end of the second PMOS transistor and a ground power supply end; And A capacitor connected between the gate terminal and the ground of the second NMOS transistor, And an output signal of the high frequency detection circuit unit is output from a common drain terminal of the second PMOS transistor and the second NMOS transistor. The method of claim 3, wherein the sampling means, D flip-flop for receiving the clock signal as a clock terminal, receiving the output signal of the high frequency detection circuit unit as a data terminal, and synchronizing with the clock signal to export the output signal of the high frequency detection circuit unit as an output terminal. Frequency detection device comprising a. The method of claim 1, wherein the set signal output means, NAND means for receiving and outputting signals output from said low frequency detection means and signals output from said high frequency detection means Frequency detection device comprising a. The method of claim 1, wherein the error signal output means, A register for receiving a set signal output from the set signal output means through a set terminal and outputting a high level signal to the output terminal in response thereto. Frequency detection device comprising a.

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