KR100247218B1 - Signal generating circuit - Google Patents

Abstract

A circuit for generating a composite signal includes means for generating count data by counting a received clock, a reference value generator for generating reference data for setting a predetermined timer period, and inputting the count data and reference data, Comparing means for comparing the two data and generating a timer signal when the data is the same, and receiving a predetermined signal, and sequentially detecting the received predetermined edge change by an edge selection signal output from the control unit. And means for automatically capturing the received signal by receiving and storing the count data at the time of detection.

Description

Signal generating circuit

The present invention relates to a signal generating circuit, and more particularly to a circuit capable of generating signals of various functions in a single integrated circuit.

In general, a timer / counter circuit is a circuit for receiving a clock signal and generating a signal having a predetermined period. FIG. 1 illustrates a configuration of a timer / counter (KS56C220 / KS56C820 / KS56C1620) manufactured and sold by Samsung of Korea. . The timer / counter shown in FIG. 1 includes a clock selector, an 8-bit timer / counter mode register TMOD, an 8-bit timer / counter counter register TCNT, an 8-bit timer / counter reference register TREF, and 8 bits. Comparator, timer output latch TOL and the like.

In the above configuration, when TMOD.2 is set and an internal clock is selected as the clock source of the counter TCNT by TMOD.6, the timer / counter function is performed. In addition, a reference value of a timer is set in the reference register TREF and a count clock frequency is determined by the mode register TMOD. In this state, when the timer / counter interrupt is enabled and TMOD.3 is set, the timer / counter is driven. When the timer / counter is enabled, the value of TCNT is increased each time a clock signal determined by TMOD is received. At this time, the comparator compares the values of the TCNT and the TREF. If the two output values are the same, the comparator sets the interrupt request flag IRQT signal of the timer / counter and inverts the TOL to generate an interrupt signal. At this time, the contents of the TCNT are initialized, and the counter is restarted by the clock signal received continuously. Therefore, when the timer period is determined by the TREF and TMOD, the timer / counter periodically generates a timer interrupt signal.

However, such a timer / counter did not generate another signal using the timer other than a timer interrupt signal having a predetermined period. For this reason, in the related art, a PWM generator (Pulse Width Modulator), an event counter, an event counter, a capture block, and a capture block that use the timer function as described above have to be separately provided and operated. However, in the case where the above blocks are to be combined (for example, an integrated circuit such as an A / D converter), the respective functions must be provided in a discrete manner. In this case, when the functions are integrated, the timer occupies the largest chip lay out. Therefore, using the timer / counter as described above, it is easy to configure the functions into a single integrated circuit, and thus it is possible to easily implement an integrated circuit having a complex function and miniaturizing the chip size.

Accordingly, an object of the present invention is to provide an integrated circuit capable of performing a complex function using a single timer circuit.

Another object of the present invention is to provide an integrated circuit capable of performing a complex function such as a PWM function and a capture function in addition to the counter and timer functions using a single timer circuit.

A composite signal generating circuit according to an embodiment of the present invention for achieving the above object, of the plurality of clocks by the input means for inputting the mode selection signal output from the controller therein and the clock selection signal of the mode selection signal; A count means for generating a count data by selecting a corresponding clock, counting the selected clock, a reference value generator for generating reference data for setting a timer period, and inputting the count data and the reference data, Comparison means for generating the timer signal at the time when the two data are the same by comparing the two data, the clock signal, the count data, the timer signal and the reference data are input, and one cycle is set by the count data. Means for generating a PWM signal that is enabled during the reference data period And receiving a predetermined signal, sequentially detecting an edge change of the signal input by an edge selection signal among the mode selection signals, and automatically storing the counted data by storing the count data at the edge detection time point. It is characterized by consisting of means.

1 is a block diagram of a conventional timer / counter circuit

2 is a block diagram of a composite signal generation circuit according to the present invention

3 is a waveform diagram of generation of the PWM signal among the signals generated by FIG.

4 is a waveform diagram of generation of a capture signal among the signals generated by FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an integrated circuit having a composite function according to an embodiment of the present invention.

All selection means are connected to the control unit, and perform a function of applying the clear signal, the counter enable signal, the clock selection signal, and the capture selection signals output from the control unit to the integrated circuit. The mode selecting means is composed of mode registers MOD1-MOD8, and the mode registers are respectively connected to a control unit. The MOD1 is a count enable signal, the MOD2 is a clear signal for the integrated circuit of the present invention, the MOD3-MOD5 is a signal for selecting a clock source, and the MOD7-MOD8 is an energy of a received CAP signal. It becomes a capture selection signal for detection.

The counting means for generating the count data receives an internal clock and an external clock, selects a clock by the clock selection signal, and counts the selected clock to generate count data when the counter enable signal is generated. The means for generating the counter data receives a clock and an external clock of the control unit, a clock selector 11 for selecting a clock source corresponding to the clock selection signal and outputting the clock signal, and receiving the selected clock and scaling the count clock. A 2-bit prescaler 12 and an output of the prescaler 12 and the count enable signal are received and logically multiplied so that the output of the prescaler 12 is counted when the count enable signal is set. And a counter 14 for counting the output of the gate 13 by a clock and generating count data.

The means for generating a timer signal has reference data set at a predetermined timer signal period, and performs the function of receiving the count data, comparing the reference data with the reference data, and generating a timer signal when the two data values are the same. The means for generating the timer signal includes a reference value generator 17 storing reference data having a predetermined period, a comparator 18 for receiving the count data and the reference data and comparing the two data to generate a timer signal if the same; Receives and multiplies the output of the comparator 18 and the signal of the MOD6 to receive a gate 19 for generating a timer interrupt set signal when the timer signal is generated, and receives the output of the gate 19 as a set signal and receives the signal of the MOD2 as a clear signal. And a timer interrupt generator 20 for generating a timer interrupt signal when the timer signal is generated, a toggle latch 22, gates 21, 23, 24, 25, and a buffer 26. The timer signal outputs the comparator 18 to the outside. It is composed.

The means for generating a PWM signal has a function of receiving the selected clock, the count data, the reference data and the timer signal and generating a PWM signal by the reference data set to a width of the PWM signal in units of periods of the count data. Perform. The means for generating the PWM signal receives the output of the prescaler 12, the output of the counter 14, the output of the comparator 18 and the output of the reference value generator 17, the period set by the reference data in units of the count period And a means for outputting the PWM signal generated from the PWM generator 27 to the outside, comprising a PWM generator 27 for generating a PWM signal set while the gate 23, 24, 25 and the buffer 26 are generated.

The means for generating a capture signal receives a predetermined signal from the outside and receives the count data, the edges of the signal received by the capture selection signal are sequentially selected and store count data between the selected edge and the edge. To generate a capture signal of the received signal. The capture signal generating means receives an edge signal to be captured and an edge selector 28 and a first edge signal for sequentially selecting a first edge signal-a third edge signal of the signal received by the capture selection signal. A first register 29 to a third register 31 which are sequentially enabled by a third edge signal and sequentially store count data received from the counter 14, and an output of the edge selector 28 to capture a capture interrupt signal. It consists of a capture interrupt generator 32 that occurs.

3 is a waveform diagram of a PWM signal output from the PWM generator 27, wherein the period of the output signal is determined by the count period of the counter 14, and the high duty of the PWM signal is the reference of the reference value generator 17 of the reference value generator 17. Determined by the data.

4 is a waveform diagram of the generation of the capture signal. When the CAP signal is received, the edge selector 28 detects and outputs the edge signals ES1-ES3 of the CAP signal and sequentially outputs the first register 29-by the edge signals ES1-ES3. Three registers 31 are sequentially enabled to store the count data of the counter 14, respectively.

Based on the configuration of FIG. 2 described above, an embodiment of the present invention will be described in detail with reference to the waveform diagrams of FIGS. 3 and 4.

First, in order to perform a counter function, a timer signal generation function, a PWM signal generation function, and a capture function, the controller should output selection signals for controlling the same. To this end, the controller first stores reference data for setting a period of the corresponding signal in the reference value generator 17 in order to generate a timer signal or generate a PWM signal. The control unit outputs a control signal corresponding to the function set in the mode register 10 to perform the complex function as described above. At this time, the mode register 10 is composed of MOD1-MOD8, the MOD1 generates a signal to enable or disable the input of the count clock of the counter 14, MOD3-MOD5 for selecting the type of the clock. A signal is generated, and the MOD7-MOD8 generates a signal for selecting an edge of the CAP signal.

First, a generation process of count data will be described.

The clock selector 11 selects a corresponding clock source among the internal clock and the external clock received by the clock selection signal output from the MOD3-MOD5 and applies it to the prescaler 12. The prescaler 12 then scales the received clock source to generate a count clock. At this time, the gate 13 gates the count clock according to the state of the count enable signal output from the MOD1, and the counter 14 counts the count clock outputting the gate 13 to generate count data. Accordingly, the counter 14 counts a clock determined by an external selection to generate count data, thereby diversifying the clock selection of the count data.

Second, look at the generation process of the timer signal.

In this case, the reference value generator 17 stores the reference data designated by the program in advance in order to determine the generation period of the timer signal. Then, the comparator 18 receiving the output count data of the counter 14 and the reference data compares the two received data and generates a timer signal indicating that the set time is reached when the values of the two data are the same. In this case, the timer mode is set by the MOD2 or MOD6 register, and gate 19 is gated by the timer signal to apply the set signal to the timer interrupt generator 20. Then, the timer interrupt generator 20 which receives the timer signal as a set signal is triggered to inform the controller that the timer interrupt signal has been generated. In addition, the timer signal for outputting the comparator 18 is applied to a toggle output latch 22, thereby toggling the timer signal, it is possible to output the timer signal to the outside. In this case, the TOE1 signal is a control bit for enabling the output of the received timer signal to the outside, and the P3.1 signal is a signal for driving the timer signal outputted by the output enable, and the PM3.1 signal is a timer signal. It is applied as a control signal for enabling / disabling the state of the buffer 26 to be finally output. When the external output function of the timer signal is not selected, the gate 21 applies a clear signal to the toggle latch 22. Accordingly, the counter 14 can be used as a timer or an event counter, and a timer signal generated from the timer can be used as a timer interrupt signal or output to the outside.

Third, look at the process of generating a PWM signal.

The PWM generator 27 receives the clock output from the prescaler 12, the count data output from the counter 14, the comparison signal output from the comparator 18, and the reference data output from the reference value generator 17 to generate a PWM signal. do. At this time, the reference value generator 17 stores in advance a reference data value for determining the high duty of the PWM signal. Accordingly, the PWM 27 generates a logic signal having a high duty during the period set by the reference data in the period of the counter 14, and in the comparator 18, the same signal generator with the same count data as the count data is cleared so that the logic signal having a low duty is generated. Occurs. Therefore, the PWM generator 28 can be seen that the width of the PWM signal is determined according to the setting of the reference data as shown in FIG. The PWM signal is output to the outside via the gates 23, 24, 25 and the buffer 26, where the TOE1 signal is a control bit for enabling the output of the received PWM signal to the outside, and the P3.1 signal is the output. A signal for driving a PWM signal that is enabled and output, and a PM3.1 signal is applied as a control signal for enabling / disabling a state of the buffer 26 that finally outputs the PWM signal. The PWM signal output as described above is converted into a DC signal through a filter and then applied as a drive signal such as a motor.

Fourth, the generation process of the capture signal will be described.

The edge selector 28 sequentially detects and outputs edges of the CAP signal received by the edge selection signal outputting the MOD7-MOD8. Here, the CAP signal is a signal for triggering a capture function. If the value for the trigger section of the signal is obtained, the CAP signal can be captured. Therefore, the edge selector 28 sequentially detects edges of the CAP signal received by the edge selection signal. Here, it is assumed that the first edge signal ES1-third edge signal ES3 is generated as shown in FIG. In this case, the ES1-ES3 signals are sequentially generated, when the ES1 signal is generated, the first register 29 is enabled, when the ES2 signal is generated, the second register 30 is enabled, and when the ES3 signal is generated, the third register is enabled. Register 31 is enabled. In addition, since the first register 29 and the third register 31 are respectively connected to the counter 14 with their input terminals, the first register 29 and the third register 31 are enabled when the ES1-ES3 signal is generated, respectively, and store count data of the corresponding time. Therefore, the first register 29 is enabled at the first rising edge of the CAP signal to store the count data CNT1 at that time, and the second register 30 is the first falling edge of the CAP signal. Is enabled at the point of time, and stores the count data CNT2 at that time, and the third register 31 is enabled at the second rising edge of the CAP signal to store the count data CNT3 at that time. A capture interrupt signal is generated and applied to the controller. In this case, the controller may generate an interrupt signal for each edge detection of the CAP signal by writing the capture selection signal to the MOD7-MOD8, and the stored data values of the first register 29 and the third register 31 Each change can generate an interrupt signal.

As described above, the present invention can manufacture an integrated circuit that generates a composite signal that performs a counter function, a timer signal generation function, a PWM signal generation function, and a capture signal generation function by using a single timer circuit. In this case, By using a timer circuit that occupies the largest area on the chip layout in common, there is an effect that the chip size can be reduced when a single integrated circuit is used.

Claims (7)

In the signal generating circuit, Counting means for counting the received clock to generate count data; A reference value generator for generating reference data for setting a predetermined timer period; Comparison means for inputting the count data and the reference data, and comparing the two input data and generating a timer signal when the count data and the reference data are the same; Receives a predetermined signal, sequentially detects the edge change of the received predetermined signal by the edge selection signal output from the control unit, and automatically receives the received signal by receiving and storing the count data at the edge detection point. A composite signal generation circuit, characterized in that consisting of means for capturing. The method of claim 4, wherein the counting means, A clock selector which inputs internal and external clocks and selects a corresponding one of the two input clocks by a clock selection signal; A counter for counting the selected clock to generate the count data; And a means for inputting the timer signal of the clear signal output from the control unit, and applying the signal as an initializing signal of the counter and a signal for setting the operation period of the counter by logically combining the two signals inputted. Signal generating circuit. 7. The composite signal generation circuit according to claim 6, further comprising means for inputting the output of the comparator means as a set signal and generating a timer interrupt signal to the controller when the timer signal is generated. According to any one of claims 1 to 3, wherein the means for generating the capture signal, An edge selector for detecting and sequentially outputting a first rising edge signal, a first falling edge signal, and a second rising edge signal of the signal received by the edge selection signal generated from the controller; A first input of the count data, each of which is activated by the corresponding first rising edge signal, first falling edge signal, and second rising edge signal to respectively store the count data input at a corresponding time; A register, a second register and a third register, And means for inputting the output of the edge selector as a set signal and generating a capture interrupt signal to the controller when the edge detection signal is generated. Input means for internally inputting a mode selection signal output from the control unit; Counting means for selecting a corresponding one of a plurality of clocks by a clock selection signal of the mode selection signal, and counting the selected clock to generate count data; A reference value generator for generating reference data for setting a timer period; Comparison means for inputting the count data and the reference data, and comparing the two inputted data to generate the timer signal at a time point when the two data are the same; Means for inputting the clock signal, count data, timer signal, and reference data, and generating a PWM signal in which one cycle is set by the count data and enabled during the reference data period; Receiving a predetermined signal, sequentially detecting an edge change of the signal input by an edge selection signal among the mode selection signals, and automatically storing the count data at the edge detection time point to automatically capture the received signal; A composite signal generating circuit comprising a means. The combined signal generating circuit according to claim 5, further comprising means for inputting the output of the comparing means as a set signal and generating a timer interrupt signal and outputting the signal to the controller when the timer signal is generated. . The method of claim 5 or 6, wherein the means for generating the capture signal, An edge selector for detecting and sequentially outputting a first rising edge signal, a first falling edge signal, and a second rising edge signal of the signal received by the edge selection signal generated from the controller; A first input of the count data, each of which is activated by the corresponding first rising edge signal, first falling edge signal, and second rising edge signal to respectively store the count data input at a corresponding time; A register, a second register and a third register, And means for inputting the output of the edge selector as a set signal and generating a capture interrupt signal to the controller when the edge detection signal is generated.