KR100246729B1 - Low capacitor varistor - Google Patents

Abstract

The present invention is to provide a varistor with low capacitance and high resistance to deformation or breakage during manufacture and handling. In order to reduce the capacity of the chip varistor, the varistor part is thinly formed so as to reduce the surface area of both sides of the varistor part in contact with the external electrode, and the support layer is formed by laminating a ceramic sheet having a very low dielectric constant on both sides of the varistor part to form and sinter the varistor. It is composed of low capacitance chip varistor by forming part and supporting layer integrally and forming external electrode connected to internal electrode on both sides. Low-capacitance chip varistors can be applied to high-speed signal circuits that are difficult to be applied to conventional varistors because they are supported by the support layer and reinforced by the support layer, while the varistor portion is thinly formed so that the capacitance of the capacitor is small. It has the advantage of protecting electronic components from internal or external surges.

Description

Low capacitance chip varistor

This invention relates to stacked chip varistors that can be used in electronic circuits that require low capacitance and protection of electronic components that can be damaged by external and internal surges in electronic devices.

In recent years, high-density mounting has been rapidly progressed by SMD and miniaturization of electronic components according to the trend of lighter and shorter and higher functionality of electronic devices. Since the signal speed of circuits in SMD electronics is more than MHz, the capacitance must be lowered below 10pF, and sometimes lowered below 5pF in order to operate properly at such a high signal rate.

In order to meet these requirements, the development of chip-type varistors in the form of chips is rapidly progressing. However, the stacked chip varistors manufactured by stacking sheets have a low dielectric constant chip varistor because the materials constituting the varistors have a high dielectric constant. There are many problems in manufacturing. That is, since the material of the chip varistor has a large dielectric constant, if the area of both ends in contact with the external electrode is large, the thickness of the varistor of the capacitance should be reduced regardless of the area of the electrode. However, if the varistor is made thin in order to reduce the capacitance of the varistor to 10 pF or less, in particular 5 pF or less, the varistor may be thinned to correspond to the low capacitance required because of the risk of deformation or breakage during sintering and lamination after lamination. As a result, stacked chip varistors are not known to reduce the capacitance associated with operating speeds below 1000 pF. As an alternative to this problem, a low dielectric constant SrTiO ₃ -based varistor may be used, but this or high speed operation characteristics and stability were not satisfactory.

In order to reduce the area of the varistor in contact with the external electrode as much as possible, the varistor may be deformed during the manufacture or handling of the varistor while minimizing the thickness of the varistor in order to reduce the area of the varistor in contact with the external electrode in order to exhibit a low capacitance capacity that can be used in a high speed signal circuit. It is to provide a chip varistor that does not break and exhibits excellent varistor characteristics.

Another object of the present invention is to provide a chip varistor capable of miniaturization of electronic products due to its small footprint and its ability to be connected to high-speed signal lines.

The object of the above-described invention is to form a varistor by stacking a plurality of thin sheets, and to form a varistor on the both surfaces of the varistor by laminating and sintering a support layer composed of a ceramic sheet having a very low dielectric constant on both surfaces of the varistor, thereby forming a cap pattern. This is achieved by the chip varistor of the present invention which minimizes the area of both sides related to the capacity of the switch.

As described above, in the chip varistor of the present invention, the layer constituting the varistor has a thin thickness, and on both sides thereof, a support layer made of a ceramic sheet having a very low dielectric constant is formed so that the varistor is not deformed or damaged during the forming and use of the varistor, and the capacitance is also reduced. Since the area of both sides in contact with the external electrode which is related to the capacitance is small, the capacitance of the capacitance can be lowered.

In the present invention, the varistor layer is manufactured by laminating a plurality of sheets including ZnO as a main raw material and a semiconducting material such as a small amount of Bi ₂ O ₃ , Sb ₂ O _3, and the aforementioned sheets are 2 to 5 In particular, it is preferable to stack three, and form internal electrodes on at least two sheets. The internal electrode of the varistor described above is conveniently formed by printing a slurry containing an oxide of a conductive metal such as Pt and Ag-Pt by a silk screen printing method. In addition, the support layer for supporting the varistor layer on both sides is formed by stacking a plurality of ceramic cities having almost no dielectric. The ceramic sheets should be laminated on both sides of the varistor before being sintered and sintered together with the varistor layer.

In the present invention, the inner electrode formed on the varistor should be exposed to both sides of the outer electrode is attached so that at least two inner electrodes are directly connected to the outer electrode, some of the inner electrode may not be directly connected have.

The varistor according to the present invention has excellent varistor characteristics showing high-speed operating characteristics, and can effectively protect electronic components from internal or external surges.

1 is a perspective view of a chip varistor according to the present invention.

2 is a longitudinal cross-sectional view of the chip varistor according to the present invention.

3 (a), (b), (c) and (d) are exploded perspective views showing the electrode arrangement of the chip varistor according to the present invention.

* Explanation of symbols for main parts of the drawings

1: varistor 2: ceramic support layer

3,4 external electrodes 9,10,11,12 varistor sheets

8,13: Ceramic Sheet

5,6,7,14,15,16,17,18,19,20,21,22,23,24,25 Internal electrodes

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a perspective view of the varistor according to the present invention, and FIG. 2 is a longitudinal sectional view of the varistor shown in FIG. The chip varistor is in the form of a chip having ceramic support layers 2 and 2 supporting and protecting the varistor 1 on both sides of the thin laminated varistor 1, and the internal electrode for determining the capacitance capacity in the varistor 1 5, 6, and 7 are alternately exposed to the outside, and are directly connected to the external electrodes 3 and 4 formed at both ends of the varistor.

In the chip varistor of the present invention, a varistor material powder such as Bi ₂ O ₃ , Sb ₂ O ₃ , which is a small amount of semiconductor oxide, is mixed with ZnO powder as a main material, and an organic binder is mixed. After the internal electrodes 5, 6, and 7 are applied to the sheets, the sheets 9, 10, 11, and 12 are laminated to form a thin varistor 1, and the dielectric constant is low on both sides of the varistor 1. The support layers 2 made of ceramic sheets 8 and 13 are laminated and sintered to produce the varistor 1 and the support layers 2 on both sides thereof integrally.

The internal electrodes 5, 6, and 7 of the varistor 1 are made of a conductive metal oxide such as Pt, Ag-Pt, and kneaded to form a thin varistor sheet 10, 11, 12 prior to lamination and sintering. It is formed by coating in a phosphorous method.

The ceramic support layer 2 is formed by laminating ceramic sheets 8 and 13 with extremely low dielectric constant on both sides of the varistor 1 before sintering.

The external electrodes 3 and 4 are formed by coating metal powders such as Ag and Ag-Pt in a kneading state and coating them on both sides of the device in the form of a film and firing them.

According to the present invention, since the thickness of the varistor is thin, for example, about 0.9 mm, the capacitance capacity is low, and a ceramic protective layer having a very low dielectric constant is formed on both sides of the thin varistor 1 to sinter the varistor. The varistors are not deformed or broken and there is no risk of breaking the varistors even when installed in the electronic device.

Example 1

95 parts of ZnO powder and 5 parts of 1: 1 mixture with Sb ₂ O ₃ and Bi ₂ O ₃ are mixed with a polyvinyl alcohol solution to make a dough, milled homogeneously using a ball mill and applied on film for uniform thickness Sheets 9, 10, 11, 12 are formed and cut to a constant size.

PtO slurry was applied to the surfaces of the sheets 10, 11, and 12 using a silk screen printing method so that one end of the internal electrodes 14, 15, and 16 were exposed to the outside, and the varistor sheets 9, 10, 11, and 12 were applied. As shown in FIG. 3 (a), the exposed ends of the electrodes are laminated alternately, and then the ceramic sheets 8 and 13 having a very low dielectric constant are laminated and sintered on the surfaces of the outer varistor sheets 9 and 12. The varistor 1 and the support layer 2 are formed to be integrated. Subsequently, a known platinum electrode material is coated on the end surface of which the ends of the inner electrodes are exposed to form a film to form the outer electrodes 3 and 4 and then baked to form a chip varistor.

Example 2

The chip varistor is formed in the same manner as in the first embodiment, and the internal electrodes 17, 18, and 19 constituting the varistor 1 are formed as shown in FIG. 3 (b). In this case, the internal electrodes 17, 17 ', 19, 19' of the sheets 10, 12 are exposed to the outside from both sides of the sheets, and the internal electrodes 18 of the sheet 11 are external electrodes ( 2,3) is not connected.

Example 3

The chip varistor is formed in the same manner as in the first embodiment, and the internal electrodes 17, 18, and 19 constituting the varistor 1 are formed as shown in FIG. 3 (c). In this case, the inner electrodes of the sheets 10, 11 and 12 are composed of electrodes 20, 21 and 22 connected to the external electrodes and electrodes 20 ', 21' and 22 'not connected to the external electrodes. .

Example 4

A chip varistor is formed in the same manner as in the first embodiment, and the internal electrodes 17, 18, and 19 constituting the varistor 1 are formed as shown in FIG. In this case, the internal electrodes 23, 24, and 25 are arranged in the same shape as the internal electrode of Embodiment 1, but have a small surface area.

The internal electrodes applied to the varistor sheets of Examples 1, 2, 3 and 4 are connected to the external terminals 3 and 4 after simultaneous sintering of the varistor sheets. As such, the internal electrodes can be variously changed according to the location of use, capacity, and characteristics of the product. Therefore, it is possible to selectively use a chip varistor having a suitable internal electrode in accordance with the characteristics of the product.

As described above, in the chip varistor of the present invention, since the varistor 1 is supported by the ceramic support layers 2 and 2, not only the varistor is stabilized, but also the amount of the varistor 1 in contact with the external electrode due to the thin thickness of the varistor 1. Since the surface area of the side is small, the capacitance can be lowered to 10pF or less, and since the external electrodes 3 and 4 are formed in the same shape as the cap terminals, the mounting area on the board is small and the high-speed signal lines can be connected to each other. Miniaturization can be achieved.

Claims (2)

In the chip varistor, a varistor formed by stacking a plurality of varistor sheets ( ₉ , ₁₀ , ₁₁ , ₁₂₎ containing a semiconducting oxide Bi ₂ O ₃ , Sb ₂ O ₃ powder in the ZnO powder and an internal electrode disposed therein Before sintering (1), the ceramic support layer (2) formed by laminating ceramic sheets (8, 13) with extremely low dielectric constant, unlike the sheet inside the varistor layer, which exhibits electrical characteristics on both sides of the varistor (1). Comprising a chip varistor molded body, the internal electrodes 17, 17 ', (19, 19') of the varistor sheet (9, 10, 11, 12) is connected to the external electrode (3, 4) directly from both sides And the inner electrode 18 of the sheet 11 is configured not to be directly exposed to the outer electrode. In the chip varistor, a varistor formed by stacking a plurality of varistor sheets ( ₉ , ₁₀ , ₁₁ , ₁₂₎ containing a semiconducting oxide Bi ₂ O ₃ , Sb ₂ O ₃ powder in the ZnO powder and an internal electrode disposed therein Before sintering (1), the ceramic support layer (2) formed by laminating ceramic sheets (8, 13) with extremely low dielectric constant, unlike the sheet inside the varistor layer, which exhibits electrical characteristics on both sides of the varistor (1). An internal electrode 20, 21 ', 22 which is configured to form a chip varistor molded body, which is connected to an external electrode of the varistor sheets 9, 10, 11, and 12, and which is not directly connected to an external electrode, respectively. And 21,22 ', wherein the internal electrodes 20, 21', 22 of the varistor sheet are alternately arranged to be connected to external electrodes on both sides of the varistor sheet.

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