KR100246345B1 - Voltage comparator - Google Patents

Abstract

The present invention relates to a voltage comparator having a feedback circuit. In the conventional voltage comparator, since the voltage gain of the amplifier stage is small, a large number of amplifier stages are required in order to obtain a desired voltage gain, resulting in a high manufacturing cost. In consideration of such a problem, the present invention provides two first switches for passing an input voltage and a reference voltage, respectively, according to a first clock signal, and first and second capacitors each charged with an output of the two first switches. First and second inverters for inverting and amplifying the outputs of the first and second capacitors, and two for applying a reference voltage to the first capacitor and an input voltage to the second capacitor according to the second clock signal. Outputs of the second switch and the first inverter to the input of the second inverter, the output of the second inverter to the input of the first inverter and two second switches, respectively at both ends of the first, second inverter Two third switches connected in parallel and turned on / off according to a third clock signal, and a latch unit for receiving and outputting the output of the first inverter and the output of the second inverter to obtain a desired voltage gain with one amplification stage. Can be manufactured It is effective in reducing the city cost.

Description

Voltage Comparators {VOLTAGE COMPARATOR}

The present invention relates to a voltage comparator, and more particularly, to a voltage comparator of an analog-to-digital converter that can obtain a desired gain with only one amplifier stage by using a feedback means.

Referring to the conventional voltage comparator with reference to the accompanying drawings in detail as follows.

FIG. 1 is a circuit diagram of a conventional voltage comparator. As shown in FIG. 1, a voltage detection stage 1 that receives a reference voltage Vref and an input voltage Vin and detects a voltage difference thereof, and a voltage detection stage 1 thereof. An amplification stage (2) for receiving and amplifying the output of the input, an inverter (INV3) for inverting and amplifying the output of the amplifying stage (2) to recover a phase, and a clock signal (for receiving the output of the inverter (INV3). It consists of a latch part 3 which outputs the output voltage Vo in synchronization with CLK. The voltage detection terminal 1 includes switches S1 and S2 for passing the input voltage Vin and the reference voltage Vref under the control of the clock signals CLK1 and CLK2, and the switches S1. Capacitor C1 receiving the input voltage Vin and the reference voltage Vref alternately by S2 and S2, an inverter INV1 for inverting and amplifying the output of the capacitor C1, and the inverter INV1. And a capacitor C2 connected in parallel to both ends thereof and turned on / off by a clock signal CLK3, and a capacitor C2 receiving an output of the inverter INV1. An inverter INV2 for inverting and amplifying the output of C2, and a switch S4 connected in parallel to both ends of the inverter INV2 and turned on / off by the clock signal CLK3. Hereinafter, the operation of the conventional voltage comparator configured as described above will be described in detail with reference to FIGS.

FIG. 2 is a waveform diagram of a clock signal input to the gate of each switch. As shown in FIG. 2, the clock signal CLK1 is a waveform having a longer rising state than the clock signal CLK3, but having a longer high state and a clock. The signal CLK2 is a waveform having a rising edge and a falling edge in the low state of the clock signal CLK1. As such, when the clock signals CLK1 and CLK3 are applied in a high state, the switches S1, S3, and S4 are conducted so that the threshold voltages Vit1 of the input voltage Vin, the inverters INV1, and INV2 are applied. Voltages (Va), (Vb), (Vc), (Vd) and (Ve) applied to the nodes (A), (B), (C), (D), and (E) according to Vit2). The voltages Vc1 and Vc2 charged to the capacitors C1 and C2 are as follows.

Va: Vin Vb: Vit1

Vc: Vit1 Vd: Vit2

Ve: Vit2

When the clock signal CLK2 becomes high after the clock signals CLK1 and CLK3 go low, the switches S1, S3, and S4 are interrupted, and the switch S2 is turned on so that the input voltage Vin ) And the reference voltage (Vref) and the threshold voltage (Vit1), (Vit2) and voltage gain (A1), (A2) of the inverter (INV1), (INV2) and the capacitor (C1), (C2) Voltages Va, Vb, and Vc applied to the nodes A, B, C, D, and E according to the voltages Vc1 and Vc2. And (Ve) are as follows.

Va: Vref

Vb:

Vc:

Vd:

Ve:

Therefore, the voltage gains A1 and A2 of the inverters INV1 and INV2 are multiplied by the difference between the input voltage Vin and the reference voltage Vref, such as the voltage Ve applied to the node E. The inverter INV3 is inputted to restore the original phase, and the latch unit 3 receives the output of the inverter INV3 to adjust the output voltage Vo according to the synchronization of the clock signal CLK. Output

However, the voltage comparator as described above has a problem in that a large number of amplification stages are required in actual use, which is expensive in manufacturing because the gain of the amplifier stage is small.

The present invention was devised to solve the above problems, and provides a voltage comparator that allows a circuit configuration of an amplifier stage to include a feedback circuit so that a conventional clock signal is unchanged and a desired gain can be obtained with only one amplifier stage. Its purpose is to.

1 is a circuit diagram of a conventional voltage comparator.

2 is a waveform diagram of a clock signal input to a gate of each switch.

3 is a circuit diagram of a voltage comparator according to the present invention.

*** Description of the symbols for the main parts of the drawings ***

10: voltage detection stage 20: amplification stage

30: Latch part S11 to S14, S21 to S24: Switch

C1, C2: Capacitor INV1 to INV2: Inverter

As described above, the first and second switches turn on / off according to the clock signal CLK1 to apply and cut off the input voltage and the reference voltage, respectively, and the input voltage or the reference voltage from the first and second switches. First and second capacitors each receiving and charging, first and second inverters receiving and amplifying the outputs of the first and second capacitors, respectively, and connected to both ends of the first and second inverters, respectively. Third and fourth switches that are turned on / off according to the clock signal CLK3, and fifth and sixth switches that turn on / off according to the clock signal CLK2 to cross and block an input voltage or a reference voltage. The output of the first inverter is the input of the second inverter, the output of the second inverter is the seventh and eighth switches to return to the input of the first inverter, and the output of the first and second inverter to receive the clock signal (CLK) This is achieved by configuring a latch unit for outputting an output voltage according to the synchronization of A voltage comparator according to the present invention with reference to Figure 3 and Figure 2 will be described in detail.

FIG. 3 is a circuit diagram of a voltage comparator according to the present invention. As shown therein, a voltage detector 10 for receiving a reference voltage Vref and an input voltage Vin and detecting a voltage difference therebetween, and the voltage detector An amplifying stage 20 for receiving and amplifying the output of the output 10 and a latch unit 30 for receiving the output of the amplifying stage 20 and outputting an output voltage Vo according to the synchronization of the clock signal CLK. do. The voltage detection terminal 10 passes the input voltage Vin to the first capacitor C1 and the reference voltage Vref to the second capacitor C2 under the control of the clock signal CLK1. Capacitors C1 and C2 that receive and charge the input voltage Vin and the reference voltage Vref through S12 and the switches S11 and S12, respectively, and the clock signal CLK2. Control S13, S14, and S14 are applied to the input voltage Vin to the capacitor C2 and the reference voltage Vref to the capacitor C1. It is connected to the inverters INV1 and INV2 that receive the outputs of C1) and C2 and inverted and amplified, respectively, and both ends of the inverters INV1 and INV2, and are controlled by the clock signal CLK3. Under the control of the switches S21 and S22 and the clock signal CLK2, the output of the inverter INV1 is the input of the inverter INV2, and the output of the inverter INV2 is the inverter INV1. Switch (S23), (S24) returning to input of It is configured. Hereinafter, the operation of the voltage comparator according to the present invention configured as described above will be described. At this time, the waveform of the clock signal input to the gate of each switch is as shown in FIG.

When the clock signals CLK1 and CLK3 are applied in the high state, the switches S11, S12, S21, and S22 are turned on, so that the thresholds of the input voltage Vin and the inverter INV1 and INV2 are applied. Voltages Va, Vb, and Vc applied to the nodes A, B, C, D, E, and F according to the voltages Vit1 and Vit2, respectively. (Vd), (Ve), (Vf); Voltages Vc1 and Vc2 charged in the capacitors C1 and C2 are as follows.

When the clock signals CLK2 go high after the clock signals CLK1 and CLK3 go low, the switches S11, S12, S21, and S22 are cut off, and the switches S13 and S14. ), (S23), (S24) are conducted so that the input voltage Vin and the reference voltage Vref, and the threshold voltages Vit1, Vit2 and voltage gain A1 of the inverters INV1 and INV2, (A2) and the nodes (A), (B), (C), (D), (E), and (2) according to the voltages Vc1 and Vc2 charged to the capacitors C1 and C2, respectively. The voltages Va, Vb, Vc, Vd, Ve and Vf applied to F) are as follows.

Va:

Vb:

Vc:

Vd:

Ve:

Vf:

The voltage Vf applied to the node F is returned to the node B by the switches S23 and S24 and amplified by the inverter INV1. Therefore, the final voltage applied to the feedback and amplified node C is multiplied by the difference between the input voltage Vin and the reference voltage Vref by the voltage gains A1 and A2 of the inverters INV1 and INV2. The latch unit 30 receives the outputs of the inverters INV1 and INV2 on one side and the other side, and outputs an output voltage Vo in synchronization with the clock signal CLK.

The voltage comparator according to the present invention, which is constructed and operated as described above, can obtain a gain obtained through a plurality of amplifier stages with only one amplifier stage under the same clock signal condition as the conventional circuit. This simplifies configuration and reduces design costs.

Claims (1)

First and second switches passing the input voltage Vin and the reference voltage Vref through the control of the clock signal CLK1, and the input voltage Vin and the reference voltage through the first and second switches. The first and second capacitors respectively receiving and charging Vref, and the input voltage Vin crosses the second capacitor and the reference voltage Vref is applied to the first capacitor under the control of the clock signal CLK2. A voltage detecting terminal consisting of fifth and sixth switches; First and second inverters that receive the outputs of the first and second capacitors, respectively, and inverted and amplified, are connected in parallel to both ends of the first and second inverters, respectively, and are controlled by the control of the clock signal CLK3. By controlling the third and fourth switches and the clock signal CLK2 which are turned off, the output of the first inverter is input to the second inverter and the output of the second inverter is input to the input of the first inverter. An amplifier stage composed of eight switches; And a latch unit configured to receive outputs of the amplifier stages and output an output voltage according to synchronization of a clock signal CLK.

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