KR100244459B1 - Sense amplifier - Google Patents

Abstract

The present invention relates to a sense amplifier circuit. In the conventional circuit, when amplifying and outputting a fine data signal, the output of the once amplified data signal does not change. Therefore, a fatal error occurs when noise is mixed in the first applied data signal. There was a problem.

The present invention provides a first and second drive means for driving by the enable signal to solve the conventional problems; First amplifying means connected to the first driving means, respectively, for amplifying and outputting data signals DATA and DATAB; First and second inverting means for inverting an output signal of the first amplifying means; Invented a sense amplifier circuit connected to the second driving means and composed of a second amplifying means for amplifying and outputting an output signal of the first and second inverting means, and thus a mirror amplifier for primary amplifying the data signal. By placing an inverting part between the latch amplifying parts for the second amplification so that the output signal of the latch amplifying part that is finally output corresponds to the polarity of the initial data signal, accurate and stable operation can be performed even if noise is mixed in the initial data signal.

Description

Sense amplifier circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier circuit. In particular, when amplifying and outputting a data signal, if the polarity of the initial data signal is changed by noise, the output signal is also changed so that the sense amplifier circuit operates stably against signal noise. It is about.

FIG. 1 is a conventional sense amplifier circuit diagram, as shown therein, an MOS transistor MN1 for enabling a sense amplifier by an enable signal SAC; NMOS transistors MN2 and MN3 connected to drains of the NMOS transistors MN1 and amplifying data signals DATA and DATAB, respectively; An enmos transistor MN4, a PMOS transistor MP1, an NMOS transistor MN5, and a PMOS transistor MP2 which latch and amplify the output signals of the NMOS transistors MN2 and MN3; The PMOS transistors MP3 and MP4 are configured to equalize the output terminals S1 and S2 of the NMOS transistors MN4 and MN5 according to the equalization signal SAEQ.

The operation of the conventional circuit configured as described above is as follows.

First, when the enable signal SAC is changed from the low state to the high state, the NMOS transistor MN1 is turned on, and the sense amplifier is enabled.

At this time, the PMOS transistors MP3 and MP4 are turned on by the equalization signal SAEQ so that the outputs across the sense amplifiers are equalized to a predetermined level, that is, precharged.

This ensures stable operating characteristics of the sense amplifier while eliminating unnecessary timing margins when transmitting signals to the data bus.

In such a state, when the data signals DATA and DATAB are applied through the data lines, the NMOS transistor MN2 and the NMOS transistor MN3 are turned on / off according to the voltage difference across the data lines.

NMOS transistors MN4 and MN5 and PMOS transistors MP1 and MP2 positively feed back the potential difference to latch the outputs of both ends S1 and S2 to Vcc and Vss, respectively.

As described above, in the static mode in which the output is latched, there is no DC current path. Therefore, the sense amplifier consumes current only during the switching time of the latch portion.

As described above, in the conventional circuit, when amplifying and outputting a fine data signal, the output of the once-amplified data signal does not change. Therefore, a fatal error occurs when noise is mixed in the first applied data signal.

An object of the present invention is to solve the conventional problems, and to first amplify the data signal is first applied to the amplifier and the output signal of the amplifier latch and amplify the output of the final latch portion and between the amplifier and the latch unit The present invention provides a sense amplifier circuit that enables stable operation with respect to signal noise by allowing a final output signal to correspond to a change of a data signal applied at first.

1 is a conventional sense amplifier circuit diagram.

Figure 2 is an embodiment of the present invention.

3 is a waveform diagram of an enable signal SEN.

4 is a waveform diagram of an equalization signal SEQ.

5 is an output waveform diagram of a mirror amplifier.

6 is an output waveform diagram of first and second inverting units.

7 is an output waveform diagram of a latch amplifier.

***** Description of the symbols for the main parts of the drawings *****

100: mirror amplifier 110,150: first registration unit

120,130: first and second inverting part 140: latch amplification part

The sense amplifier circuit for achieving the object of the present invention comprises: first and second driving means for driving by the enable signal; First amplifying means connected to the first driving means, respectively, for amplifying and outputting data signals DATA and DATAB; First and second inverting means for inverting an output signal of the first amplifying means; And a second amplifying means connected to the second driving means to amplify and output the output signals of the first and second inverting means.

Hereinafter, the operation and effects of the present invention will be described with reference to one embodiment.

FIG. 2 is an exemplary embodiment of the present invention, and as shown therein, the NMOS transistors MN1 and MN4 which are driven by the enable signal SEN to enable the sense amplifiers; It is composed of NMOS transistor (MN2), PMOS transistor (MP1), NMOS transistor (MN3) and PMOS transistor (MP2) and connected to the NMOS transistor (MN1) to amplify the data signals (DATA, DATAB) A mirror amplifier 100 for outputting; A first equalizer 110 formed of an NMOS transistor MN9 and a PMOS transistor MP7 for precharging both ends of the mirror amplifier 100 according to the equalization signal SEQ; A first inverting unit 120 including an NMOS transistor MN5 and a PMOS transistor MP5 to invert and output an output signal of the mirror amplifier 100; A second inverting unit 130 including an NMOS transistor MN6 and a PMOS transistor MP6 to invert and output an output signal of the mirror amplifier 100; It is composed of an NMOS transistor (MN5), a PMOS transistor (MP3), an NMOS transistor (MN6) and a PMOS transistor (MP4) and connected to the NMOS transistor (MN4), the first and second inverting parts (120, 130) A latch amplifier 140 for latching, amplifying and outputting an output signal; A second equalizer 150 is formed of the NMOS transistor MN10 and the PMOS transistor MP8 to precharge both ends of the latch amplifier 140 according to the equalization signal SEQ.

Referring to the operation of the embodiment of the present invention configured as described above are as follows.

First, as shown in FIG. 3, when the enable signal SEN changes from 'low' to 'high', the NMOS transistor MN1 and the NMOS transistor MN4 are turned on, and the sense amplifier is enabled.

As shown in FIG. 4, the NMOS transistor MN9, the PMOS transistor MP7, the NMOS transistor MN10, and the PMOS transistor MP8 are turned on while the equalization signal SEQ is 'high'. The contacts S1, S2 and S5, S6 at both ends of the sense amplifier are registered at the same level of potential.

At this time, when the minute data signals DATA and DATAB stored in the cell are applied to the gates of the NMOS transistors MN2 and MN3 through the data lines, the NMOS transistors MN2 and MN3 are turned on so that the corresponding voltage is turned on. It is first amplified by the NMOS transistor MN6 and the PMOS transistor MP6, and the NMOS transistor MN5 and the PMOS transistor MP5, and appears at the contacts S1 and S2.

The potentials of the contacts S1 and S2 are applied to the gates of the MOS transistor MN5 and the PMOS transistor MP5 and the gates of the NMOS transistor MN6 and the PMOS transistor MP6, and the voltages of the contacts S1 and S2 are Inverted and amplified by the MOS transistors MN5, MN6, MP5, and MP6 as shown in FIG. 6, they appear at the contacts S3 and S4.

The voltages shown at the contacts S3 and S4 are latched and amplified by the MOS transistors MN7, MN8, MP3, and MP4 as shown in FIG. 7, and finally output through the output terminal S / AOUTPUT.

As described in detail above, an inverting part is provided between the mirror amplifying part which first amplifies the data signal and the latch amplifying part which amplifies the second signal so that the output signal of the latch amplifying part which is finally output corresponds to the polarity of the initial data signal. Even if the noise is mixed, there is an effect that it can operate correctly and stably.

Claims (3)

First and second driving means driven by an enable signal; First amplifying means connected to the first driving means, respectively, for amplifying and outputting data signals DATA and DATAB; First and second inverting means for inverting an output signal of the first amplifying means; And a second amplifying means connected to the second driving means and configured to amplify and output the output signals of the first and second inverting means. The sense amplifier circuit of claim 1, wherein the first amplifying means is a mirror amplifying means. 2. A sense amplifier circuit as set forth in claim 1, wherein said second amplifying means is a latching amplifying means.

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