KR0172783B1 - Data output buffer - Google Patents

Abstract

The present invention relates to a data output buffer of a semiconductor memory device in which the output terminal of the data output buffer is always precharged to the inversion level {(1/2) Vcc}. When reading data using this data output buffer. It eliminates the pull-swing behavior that occurs at the pull-up and pull-down driver stages of the data output buffer, reducing the operating speed and power line noise.

Description

Data output buffer

1 is a circuit diagram of a conventional data output buffer.

2 is a detailed circuit diagram of a data output buffer according to the first embodiment of the present invention.

FIG. 3 is a detailed circuit diagram of the reference voltage generator circuit shown in FIG.

4 is a circuit diagram of a data output buffer according to a second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: data output buffer section 11: reference voltage generation circuit section

12: potential comparison circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer of a semiconductor device, and more particularly, to full-swing in pull-up and pull-down driver stages during data output by precharging the output stage to a specific potential {(1/2) Vcc} The present invention relates to a data output buffer that suppresses noise due to full swing and improves operation speed.

FIG. 1 is a circuit diagram showing a conventional data output buffer. The pull-up transistor MP1 is connected between a power supply potential Vcc and an output terminal N2 and has a gate connected to an input terminal N1 for inputting data. And a pull-down transistor MN1 connected between the output terminal N2 and the ground potential Vss and having a gate connected to the input terminal N1.

When the 'high' data is input to the input terminal N1, the pull-up transistor MP1 is turned off, and the pull-down transistor MN1 is turned on to 'low' to the output terminal N2. 'Print data. When the 'low' data is input, the pull-up transistor MP1 is turned on and the pull-down transistor MN1 is turned off to output 'high' data to the output terminal N2. .

In this operation, the data output buffer outputs data opposite to the input data signal, wherein the pull-up / pull-down transistors MP1 and MN1 for supplying a power potential or a ground potential to the output terminal N2, respectively. ) Is a full-swing operation as the input data signal changes. That is, a full swing with a large voltage swing width must be made from the power potential Vcc to the ground potential Vss or from the ground potential Vss to the power potential Vcc. Will be slow.

Accordingly, it is an object of the present invention to provide a data output buffer in which the full-swing operation does not occur when data is read by precharging the potential of the output terminal to the inverted potential {(1/2) Vcc} at all times.

In order to achieve the above object, a data output buffer according to a first embodiment of the present invention includes data including pull-up means for transmitting a high potential to an output terminal and pull-down means for outputting a low potential to an output terminal. An output buffer comprising: reference voltage generating means for generating a constant reference voltage, potential comparing means for comparing and amplifying a signal of said reference voltage and said output terminal, and a first and a second control signal as a control signal of a first logic is input; The operation of the pull-up means and the pull-down means is controlled by data signals from two input lines, and as the control signal of the second logic is inputted, the signals from the reference voltage generating means and the potential comparing means And switching means for controlling the operation of the pull-up means and the pull-down means, respectively, to maintain the potential of the output terminal at an inverted state at all times.

A data output buffer according to a second embodiment of the present invention is a data output buffer including pull-up means for transmitting a high potential to an output terminal and pull-down means for outputting a low potential to an output terminal. A reference voltage generating means for generating a voltage, a potential comparing means for comparing and amplifying an output signal of the reference voltage generating means and an output signal of the output terminal, and an output from the reference voltage generating means and a potential comparing means; And switching means for keeping the potential of the output terminal always in an inverted state by control of a signal and a control signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a detailed circuit diagram of a data output buffer according to the first embodiment of the present invention, which includes a data output buffer unit 10 composed of pull-up and pull-down transistors MP1 and MN1, and a constant reference voltage Vref. A reference voltage generator circuit portion 11 for generating a voltage, a potential comparison circuit portion 12 for comparing and amplifying the output signal of the reference voltage generator circuit portion 11 and the output signal of the data output buffer portion 10, and outputting the same; First transfer gates MN5 and MP4 for transferring an input data signal to the gate of the pull-up transistor MP1 by a control signal preset and an inverted control signal / preset, and a control signal preset and Second transfer gates MN6 and MP5 for transmitting an input data signal to the gate of the pull-down transistor MN1 by an inverted control signal / preset, a control signal preset and an inverted control signal / preset) outputs the output signal of the potential comparison circuit section 12 to the pull-up transistor. The output signal of the reference voltage generator circuit part 11 by the third transfer gates MN7 and MP6 and the control signal preset and the inverted control signal / preset to be transferred to the gate of the signal generator MP1. And fourth input gates MN8 and MP7 passing to the gate of the down transistor MN1, and input terminals N8 for inputting preset signals for controlling the operations of the first to fourth transfer gates, respectively. do.

Before looking at the operation by the configuration, the configuration and operation of the reference voltage generator circuit 11 will be described first.

The circuits of (a) and (b) of FIG. 3 constitute two types of reference voltage generating circuit sections 11. First, the reference voltage generator 11 of FIG. 3A is connected between a power supply voltage Vcc and an output terminal N14, and a PMOS transistor MP8 and an output terminal N14 having a gate connected to the output terminal N14. And an NMOS transistor MN9 connected between the ground voltage Vss and a gate connected to the output terminal N14, divided by the PMOS transistor MP8 and the NMOS transistor MN9 (1/2). The Vcc potential is output to the output terminal N14.

The reference voltage generating circuit part 11 of FIG. 3b is connected between the power supply voltage Vcc and the node N15, the resistor R1 connected between the node N15 and the node N16, and the gate thereof is connected to the gate ( NMOS transistor MN10 connected to N15, a PMOS transistor MP9 connected between node N16 and node N17 and a gate connected to node N17, node N17 and ground voltage NMOS transistor MN11 connected between a resistor R2 connected between Vss, a power supply voltage Vcc and an output terminal N18, and a gate connected to the node N15, and the output terminal N18 and A PMOS transistor MP10 connected between the ground voltage Vss and a gate connected to the node N17 is configured.

The NMOS transistors MN10 and MN11 are turned on by a power potential supplied to the node N15 through the resistor R1 to supply power potentials to the node N16 and the output terminal N18. However, the PMOS transistor MP9 of the diode structure is turned on to generate the power potential supplied to the node N17 to the ground potential through the resistor R2, so that the node N17 is connected to the gate. The transistor MP10 is turned on. Accordingly, the potential of the output terminal N18 outputs the potential (1/2) Vcc divided by the turned-on NMOS transistor MN11 and the PMOS transistor MP10 to the output terminal N18.

In FIG. 2, the potential comparison circuit unit 12 is connected between the power supply voltage Vcc and the nodes N5 and N6, respectively, and the PMOS transistors MP2 and MP3 having the current mirror structure connected to the node N6 in common. NMOS transistor MN2 connected between the output node N5 and the node N7, the gate of which is connected to the output terminal N3 of the reference voltage generator circuit 11, and the node N6 and the node. (N7) and a gate is connected between the NMOS transistor (MN3) and the node (N7) and ground voltage (Vss) connected to the output terminal (N4) of the data output buffer unit 10, the gate is the It is composed of an NMOS transistor MN4 connected to the node N8. The potential comparison circuit unit 12 is a differential amplifier for comparing and amplifying the signal of the output terminal N3 of the reference voltage generating circuit unit 11 and the signal of the output terminal N4 of the data output buffer unit 10. Consists of.

Here, the first transfer gates MN5 and MP4 are turned on when the control signal is 'low' so that the data signal input through the input line N10 is input to the gate of the pull-up transistor MP1. The second transfer gates MN6 and MP5 are turned on when the control signal preset is 'low' to input data signals input through the input line N11 to gates of the pull-down transistor MN1. The third transfer gates MN7 and MP6 are turned on when a control signal is 'high' to output an output terminal N5 signal of the potential comparison circuit unit 12 to the pull-up transistor. The fourth transfer gates MN8 and MP7 are turned on when the control signal is 'high' to transmit an output terminal N3 signal of the reference voltage generator circuit 11 to the gate of MP1. Transfer to the gate of the pull-down transistor (MN1).

On the other hand, when the control signal preset becomes 'high' and the third and fourth transfer gates MN7, MP6 / MN8, and MP7 are turned on, the voltage of the node N4 is set to the node N3. If the voltage is greater than the voltage, the current flowing through the NMOS transistor MN3 is greater than the current flowing through the NMOS transistor MN2, so that the potential of the node N6 is lowered, while the output terminal output from the potential comparison circuit section 12 is reduced. The potential of (N5) becomes high. Therefore, the current flowing toward the output terminal N4 through the pull-up transistor MP1 supplied with the gate of the output terminal N5 is reduced, and the reference applied to the gate from the reference voltage generating circuit section 11. The voltage of the output terminal N4 is lowered through the pull-down transistor MN1 turned on by the potential (1/2) Vcc (at this time, the potential of the output terminal N4 is approximately (1/2). Vcc is about).

When the voltage of the node N4 is smaller than the voltage of the node N3, the current flowing through the NMOS transistor MN3 is smaller than the current flowing through the NMOS transistor MN2 so that the potential of the node N6 is increased. On the other hand, the potential of the output terminal N5 output from the potential comparison circuit section 12 is lowered. Accordingly, the current flowing toward the output terminal N4 through the pull-up transistor MP1 supplied with the gate of the output terminal N5 is increased, and the reference potential applied to the gate from the reference voltage generating circuit section 11 is increased. The voltage of the output terminal N4 is reduced through the pull-down transistor MN1 turned on by ((1/2) Vcc). Therefore, the potential of the output terminal N4 of the data output buffer unit 10 is output such that the divided voltage is turned to (1/2) Vcc potential by the turned-up and pull-down transistors MP1 and MN1. do. As a result, the potential of the output terminal N4 of the data output buffer unit 10 can be adjusted by the output signal N3 from the reference voltage generating circuit unit 11.

Therefore, in the present invention, if the previous data output from the output terminal N4 of the data output buffer section 10 was 'high (ccc)' data, the pull-down transistor MN1 causes the (1/2) The charge is discharged to the Vcc potential, and if the previous data is 'low (Vss)' data, the charge is charged to the (1/2) Vcc potential by the pull-up transistor MP1.

When the control signal is 'low', the third and fourth transfer gates MN7, MP6 / MN8 and MP7 are turned off, and the first and second transfer gates MN5, MP4 / MN6, The MP5 is turned on to apply data signals input to the nodes N10 and N11 to the gates of the pull-up and pull-down transistors MP1 and MN1 of the data output buffer unit 10, respectively.

4 is a circuit configuration diagram of a data output buffer according to a second embodiment of the present invention. The pull-up transistor MP1 and the output terminal N19 connected between a power supply potential Vcc and an output terminal N19 are shown in FIG. And a data output buffer unit 10 including a pull-down transistor MN1 connected between the ground voltage Vss, a reference voltage generating circuit unit 11 for generating a constant reference voltage Vref, and generating the reference voltage. By the potential comparison circuit section 12 for comparing, amplifying and outputting the output signal of the circuit section 11 and the output signal of the data output buffer section 10, and the control signal (/ preset) inverted by the inverter G2. The first terminal switching device MP11 (PMOS transistor) for supplying the power potential Vcc to the node N25 and the charge transferred to the node N25 by the output signal of the potential comparison circuit unit 12 are outputted to the output terminal. A second switching element (MP12; PMOS transistor) transferred to N19, and the reference voltage generation circuit The third switching element MN12 (NMOS transistor) for supplying charges from the output node N19 to the node N26 by the output signal of the unit 11 and the node N26 by the control signal preset. And a fourth switching element MN13 (NMOS transistor) for discharging the charge from the battery to ground potential.

The reference voltage generator 11 has the same structure and operation as the reference voltage generators a and b shown in FIG. 3, and the potential comparison circuit 12 also has the potential comparison circuit shown in FIG. And its configuration and operation are the same.

First, when the voltage of the output terminal N19 of the data output buffer 10 is greater than the reference voltage ((1/2) Vcc) from the reference voltage generating circuit section 11, the output voltage of the potential comparing circuit section 12 Is higher. That is, the potential of the output node N22 of the potential comparison circuit unit 12 becomes 'high' to turn off the second switching element MP12. In this case, when a signal controlling the operation of the first and fourth switching elements MP11 and MN13 is 'high', the first switching element MP11 is turned on but the second switching element is turned on. MP12 is turned off to stop the supply of charge to the output terminal N19. However, the potential of the output terminal N19 that maintains the 'high' potential by the capacitor C1 connected to the output terminal N19 is turned on by the reference voltage generating circuit section 11 and the control signal (preset). The third and fourth switching elements MN12 and MN13 are lowered to the (1/2) Vcc potential.

If the voltage of the output terminal N19 of the data output buffer 10 is smaller than the reference voltage ((1/2) Vcc) from the reference voltage generating circuit section 11, the output of the potential comparing circuit section 12 The voltage is lowered. That is, the potential of the output node N22 of the potential comparison circuit unit 12 becomes 'low' to turn on the second switching element MP12. In this case, when the signal controlling the operation of the first and fourth switching elements MP11 and MN13 is 'high', the first switching element MP11 may also be connected to the second switching element MP12. Likewise, it is turned on to supply the power potential Vcc to the output terminal N19. However, the potential of the output terminal N19 is (1/2) Vcc potential by the third and fourth switching elements MN12 and MN13 turned on by the reference voltage generator 11 and the control signal preset. Will be lowered.

As described above, when the data output buffer of the present invention is implemented in the semiconductor memory device, since the output terminal of the data output buffer is always precharged to the inversion level {(1/2) Vcc}, data can be read. If the data is not full-swing, the operation speed can be improved, and the power line noise can be reduced.

Claims (10)

A data output buffer comprising a pull-up means for transmitting a high potential to an output terminal and a pull-down means for outputting a low potential to an output terminal, the data output buffer comprising: reference voltage generating means for generating a constant reference voltage; Operation of the pull-up means and the pull-down means by means of a potential comparison means for comparing and amplifying the signals of the output terminal and data signals from the first and second input lines as a control signal of a first logic is input; And control the operation of the pull-up means and the pull-down means by the signals from the reference voltage generating means and the potential comparing means, respectively, as the control signal of the second logic is inputted to adjust the potential of the output terminal. And a switching means for keeping the inverted state at all times. The pull-up driver means of claim 1, wherein the switching means is connected between a first input line and the pull-up means and outputs a data signal from the first input line by a control signal of the first logic. A first switching means connected to the first input means and a second input line and the pull-down means, and transferring the data signal from the second input line to the pull-down driver means by a control signal of the first logic. A third switching means connected between the second switching means, the potential comparing means and the pull-up means, and transferring the output signal of the potential comparing means to the pull-up driver means by the control signal of the second logic; Means, connected between the reference voltage generating means and the pull-down means, and the pull-down number of output signals of the reference voltage generating means by the second logic control signal. And a switching control signal input terminal for inputting a signal for controlling the operation of the first to fourth switching means, respectively. 3. The data output buffer as claimed in claim 2, wherein said first to fourth switching means are transfer gates. 3. The data output buffer as claimed in claim 2, wherein the first and second switching means are turned on / off in opposition to the third and fourth switching means according to the control signal of the first logic. The PMOS transistor of claim 1, wherein the reference voltage generating means is connected between a power supply voltage and an output node, and a gate is connected between the output node and the output node, and a gate is connected to the output node. Data output buffer, characterized in that consisting of NMOS transistors. The voltage generating means of claim 1, wherein the reference voltage generating means is connected between a power supply voltage Vcc and a node N15, a node R15 connected between the node N15, and a node N16, and a gate of the reference voltage generating means. NMOS transistor MN10 connected to node N15, PMOS transistor MP9 connected between node N16 and node N17, and a gate connected between node N17, node N17 and A resistor R2 connected between the ground voltage Vss, an NMOS transistor MN1 transistor connected between a power supply voltage Vcc and an output terminal N18 and a gate connected to the node N15, and the output terminal. And a PMOS transistor (MP10) connected between the node (N18) and the ground voltage (Vss) and whose gate is connected to the node (N17). The PMOS transistor according to claim 1, wherein the potential comparing means is connected between a power supply voltage Vcc, an output node N5, and a node N6, and a gate is connected to the node N6 in common. An NMOS transistor MN2 connected between an output node N5 and a node N7, a gate of which is connected to an output terminal N3 of the reference voltage generating circuit unit 11, and the node (MP2, MP3). NMOS transistor MN3, which is connected between N6 and node N7 and whose gate is connected to output terminal N4 of the data output buffer section 10, is connected between node N7 and ground voltage Vss. And an NMOS transistor (MN4) whose gate is connected to the node (N8). A data output buffer comprising a pull-up means for transmitting a high potential to an output terminal and a pull-down means for outputting a low potential to an output terminal, the data output buffer comprising: reference voltage generating means for generating a constant reference voltage and generating the reference voltage; A potential comparison means for comparing and amplifying the output signal of the means and the output signal of the output terminal and outputting the potential of the output terminal by controlling the output signal and the control signal from the reference voltage generating means and the potential comparing means. And a switching means for keeping the inverted state at all times. 9. The apparatus of claim 8, wherein the switching means comprises: first switching means for transferring a power potential to the first node by an inverted control signal connected between a power supply voltage terminal and a first node, the first node and the output; Second switching means connected between the terminals and transferring charges transferred to the first node to the output terminal by an output signal of the potential comparing means, and connected between the output terminal and the second node to the reference voltage Third switching means for transferring charge from the output terminal to the second node by an output signal of the generating means, and connected between the second node and the ground voltage terminal from the second node by a control signal. And a fourth switching means for discharging at the ground potential of the charge. 10. The data output buffer as claimed in claim 9, wherein the first switching means and the second switching means are PMOS transistors, and the third switching means and the fourth switching means are NMOS transistors.