KR100190189B1 - Data output buffer - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer of a semiconductor memory device, wherein the output device has a large driving capability in an operation in which the output data changes when the output stage is charged to a specific potential (high-impedance state), and the data is in a state of being changed. In the holding operation, having a small driving force has the effect of increasing the data transition speed and reducing noise due to the peak current.

Description

[Name of invention]

Data output buffer

[Brief Description of Drawings]

1 is a circuit diagram of a conventional data output buffer.

2 is an operation timing diagram of FIG.

3 is a circuit diagram of a data output buffer according to a first embodiment of the present invention.

4 is a circuit diagram of a data output buffer according to a second embodiment of the present invention.

5 is an operation timing diagram of FIGS. 3 and 4;

* Explanation of symbols for main parts of the drawings

11, 21: first pull-up driver control circuit

12, 22: second pull-up driver control circuit

13, 23: first pull-down driver control circuit

14, 24: second pull-down driver control circuit

MN1 to MN11: NMOS transistor

MP1 to MP11: PMOS transistor

G1 to G16: inverter and logic gate

R1 to R5: resistance

[Brief Description of Drawings]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer of a semiconductor memory device, and more particularly, to a data output buffer that realizes a fast transition speed of data in an operation of changing output data.

1 is a circuit diagram of a conventional data output buffer in which a NAND gate for outputting logic values having two output states to the nodes N1 and N3, respectively, with authentic data pu and complement data pd as inputs. A flip-flop logic circuit composed of G1 and G4, an inverter G2 and G3 connected between the node N1 and N2, a power supply voltage Vdd, and an output node N5, and are connected to the gate Is a pull-up and driver MP1 connected to the node N2, an inverter G5 connected between the node N3 and a node N4, the output node N5, and a ground voltage Vss. NMOS transistor MN1 connected between the node N4 and a gate connected to the node N4, and a Vtt voltage inputted to maintain the potential of the output terminal N5 in a high-impedance state, and the Vtt voltage. The resistor R1 is connected between the input terminal and the output terminal N5.

The operation will be described with reference to the operation timing diagram of FIG. 2. When the authenticity data pu is 'high' and the complementary data pd is 'low', the flip-flops composed of the NAND gates G1 and G4 are provided. The node N1 and the node N2 are turned low by the logic circuit to turn on the pull-up driver MP1, while the node N3 is 'high' and the node N4 is It becomes 'low' to turn off the pull-down driver MN1.

Therefore, by the above operation, the node N5 of the output terminal Dout is changed to the power supply voltage Vdd by the electric charge supplied through the pull-up driver MP1.

When the authenticity data pu is 'low' and the complementary data pd is 'high', the potential of the node N2 and the node N4 is transferred to the 'high', so that the pull-up driver ( MP1 is turned off and the pull-down driver MN1 is turned on to make the potential of the node N5 of the output terminal Dout a ground voltage.

However, in the data output buffer, when the pull-up driver MP1 and the pull-down driver MN1 are both turned off, the potential of the node N5 of the output terminal Dout is changed to the resistance R1. ) To make ('high' level voltage-'low 'level voltage / 2: 2 (V _H -V _L ) / 2｝).

The reason for this is to increase the operation speed by having a mid-level voltage value between the power supply voltage Vdd supplied through the pull-up driver MP1 and the ground voltage supplied through the pull-down driver MN1. To do that.

However, when data is continuously output to the output terminal Dout, that is, when 'low' data is output immediately after the 'low' data is output to the output terminal, the potential difference is greatly widened. It takes a long time to transition to the power supply voltage (Vdd) causes a problem that the operation speed is slow.

In addition, when the driving force of the pull-up driver MP1 is increased to obtain a high potential with the output terminal Dout, a large amount of current temporarily flows through the pull-up driver MP1, and thus the output terminal side. There is a problem that noise occurs due to peak current.

In addition, if the driving force of the pull-up driver is reduced in order to prevent this noise, the operation speed becomes slow.

Accordingly, an object of the present invention is to provide a data output buffer in which the transition speed of data is rapidly improved when data is continuously output.

It is another object of the present invention to provide a data output buffer which reduces noise generated at an output stage by implementing an output device having a large driving capability in an operation of changing output data and a small driving capability in an operation of maintaining data. have.

In order to achieve the above object, in the data output buffer of the present invention, pull-up driver means for supplying a power potential (Vdd) to the output terminal, pull-down driver means for supplying a ground potential to the output terminal, and First pull-up driver control means for controlling the operation by outputting the first potential for a predetermined time to the pull-up driver means, and outputting the second potential after the predetermined time to the pull-up driver means for the operation Second pull-up driver control means for controlling, first pull-down driver control means for outputting a second potential to the pull-down driver means for a predetermined time and controlling its operation, and the pull-down driver means Second pull-down driver control means for outputting the fourth potential after a predetermined time and controlling its operation.

Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

3 is a circuit diagram of a data output buffer according to a first embodiment of the present invention, in which logic values having two output states are inputted as authentic data pu and complement data pd to (N1, N3). Flip-flop logic circuits each configured to output NAND gates G1 and G4, an inverter G6 connected between the node N1 and node N6, and between the node N6 and node N7. The PMOS transistor Mp2 connected between the inverters G7 to G9 connected in series, the power supply voltage Vdd, and the node N2 and the gate connected to the node N6, the node N2 and the ground voltage ( NMOS transistor MN2 connected between Vss and having a gate connected to the node N6, and an NMOS transistor MN3 connected between the NMOS transistor MN2 and a ground voltage and whose gate is connected to a gain node N7. And a PMOS transistor connected between a power supply voltage Vdd and an output node N5 and whose gate is connected to the node N2. , The PMOS transistor MP3 connected between the power supply voltage Vdd and the power supply voltage Vdd and the node N8, connected to the node N8, the resistor R2 connected between the node N8 and the ground voltage, An NMOS transistor MP4 connected between the node N8 and a node N9 and a gate connected to the node N7, a node connected to the node N9 and a ground voltage, and a gate connected to the node N7. A connected NMOS transistor MN4 is connected between the power supply voltage Vdd and the node N2, and a gate is connected to the node N9.

In addition, a PMOS transistor connected between the inverters G10 to G12 connected in series between the node N3 and the node N10, the power supply voltage Vdd, and the node N4, and whose gate is connected to the node N10. A PMOS transistor MP6 connected between a node MP5 and the PMOS transistor MP5 and a node N4 and a gate connected to the node N3, and a gate connected between the node N4 and a ground voltage. An NMOS transistor MN6 connected to the node N3, an output node N5 and a ground voltage connected between the NMOS transistor MN1 connected to the node N4, a power supply voltage Vdd, and a node. The NMOS transistor MN7 connected between the resistor R3 connected between the N11 and the node N11 and the ground voltage and the gate connected to the node N11, and the node N11 and the node ( An NMOS transistor MN8 connected between Nl2 and a gate connected to the node N10, a power supply voltage Vdd, and A PMOS transistor MP7 connected between the node Nl2 and a gate connected to the node N10, and a PMOS transistor MP8 connected between the node N4 and a ground voltage and a gate connected to the node Nl2. ) And a resistor R1 connected between the Vtt voltage input to maintain the potential of the output terminal N5 in the high-impedance state, and the input terminal and the output terminal N5 that input the Vtt voltage. It was provided.

In operation, when the authenticity data pu is 'high' and the complementary data pd is 'low', the output node N1 is formed by a flip-flop logic circuit composed of the NAND gates G1 and G4. ) Is 'low', node N6 is 'high' so that the PMOS transistor MP2 is turned off, and the NMOS transistor MN2 is turned on.

However, in order for the pull-up transistor MP1 to operate, the potential of the node N2 needs to be changed to a low potential, so the NMOS transistor MN3 must be turned on.

The potential of the node N7, which is input to the gate of the NMOS transistor MN3, is delayed for a predetermined time by the inverters G7 to G9 connected in series between the node N6 and the node N7, and then 'low'. 'Potential signal is transmitted.

In the meantime, the potential of the node N7 remains 'high' by the previous data signal, thereby turning on the NMOS transistor MN3 to supply the ground potential to the potential of the node N2. do.

Accordingly, the pull-up transistor MP1 is turned on only for a predetermined time delayed by the inverters G7 to G9 to supply the power potential Vdd to the output terminal N5.

However, when the potential of the node N7 has a 'high' state before the signal of the controller is changed, the PMOS transistor MP4 is turned off and the NMOS transistor MN8 is turned on so that the node ( N12), the potential of the node N9 input to the gate of the NMOS transistor MN5 is made the ground potential Vss to prevent the supply of current to the node N2.

On the other hand, when the potential of the node N7 is changed to 'low' by an input data signal, the NMOS transistor MN3 is turned off and the PMOS transistor MP4 is driven to supply power to the node N9. Will supply (Vdd).

At this time, the NMOS transistor MN5 is operated by the potential of the node N9, and the node N2 is supplied to the node N2 by supplying the value Vdd-V _T of the threshold potential of the power potential-NMOS transistor. The potential of N2) has a value (Vdd-Vss / 2) between the ground potential and the power supply potential at the ground potential Vss.

Therefore, the constant high potential is continuously output to the output terminal N5 through the pull-up transistor MP1.

Since the authenticity data pu is 'high' and the complementary data pd is 'low', the node N3 becomes 'high' so that the PMOS transistor MP6 is turned off and the NMOS transistor ( MN6 is turned on to supply the ground potential to node N4.

During the time when the potential of the node N3 is delayed by the inverters G10 to G12 for a predetermined time, the potential of the node N10 has a previous data signal and thus becomes 'high'.

At this time, the PMOS transistor MP5 is turned off by the potential of the node N10, and the NMOS transistor MN8 is turned on to supply the power potential Vdd to the node N12. The PMOS transistor MP8 is turned off so that the node N4 is not affected.

At this time, if the node N10 transitions to low after being delayed by the epidermal inverters G10 to G12 due to the change of the input data signal, the PMOS transistor MP5 is turned on but the PMOS transistor MP6 is turned on. Power is not supplied to the node N4 because is turned off.

In addition, the PMOS transistor MP7 is turned on but the PMOS transistor MP8 is turned off, so that the potential of the node N4 is grounded by the NMOS transistor MN8 so that the pull-down transistor is turned on. MN1 is to be turned off.

Therefore, when the high potential is output to the output terminal, the transition speed of the data is rapidly increased in the operation of continuously changing the input data signal, and the noise generated by the peak current is also reduced.

4 is a circuit diagram of a data output buffer according to a second embodiment of the present invention, in which nodes of the nodes N1 and N3 have a logic value between the two output states by inputting authenticity data pu and complementary data pd. A flip-flop logic circuit composed of NAND gates G1 and G4 respectively outputted to each other, an inverter G6 connected between the node N1 and the node N6, and between the node N6 and the node N7. A PMOS transistor MP2 connected between an inverter G7 to G9 connected in series to a power supply voltage Vdd and a node N2, the gate of which is connected to the node N6, and the node N2 and a ground voltage. An NMOS transistor MN2 connected between (Vss) and a gate connected to the node N6, the NMOS transistor MN2 and a ground voltage Vss, and a gate connected to the node N7. PMOS connected between transistor MN3 and power supply voltage Vdd and output node N5 with a gate connected to node N2. PMOS transistors MP9 and MP10 connected in series with a diode structure between the transistor MP1, the power supply voltage Vdd and the node N14, and a resistor connected between the node N14 and the ground voltage Vss. An NMOS transistor MN9 connected between a node R4 and the node N14 and a node N2 and a gate connected to the node N13, and an inverted signal of the node N7 and the node N6 are input. And a NOR gate G14 for outputting the NOR value to the node N13.

And a PMOS transistor connected between an inverter (G10 to G12) connected in series between the node (N3) and a node (N10), a power supply voltage (Vdd) and a node (N4), and whose gate is connected to the node (N10). MP5 and a PMOS transistor MP6 connected between the PMOS transistor MP5 and the node N4 and a gate connected to the node N3, and between the node N4 and the ground voltage Vss. An NMOS transistor MN6 having a gate connected to the node N3, an output node N5 and a ground voltage Vss, and a NMOS transistor MN1 having a gate connected to the node N4 and a power supply voltage; Resistor R5 connected between Vdd and node N16, NMOS transistors MN10 and MN11 connected in a diode structure between node N16 and ground voltage Vss, and node N16. And a PMOS transistor MP11 connected between node N4 and having a gate connected to node N15, the node N10 and the node; A NAND gate N15 for outputting the NAND operation value by inputting the inverted signal of the node N3 to the node N15 and an input for maintaining the potential of the output terminal N5 in a high-impedance state. A resistor R1 connected between the Vtt voltage and the input terminal for inputting the Vtt voltage and the output terminal N5 was provided.

In operation, when the authenticity data pu is 'high' and the complementary data pd is 'low', the output node N1 is formed by a flip-flop logic circuit composed of the NAND gates G1 and G4. ) Is low, the node N6 is high, the PMOS transistor (MP2) is turned off, the NMOS transistor (MN2) is turned on.

However, in order for the pull-up transistor MP1 to operate, the potential of the node N2 needs to be changed to a low potential, so the NMOS transistor MN3 must be turned on.

The potential of the node N7, which is input to the gate of the NMOS transistor MN3, is delayed for a predetermined time by the inverters G7 to G9 connected in series between the node N6 and the node N7, and then 'low'. 'Potential signal is transmitted.

In the meantime, the potential of the node N7 attracts the 'high' state by the previous data signal, thereby turning on the NMOS transistor MN3 to raise the ground potential Vss to the potential of the node N2. Will be supplied.

Accordingly, the pull-up transistor MP1 is turned on only for a predetermined time delayed by the inverters G7 to G9 to supply the power potential Vdd to the output terminal N5.

The PMOS transistors MP9 to MP10 connected in series between the power supply voltage Vdd and the node N14 are always turned on in a diode structure to supply power to the node N14-the PMOS transistors MP9 and MP10. The threshold voltage potential of Vdd-2V _T is transferred.

The potential of the node Nl4 transfers charge to the node N2 by the operation of the NMOS transistor MN9, thereby controlling the operation of the pull-up transistor MP1.

Then, the output signal N13 of the NOR gate G14 that controls the operation of the NMOS transistor MN9 has a potential of the node N6 in the 'high' state being 'low' signaled by the inverter G13. Is inverted to the NOR gate G14 and is input to one side terminal, and the potential of the node N6 in the 'high' state is delayed by a low signal by the inverters G7 to G9 to the node N7. When the NOR is input to the other terminal of the NOR gate Gl4, the NMOS transistor MN9 is driven by outputting 'high' to the node N13, thereby supplying a power supply voltage to the node N2-the PMOS transistor. The threshold voltage potentials Ydd-2V _T of MP9 and MP10 are transferred.

At this time, since the potential of the node N2 has the ground potential Vss since the NMOS transistors MN2 and MN3 are turned on, the potential of the node N2 is actually passed through the NMOS transistor MN9. The electric potential transmitted from the node Nl4 is slightly higher than the ground potential Vss.

Therefore, a constant high potential is continuously output to the output terminal N5 through the pull-up transistor MP1.

Since the authenticity data pu is 'high' and the complementary data pd is 'low', the node N3 becomes 'high' so that the PMOS transistor MP6 is turned off and the NMOS transistor ( MN6 is turned on to supply the ground potential Vss to the node N4.

During the time when the potential of the node N3 is delayed for a predetermined time by the inverters G10 to G12, the potential of the node N10 has a previous data signal and thus becomes 'high'.

At this time, the PMOS transistor MP5 is turned off by the potential of the node N10.

The NAND gate G16 inputting the inverted signal (low) of the node N3 and the node N10 (high or low) outputs a 'high' to the node Nl5, thereby outputting the PMOS transistor ( The MP11 is turned off and the node N4 remains unchanged at the ground potential Vss so that the pull-down transistor MN1 is turned off and does not drive.

Therefore, when the high potential is output to the output terminal, the transition speed of the data is rapidly improved in the operation of continuously changing the input data signal, and the noise caused by the peak current is also reduced.

5 shows an operation timing diagram for the first and second embodiments of the present invention shown in FIG. 3 and FIG.

As can be seen from the timing diagram, in order to increase the driving force of the pull-up / pull-down transistors MP1 and MN1 of the output terminal when the input data is changed, the pull-up / pull-down transistors MP1, The potential of the node input to the gate of NN1 is set to the respective ground potential (Vss) or the power supply potential (Vdd), and the structure of the double slope in order to reduce the driving force of the transistor in the t2 and t4 sections where the output data is constantly output. Each made to have.

As described above, when the data output buffer of the present invention is implemented in a semiconductor memory device whose output terminal is charged (Vtt-Vss) / 2 to a specific potential ((Vdd-Vss) / 2), data is continuously output to the output terminal. The output speed of data is improved quickly when outputting, and the noise caused by peak current is also reduced.

Claims (8)

A data output buffer in which an output terminal of a semiconductor memory device maintains a high-impedance state, comprising: a pull-up driver means for supplying a power potential Vdd to an output terminal, and a ground potential Vss to the output terminal; First pull-up driver control means for outputting a first potential for a predetermined time delayed by an inverter to the pull-up driver means, and controlling the operation thereof; and the pull-up driver means. Second pull-up driver control means for outputting a second potential after a predetermined time delayed by the inverter to control its operation, and outputting a third potential for a predetermined time delayed by the inverter to the pull-down driver means; First pull-down driver control means for controlling operation, and a fourth potential is output to the pull-down driver means after a predetermined time delayed by the inverter; And a second pull-down driver control means for controlling the control by the operation. 2. The power source of claim 1, wherein the first potential is a ground power Vss, the second potential is a mid-level potential (Vdd-Vss / 2) between a power supply potential and a ground potential, and the third potential is a power supply potential Vdd. And the fourth potential is an intermediate level potential (Vdd-Vss / 2) between a power supply potential and a ground potential. The first pull-up driver control means includes: inverters G7 to G9 connected in series between the node N6 and the node N7, a power supply voltage Vdd, and a node N2. A PMOS transistor MP2 connected between the node N6 and a gate connected to the node N6, and an NMOS transistor MN2 connected between the node N2 and the ground voltage Vss and a gate connected to the node N6. And an NMOS transistor (MN3) connected between the NMOS transistor (MN2) and a ground voltage (Vss) and whose gate is connected to the node (N7). 2. The PMOS transistor (MP3) and the node (N8) of claim 1, wherein the second pull-up driver control means is connected between a power supply voltage (Vdd) and a node (N8) and a gate is connected to the node (N8). And a PMOS transistor MP4 connected between the node N8 and the node N9 and a gate connected to the node N7, and the node R2 connected between the ground voltage Vss and the node N7. NMOS transistor MN4 connected between node N9 and ground voltage Vss and a gate connected to node N7, a power supply voltage Vdd and node N2, and a gate connected to node N9. Data output buffer, characterized in that consisting of the connected NMOS transistor (NM5). 2. The device of claim 1, wherein the second pull-up driver control means includes: a PMOS transistor (MP9 and MP10) connected in series with a diode structure between a power supply voltage (Vdd) and a node (N14), the node (N14) and The resistor R4 connected between the ground voltage Vss, the NMOS transistor MN9 connected between the node N14 and the node N2 and the gate connected to the node N13, and the node N7 And a NOR gate G14 for outputting a NOR value to the node N13 by using a signal as an input of one terminal and an inverted signal of the node N6 as an input of the other terminal. . 2. The first pull-down driver control means according to claim 1, wherein the inverters G10 to G12 connected in series between the node N3 and the node N10, a power supply voltage Vdd, and a node N4. A PMOS transistor MP5 connected between the PMOS transistor MP5 and a node connected to the node N10, and a PMOS transistor MP6 connected between the PMOS transistor MP5 and the node N4 and a gate connected to the node N3. And an NMOS transistor (MN6) connected between the node (N4) and a ground voltage (Vss) and whose gate is connected to the node (N3). 2. The second pull-down driver control means according to claim 1, wherein the second pull-down driver control means includes a resistor (R3) connected between the power supply voltage (Vdd) and the node (N11) and the node (N11) and the ground voltage (Vss). An NMOS transistor MN7 having a gate connected to the node N11, an NMOS transistor MN8 connected between the node N11 and a node N12, and a gate connected to the node N10; A PMOS transistor MP7 connected between a power supply voltage Vdd and the node N12 and a gate connected to the node N10, and connected between the node N4 and the ground voltage Vss, and a gate connected to the node. And a PMOS transistor (MP8) connected to (N12). 2. The second pull-down driver control means according to claim 1, wherein the second pull-down driver control means includes a resistor R5 connected between the power supply voltage Vdd and the node N16, and between the node N16 and the ground voltage Vss. NMOS transistors MN10 and MN11 connected in a diode structure, PMOS transistor MP11 connected between node N16 and node N4 and whose gate is connected to node N15, and the signal of node N10. And a NAND gate (N15) for outputting the value obtained by NAND operation to the node (N15) with the input of one terminal and the inverted signal of the node (N3) as the input of the other terminal.