KR100242474B1 - Output buffer - Google Patents

Abstract

The present invention provides an output buffer for generating an effective switching operation at an output terminal using an input data line A, a control signal line fi and an output terminal PAD of an output buffer as input means. The first inverter G8 and the second inverter G6 connected to each other, the first NOR gate NOR2 connected to the first inverter G8 and the control signal line fi, and the first inverter G8 and the control A first NAND gate ND2 connected to an inverted output of a signal line fi, an inverted output of the control signal line fi and a second inverter G6 and an output terminal PAD. 2 NOR gate NOR3, an inverted output of the input data line A, a second NAND gate ND3 connected to the control signal line fi and the output terminal PAD, and the second NOR gate NOR3 ) And a third inverter G3 and a fourth inverter G4 connected to the second NAND gate ND3, respectively, and the third and fourth inverters. It characterized in that comprises a first transistor (Q3) and a second transistor (Q4) are connected respectively to the output terminal (PAD).

Description

Output buffer circuit with instantaneous maximum current reduction function

1 is a conventional output buffer circuit.

2 is an output buffer circuit diagram of the present invention.

3 is an input / output relationship diagram of an output buffer according to the present invention.

The present invention is to solve the problem that the output signal of the high output buffer circuit of the semiconductor integrated device delays the data access time to reduce the circuit characteristics by the noise generated by the excessive instantaneous maximum current to reduce the circuit characteristics and the input signal and It is a high output buffer circuit that generates an intermediate output level state only when the input signal of the output buffer is changed by the logic combination unit combined with the control signal, which reduces the instantaneous maximum current and reduces the number of unnecessary output switching. Applicable to semiconductor integrated devices.

In the conventional output buffer circuit shown in FIG. 1, when the control signal fi changes from the logic level 1 state to the 0 state, the output level of the output voltage P4 of the output buffer is preset in advance regardless of the states of the input signals S1 and S2 of the output buffer circuit. When the control signal fi changes from the logic level 0 state to the 1 state after the change to the intermediate level, the output voltage P4 of the output buffer circuit changes to the final output logic level 1 or 0 depending on the state of the input signals S1 and S2. It is an output buffer circuit with the function of reducing the maximum current. However, such an output buffer circuit does not need the output buffer circuit because the voltage level of the output signal P4 changes to the intermediate voltage level only when the logic level of the control signal fi changes from 1 to 0 even if the logic states of the input signals S1 and S2 do not change. It induces a switching operation, which in turn causes unnecessary power consumption at the output stage.

In the present invention, in order to eliminate the above-mentioned drawbacks, in addition to the output voltage and the input control signal of the output buffer, in addition to the output voltage of the output buffer in order to eliminate unnecessary switching operation during the output signal, a new logic combination portion as the input terminal of the logic combination portion. When the input signal of the output buffer to be transmitted is changed from logic level 0 to 1 or 1 to 0, the output signal of the output buffer is changed to the final output state through the intermediate voltage level. Eliminating unnecessary switching operations by configuring logic combinations to maintain the entire state. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates the operation of the output circuit limited in the present invention. First, the initial state of each input terminal of the output buffer, that is, the logic state of the output data of the output buffer input terminal A is 0, and the logic state of the control signal fi. Assuming zero, the initial state of the output stage PAD of the output buffer is maintained at a logic zero state. When the control signal changes to the logic 1 state in the above state, the gate terminals of the PMOS and NMOS drives Q1 and Q2 of the output buffer are changed to the logic 1 and logic 0 states, respectively, to switch off the drivers Q1 and Q2. At this time, the logic state of the output terminal PAD of the output buffer maintains the current logic state 0. Now the PMOS and NMOS drive Q1 of the output buffer when the logic state of the output data of the output buffer input stage A changes to 1 while the control signal is changed to 1 state and the logic state of the output buffer output pad (PAD) remains 0. Q2 remains switched off while PMOS Q3 drives to intermediate output levels, logic state 1 of output buffer input A, logic state 1 of control signal fi, and initial logic state of output buffer PAD of output buffer. By combining with 0, PMOS drive Q3 is switched on so that the voltage level of output stage PAD of output buffer goes to logic 1 state. After that, when the voltage level of the output stage PAD is increased to be greater than the logic threshold hold voltage level of the logic combination NOR logic NOR3, the output stage 8 of the NOR logic NOR3 of the logic combination portion changes to logic state 0, and eventually the PMOS. Switch off drive Q3 so that the output stage's output stage (PAD) stays at an intermediate level between logic 1 and 0.

Then, when the control signal fi returns to the logic 0 state, the PMOS (Q3) and NMOS (Q4) for driving to the intermediate output level are switched off, and the output value of the logic 1 state of the input data line A of the output buffer is output via the logic combination part. The drive PMOS Q1 is switched on and the NMOS Q2 is switched off so that the output stage PAD of the output buff is output as 1 in the final logic state. Secondly, when only the control signal fi is changed to logic state 1 from the final input / output state (the logic state of A is 0 and the logic state of fi is 0) of the output buffer of the first state, the output drive PMOS (Q1) of the output buffer, Since the NMOS Q2 is switched off and the PMOS Q3 and NMOS Q4, which serve as intermediate output level driving functions, are switched off, the logic state of the output terminal PAD of the output buffer remains at 1 state. When the control signal fi changes to the logic state 0 again, the output drive PMOS (Q1) of the output buffer is switched on by a logic combination with the logic state 1 of the output buffer input stage A, and the NMOS (Q2) switches off and the remaining PMOS (Q3). ), The NMOS Q4 is switched off to maintain the output stage PAD in a logic 1 state.

Third, the control signal fi is changed to logic state 1 again from the final input / output state (the logic state of A is 1, the logic state of fi is 0) of the output buffer of the second state, and the logic state of output data A is maintained at 1. The output driver PMOS (Q1), NMOS (Q2), and PMOS (Q3) and NMOS (Q4), which serve as intermediate output level driving, are switched off. After that, the control signal fi is kept in logic state 1, and when the value of output data A changes to logic state 0, only the NMOS (Q4) which acts as an intermediate output level drive through the logic combination part is switched on and the remaining PMOS ( Q1, Q3) and NMOS Q4 are switched off so that the voltage level of output stage PAD is increased to 1 in logic state. After that, when the voltage level of the output terminal PAD becomes lower than the logic threshold hold voltage of the NAND logic ND3 of the logic combination unit, the output terminal 9 of the NAND logic ND3 instantly changes to 1 in a logic state, and eventually the inverter logic G4. After the logic state is reversed, the logic state 0 is transmitted to the gate of NMOS Q4 to switch off the NMOS Q4 to prevent the voltage level of the output stage from being lowered. When the control signal fi, which remains at logic state 1 again, returns to logic state 0, the intermediate output level driving drive PMOS (Q3), NMOS (Q4) and output drive PMOS are combined with logic state 0 of the output data through a logic combination part. By switching off (Q1) and switching on only output drive NMOS (Q2), the logic state of output stage PAD is maintained at zero.

Fourth, output buffer while the control signal fi is changed to logic state 1 and the logic state of output data A is maintained at the last input / output state (the logic state of A is 0 and the logic state of fi is 0) of the third state. The output drive PMOS (Q1), NMOS (Q2) and the intermediate output level drive drive PMOS (Q3), NMOS (Q4) of all the switching off, so the logic state of the output stage (PAD) of the output buffer is kept at zero. When the control signal fi is changed to 0 in the logic state, only the output drive NMOS (Q2) of the output buffer is switched on by the logic state 0 and the logic combination of the output buffer input stage A, and the remaining PMOS (Q1, Q3) NMOS (Q4) is switched. Off, the logic state of the output stage PAD remains at zero.

Finally, in FIG. 3, the instantaneous maximum current of the output stage PAD is driven by the logic threshold level and the intermediate output level of the NOR logic NOR3, NAND logic ND3, and the inverters G3 and G4 of the logic combination unit. By controlling the size of the PMOS Q3 and NMOS Q4, the amount of load on the output stage PAD of the output buffer, and the time intervals Ta and Tb of the input data A and the control signal fi given in FIG. It can be controlled freely.

Therefore, the present invention is an output stage when the effective switching operation (change from logic state 0 to 1 or 1 to 0) by the logical combination of the input data line and the control signal of the output buffer to be transmitted to prevent unnecessary switching operation of the conventional output buffer. The output buffer is configured to change to this intermediate level.

This output buffer can reduce power consumption at the output stage of the existing output buffer, and PMOS (Q3) which acts as the logic threshold level and the intermediate output level of logic gates (ND3, NOR3, G3, G4) connected to the output stage. ), The amount of instantaneous maximum current can be freely controlled by adjusting the size of the NMOS Q4 and adjusting the time intervals Ta and Tb of the input data line and the control signal.

Claims (1)

An output buffer for generating an effective switching operation at an output terminal using an input data line A, a control signal line fi, and an output terminal PAD of an output buffer as an input means, the first buffer connected to the input data line A; Inverter G8 and second inverter G6, a first NOR gate NOR2 connected to the first inverter G8 and the control signal line fi, the first inverter G8 and the control signal line A first NAND gate ND2 connected to an inverted output of fi, an inverted output of the control signal line fi and a second NOR gate connected to the second inverter G6 and the output terminal PAD. NOR3), a second NAND gate ND3 connected to the inverted output of the input data line A, the control signal line fi, and the output terminal PAD, the second NOR gate NOR3, and the second 3rd inverter G3 and 4th inverter G4 connected to 2 NAND gate ND3, and the said 3rd inverter, 4th inverter, and the said output, respectively An output buffer, characterized in that comprises a first transistor (Q3) and a second transistor (Q4) are connected respectively to (PAD).