KR100241539B1 - Method for forming gate electrode of semiconductor device - Google Patents
Method for forming gate electrode of semiconductor device Download PDFInfo
- Publication number
- KR100241539B1 KR100241539B1 KR1019930031178A KR930031178A KR100241539B1 KR 100241539 B1 KR100241539 B1 KR 100241539B1 KR 1019930031178 A KR1019930031178 A KR 1019930031178A KR 930031178 A KR930031178 A KR 930031178A KR 100241539 B1 KR100241539 B1 KR 100241539B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- gate electrode
- gate
- oxide film
- semiconductor device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Abstract
본 발명은 반도체 소자의 게이트 전극 형성방법에 관한 것으로, 반도체 소자의 ESD(Electro Static Discharge) 보호회로에 사용되는 FET(Field Effect Transistor)의 필드 산화막을 게이트 산화막으로 사용하고, 상기 게이트 산화막 상부에 제1차 게이트(Gate) 전극을 형성한 다음 제1중간 절연막 형성후 제2차 게이트 전극을 형성하여 소자의 신뢰성을 향상시키는 반도체 소자의 게이트 전극 형성방법에 관해 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode of a semiconductor device, wherein a field oxide film of a field effect transistor (FET) used in an electrostatic discharge (ESD) protection circuit of a semiconductor device is used as a gate oxide film, and is formed on the gate oxide film. A method of forming a gate electrode of a semiconductor device is described, in which a primary gate electrode is formed, followed by formation of a first intermediate insulating film, and a second gate electrode, thereby improving reliability of the device.
Description
제1도는 종래의 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 소자의 단면도.1 is a cross-sectional view of a device for explaining a gate electrode forming method of a conventional semiconductor device.
제2도는 제1도의 등가 회로도.2 is an equivalent circuit diagram of FIG.
제3(a)도 내지 제3(c)도는 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 소자의 단면도.3 (a) to 3 (c) are cross-sectional views of a device for explaining a method of forming a gate electrode of a semiconductor device according to the present invention.
제4도는 제3(c)도의 등가회로도.4 is an equivalent circuit diagram of FIG. 3 (c).
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : N-웰1: silicon substrate 2: N-well
3 : 필드 산화막 4 : 드레인 영역3: field oxide film 4: drain region
5 : 소오스 영역 6 : 중간 절연막5 source region 6 intermediate insulating film
7 : 게이트 및 드레인 전극용 금속배선 8 : 소오스 전극용 금속배선7 metal wiring for gate and drain electrodes 8 metal wiring for source electrodes
9 : 제1차 게이트 전극 10 : 제1중간 절연막9: primary gate electrode 10: first intermediate insulating film
11 : 제1차 게이트와 제2차 게이트 전극 연결용 콘택11: contact for connecting the primary gate and the secondary gate electrode
12 : 제2차 게이트 전극 13 : 금속배선 연결용 콘택12: secondary gate electrode 13: metal wire contact
14 : 게이트 및 드레인 전극용 금속배선 15 : 소오스 전극용 금속배선14 metal wiring for gate and drain electrodes 15 metal wiring for source electrodes
16 : 제2중간 절연막16: second intermediate insulating film
본 발명은 반도체 소자의 게이트 전극 형성방법에 관한 것으로, 특히 반도체 소자의 ESD(Electro Static Discharge) 보호회로에 사용되는 FET(Field Effect Transistor)의 필드 산화막을 게이트 산화막으로 사용하고, 상기 게이트 산화막 상부에 제1차 게이트(Gate) 전극을 형성한 다음 제1중간 절연막 형성후 제2차 게이트 전극을 형성하여 소자의 신뢰성을 향상시키는 반도체 소자의 게이트 전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode of a semiconductor device. In particular, a field oxide film of a field effect transistor (FET) used in an electrostatic discharge (ESD) protection circuit of a semiconductor device is used as a gate oxide film, The present invention relates to a method of forming a gate electrode of a semiconductor device, in which a first gate electrode is formed, followed by a first intermediate insulating film, and a second gate electrode.
일반적으로 ESD 보호용 FET의 게이트 전극으로는 메탈(metal)을 사용하므로 층간 절연을 위해 사용되는 중간절연막(inter layer insulator)으로 인하여 게이트 전극의 두께가 10,000~15,000Å 정도로 두꺼워 트랜지스터의 문턱전압(VT)이 상당히 높다. 그러면 종래의 반도체 소자의 게이트 전극 형성방법을 제1도 및 제2도를 통해 설명하면 다음과 같다.In general, the gate electrode of the ESD protection FET, uses the metal (metal) so the threshold voltage of the thick intermediate insulating film (inter layer insulator) with the thickness of the gate electrode 10,000 ~ 15,000Å due used for insulating the transistor (T V ) Is quite high. A method of forming a gate electrode of a conventional semiconductor device will now be described with reference to FIGS. 1 and 2.
종래의 반도체 소자의 게이트 전극 형성방법은 제1도에 도시된 바와같이 실리콘 기판(1)상에 N-웰(Well)영역 (2)을 형성한 후 활성(active) 영역을 분리하는 필드 산화막(3)이 게이트 산화막 역할을 하도록 형성하고 상기 필드 산화막(3) 양측에 n+ 또는 p+ 이온을 주입하여 드레인 영역(4) 및 소오스 영역(5)을 형성한다. 또한 상기의 전체구조상에 중간 절연막(6)을 형성한 다음 마스크 공정 및 사진식각 공정에 의해 금속배선용 콘택을 형성하고 상기 콘택을 배선용 금속으로 매립하여 게이트 및 드레인 전극용 금속배선(7) 및 소오스 전극용 금속배선(8)을 형성한다. 그런데 게이트 산화막으로 사용되는 필드산화막(3) 및 중간절연막(6)의 두께가 두꺼워 트랜지스터의 문턱전압(VT)이 높고, 제2도에 도시된 등가회로와 같이 게이트단자(7) 및 드레인 단자(4)가 공통으로 사용되므로 이 단자에 동시에 전압이 인가되면 게이트와 소오스간의 게이트 산화막 항복(gate oxide breakdown) 현상으로 인해 소자가 파괴되며, 또한 고전압 인가시 드레인 접합 스파이킹(drain junction spiking)현상도 발생된다.In the conventional method for forming a gate electrode of a semiconductor device, as shown in FIG. 3) is formed to act as a gate oxide layer, and the drain region 4 and the source region 5 are formed by implanting n + or p + ions into both sides of the field oxide layer 3. In addition, an intermediate insulating film 6 is formed on the entire structure, a metal wiring contact is formed by a mask process and a photolithography process, and the contact is filled with a metal for wiring so that the metal wiring 7 for the gate and drain electrodes 7 and the source electrode are formed. A metal wiring 8 is formed. However, because the thickness of the field oxide film 3 and the intermediate insulating film 6 used as the gate oxide film is thick, the threshold voltage V T of the transistor is high, and the gate terminal 7 and the drain terminal are similar to those of the equivalent circuit shown in FIG. Since (4) is commonly used, if a voltage is applied to this terminal at the same time, the device is destroyed due to a gate oxide breakdown phenomenon between the gate and the source, and drain junction spiking occurs when a high voltage is applied. Is also generated.
따라서, 본 발명은 FET의 필드 산화막을 게이트 산화막으로 사용하고, 상기 게이트 산화막 상부에 제1차 게이트 전극을 형성한 다음 제1중간 절연막 형성후 제2차 게이트 전극을 형성하여 상기한 단점을 해소할 수 있는 반도체 소자의 게이트 전극 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention solves the above disadvantages by using a field oxide film of the FET as a gate oxide film, forming a first gate electrode on the gate oxide film, and then forming a second gate electrode after forming the first intermediate insulating film. It is an object of the present invention to provide a method for forming a gate electrode of a semiconductor device.
상기한 목적을 달성하기 위한 본 발명은 실리콘 기판(1)상에 N-웰 영역(2)을 형성한 후 활성영역을 분리하는 필드 산화막(3)이 게이트 산화막 역할을 하도록 형성하고, 상기 필드 산화막(3) 상부에 제1차 게이트 전극(9)을 형성하는 단계와, 상기 단계로부터 상기 필드 산화막(3) 양측에 n+ 또는 p+ 이온을 주입하여 드레인 영역(4) 및 소오스 영역(5)을 형성하는 단계와, 상기 단계로부터 전체 구조상에 제1중간 절연막(10)을 형성한 후 전극 연결용 콘택(11)을 형성한 다음 제2차 게이트 전극(12)을 형성하는 단계와, 상기 단계로부터 전체 구조상에 제2중간 절연막(16)을 형성한 후 전극 연결용 콘택(13)을 형성한 다음 게이트 및 드레인 전극용 금속배선(14) 및 소오스 전극용 금속배선(15)을 형성하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is formed so that the field oxide film 3 separating the active region after forming the N-well region 2 on the silicon substrate 1 to serve as a gate oxide film, the field oxide film (3) forming a primary gate electrode 9 thereon, and implanting n + or p + ions into both sides of the field oxide film 3 from the step to form a drain region 4 and a source region 5 And forming a first intermediate insulating film 10 on the entire structure from the step, forming an electrode connection contact 11 and then forming a second gate electrode 12, Forming a second intermediate insulating film 16 on the structure, forming an electrode connection contact 13, and then forming metal gates 14 for gate and drain electrodes and metal wires 15 for source electrodes. It features.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3(a)도 내지 제3(c)도는 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 소자의 단면도로서, 제4도를 참조하여 설명하면 다음과 같다.3 (a) to 3 (c) are cross-sectional views of a device for explaining a method of forming a gate electrode of a semiconductor device according to the present invention, which will be described below with reference to FIG.
제3(a)도는 실리콘 기판(1)상에 N-웰(Well) 영역(2)을 형성한 후 활성(active) 영역을 분리하는 필드 산화막(3)이 게이트 산화막 역할을 하도록 형성하고, 상기 필드 산화막(3) 상부에 제1차 게이트 전극(9)을 형성하되 제1차 게이트 전극(9)의 일측은 상기 필드 산화막(3)의 끝부분까지, 그것의 다른 측은 상기 필드 산화막(3)보다 짧게 형성한 다음 상기 필드 산화막(3) 양측으로 n+ 또는 p+ 이온을 주입하여 상기 실리콘 기판(1)상에 드레인 영역(4) 및 소오스 영역(5)이 형성된 상태의 단면도이다.FIG. 3 (a) shows that the field oxide layer 3 separating the active region after forming the N-well region 2 on the silicon substrate 1 serves as a gate oxide layer. The primary gate electrode 9 is formed on the field oxide layer 3, but one side of the primary gate electrode 9 is extended to the end of the field oxide layer 3, and the other side thereof is the field oxide layer 3. It is a cross-sectional view of a state in which a drain region 4 and a source region 5 are formed on the silicon substrate 1 by forming a shorter layer and then implanting n + or p + ions to both sides of the field oxide film 3.
제3(b)도는 제3(a)도의 구조상에 제1중간 절연막(10)을 형성한 후 마스크 공정 및 사진식각 공정에 의해 전극 연결용 콘택(11)을 형성하고 제2차 게이트 전극(12)을 형성한 상태의 단면도이다. 이때 드레인 영역(4)은 상기 제2차 게이트 전극(12)과 서로 연결되고, 소오스 영역(5) 방향의 상기 제2차 게이트 전극(12)은 상기 필드 산화막(3)보다 길게 형성된다.In FIG. 3 (b), after forming the first intermediate insulating film 10 on the structure of FIG. 3 (a), the electrode connecting contact 11 is formed by a mask process and a photolithography process, and the secondary gate electrode 12 is formed. It is sectional drawing of the state formed. In this case, the drain region 4 is connected to the secondary gate electrode 12, and the secondary gate electrode 12 in the direction of the source region 5 is formed longer than the field oxide layer 3.
제3(c)도는 제3(b)도의 구조상에 제2중간 절연막(16)을 형성한 후 마스크 공정 및 사진식각 공정에 의해 금속배선용 콘택(13)을 형성하고 상기 콘택(13)을 배선용 금속으로 매립하여 게이트 및 드레인 전극용 금속배선(4) 및 소오스 전극용 금속배선(15)이 형성된 상태의 단면도이다.In FIG. 3 (c) or the second intermediate insulating film 16 on the structure of FIG. 3 (b), a metal wiring contact 13 is formed by a mask process and a photolithography process, and the contact 13 is made of metal for wiring. Sectional drawing of the state in which the metal wiring 4 for gate and drain electrodes, and the metal wiring 15 for source electrodes were formed.
제3(c)도에 도시된 바와같이 상기 필드 산화막(3)이 게이트 산화막 역할을 하므로 트랜지스터의 문턱전압(VT)은 상대적으로 낮아지고 제4도의 등가회로에서와 같이 소오스 영역(5) 쪽의 게이트 오버랩(over lap) 부분을 제2차 게이트로 사용하여 게이트 및 소오스 간의 항복(Vreakdown) 현상이 개선되며, 상기 제2차 게이트 전극(12)을 드레인 영역(4)과 게이트 및 드레인 전극용 금속배선(14)을 연결하는 내부배선으로 사용하여 드레인 접합 스파이킹(drain junction spiking) 현상을 완화시켜 준다.As shown in FIG. 3 (c), since the field oxide film 3 serves as a gate oxide film, the threshold voltage V T of the transistor is relatively low, and as in the equivalent circuit of FIG. By using the gate overlap portion of the gate as the secondary gate, the breakdown between the gate and the source is improved, and the secondary gate electrode 12 is used for the drain region 4 and the gate and drain electrode. By using the metal wiring 14 as an internal wiring to connect to the drain junction spiking (drain junction spiking) phenomenon is alleviated.
상술한 바와같이 본 발명에 의하면 FET의 필드 산화막을 게이트 산화막으로 사용하고, 상기 게이트 산화막 상부에 제1차 게이트 전극을 형성한 다음 제1중간 절연막 형성후 제2차 게이트 전극을 형성하여 트랜지스터의 문턱전압을 낮게하여 전류싱크(Current Sink)를 빠르게 하고, 게이트 및 소오스간 항복(breakdown) 현상이 개선되며 드레인 접합 스파이킹(dran junction spiking) 현상을 완화시키는데 탁월한 효과가 있다.As described above, according to the present invention, a field oxide film of a FET is used as a gate oxide film, a first gate electrode is formed on the gate oxide film, a second gate electrode is formed after the first intermediate insulating film is formed, and a threshold of the transistor is formed. Lower voltages speed current sinks, improve gate-to-source breakdown, and mitigate drain junction spiking.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930031178A KR100241539B1 (en) | 1993-12-30 | 1993-12-30 | Method for forming gate electrode of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930031178A KR100241539B1 (en) | 1993-12-30 | 1993-12-30 | Method for forming gate electrode of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950021247A KR950021247A (en) | 1995-07-26 |
| KR100241539B1 true KR100241539B1 (en) | 2000-02-01 |
Family
ID=19374185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930031178A KR100241539B1 (en) | 1993-12-30 | 1993-12-30 | Method for forming gate electrode of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100241539B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100393200B1 (en) * | 2001-02-20 | 2003-07-31 | 페어차일드코리아반도체 주식회사 | Field transistor for electrostatic discharge protection and method for fabricating the same |
-
1993
- 1993-12-30 KR KR1019930031178A patent/KR100241539B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR950021247A (en) | 1995-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH05259454A (en) | Semiconductor device with improved breakdown-voltage characteristic | |
| JPH0236071B2 (en) | ||
| KR950012705A (en) | Transistor of electrostatic discharge protection circuit and its manufacturing method | |
| US5744840A (en) | Electrostatic protection devices for protecting semiconductor integrated circuitry | |
| US5744838A (en) | Semiconductor device having internal circuit other than initial input stage circuit | |
| KR100241539B1 (en) | Method for forming gate electrode of semiconductor device | |
| US5698886A (en) | Protection circuit against electrostatic discharges | |
| US5736772A (en) | Bifurcated polysilicon gate electrodes and fabrication methods | |
| KR100309883B1 (en) | Semiconductor Device, Electrostatic Discharge Protection Device and Insulation Break Prevention Method | |
| US6180983B1 (en) | High-voltage MOS transistor on a silicon on insulator wafer | |
| US7205581B2 (en) | Thyristor structure and overvoltage protection configuration having the thyristor structure | |
| CN108039362B (en) | Transistor, clamping circuit and integrated circuit | |
| JPS626661B2 (en) | ||
| KR19980043416A (en) | ESD protection circuit | |
| JPH0468576A (en) | Semiconductor device | |
| JPH0478022B2 (en) | ||
| JPS6066444A (en) | Semiconductor device | |
| KR100270956B1 (en) | Semiconductor divice having open drain input/output and method for fabricating thereof | |
| JP3071773B1 (en) | Method for manufacturing semiconductor device | |
| US6445601B1 (en) | Electrostatic discharge protection circuit | |
| CN108039364B (en) | Transistor, clamping circuit and integrated circuit | |
| JPH0817206B2 (en) | Semiconductor device | |
| KR100362180B1 (en) | Method for fabricating ESD protection device of high breakdown voltage circuit | |
| JPH0831948A (en) | Semiconductor integrated circuit device | |
| US5432369A (en) | Input/output protection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20081027 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |