KR100241512B1 - Manufacture of semiconductor - Google Patents

Manufacture of semiconductor Download PDF

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KR100241512B1
KR100241512B1 KR1019970026329A KR19970026329A KR100241512B1 KR 100241512 B1 KR100241512 B1 KR 100241512B1 KR 1019970026329 A KR1019970026329 A KR 1019970026329A KR 19970026329 A KR19970026329 A KR 19970026329A KR 100241512 B1 KR100241512 B1 KR 100241512B1
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South Korea
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film
forming
tunnel oxide
self
etching process
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KR1019970026329A
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Korean (ko)
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KR19990002658A (en
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박승희
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 플래쉬 메모리 셀 형성 방법에 관한 것으로, 게이트 형성을 위한 자기정렬 식각 공정시 터널 산화막의 손상을 방지하는 것임.The present invention relates to a method of forming a flash memory cell, and to prevent damage to a tunnel oxide layer during a self-aligned etching process for forming a gate.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

게이트를 형성하기 위한 자기정렬 식각 공정시 터널 산화막이 식각 손상되어 소자의 사이클링, 전하량 유지 특성 및 신뢰성이 저하되는 문제점을 해결하기 위함.This is to solve the problem that the cycling oxide film is etched during the self-aligned etching process for forming the gate, thereby deteriorating cycling, charge retention and reliability of the device.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

자기정렬 식각 공정시 플로팅 게이트용 폴리실리콘막의 일부를 남기므로써 식각 가스가 터널 산화막에 직접 반응되는 것이 방지되어 터널 산화막의 손상을 최소화함.By leaving part of the polysilicon film for the floating gate during the self-aligned etching process, the etching gas is prevented from directly reacting to the tunnel oxide film, thereby minimizing damage to the tunnel oxide film.

Description

플래쉬 메모리 셀 형성 방법How to Form Flash Memory Cells

본 발명은 플래쉬 메모리 셀 형성 방법에 관한 것으로, 특히 게이트 형성을 위한 자기정렬 식각 공정시 터널 산화막의 손상을 방지하기 위한 것이다.The present invention relates to a method of forming a flash memory cell, and more particularly, to prevent damage to a tunnel oxide layer during a self-aligned etching process for forming a gate.

제1도는 플래쉬 메모리 셀의 형성 방법을 설명하기 위한 소자의 단면도이다.1 is a cross-sectional view of a device for explaining a method of forming a flash memory cell.

실리콘 기판(11) 상부에 터널 산화막(12), 제1폴리실리콘막(13) 및 유전체막(14)이 순차적으로 형성된다. 이후 제2폴리실리콘막(15) 및 난반사막(16)이 순차적으로 형성된다. 콘트롤 게이트용 마스크로 사용할 식각 공정으로 제2폴리실리콘막(15)을 식각하여 콘트롤 게이트(15)를 형성하고 계속해서 자기정렬 식각 방식으로 유전체막(14), 제1폴리실리콘막(13)을 순차적으로 식각하여 플로팅 게이트(13)를 형성한다. 이러한 자기정렬 식각 공정시 식각 가스가 터널 산화막(12)과 반응하여 터널 산화막(12)에 언더컷(17)과 같은 손상 부분이 발생한다. 이러한 터널 산화막(12)의 손상부분은 후속 공정인 재 산화 공정과 소스/드레인 어닐 공정으로 어느 정도 회복하였다. 그러나 이러한 공정에도 불구하고 터널 산화막(12)에 결핍(defect)이 증가되어 소자의 사이클링 특성이 저하되며 프로그래밍의 특성을 장기간 유지하고 있어야 하는 전하량 유지 특성 역시 저하되어 전체적인 소자의 신뢰성을 확보하기 어려운 문제점이 있다.The tunnel oxide film 12, the first polysilicon film 13, and the dielectric film 14 are sequentially formed on the silicon substrate 11. Thereafter, the second polysilicon film 15 and the diffuse reflection film 16 are sequentially formed. The second polysilicon film 15 is etched to form the control gate 15 by an etching process to be used as a mask for the control gate, and the dielectric film 14 and the first polysilicon film 13 are subsequently formed by a self-aligned etching method. Etching is sequentially performed to form the floating gate 13. During the self-aligned etching process, the etching gas reacts with the tunnel oxide film 12 to generate a damaged portion such as an undercut 17 in the tunnel oxide film 12. The damaged portion of the tunnel oxide film 12 was recovered to some extent by a subsequent oxidation process and a source / drain annealing process. However, despite this process, there is an increase in defects in the tunnel oxide film 12, which degrades the cycling characteristics of the device, and also reduces the amount of charge retention that must maintain programming characteristics for a long time, making it difficult to secure reliability of the overall device. There is this.

따라서, 본 발명은 자기정렬 식각 공정시 플로팅 게이트용 폴리실리콘막의 일부를 남기므로써 식각 가스나 터널 산화막에 직접 반응되는 것이 방지되어 터널 산화막의 손상을 최소화할 수 있는 플래쉬 메모리 셀 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a method of forming a flash memory cell capable of minimizing damage to a tunnel oxide by preventing a reaction of an etching gas or a tunnel oxide directly by leaving a portion of the polysilicon film for a floating gate during a self-aligned etching process. There is a purpose.

상술한 목적을 달성하기 위한 본 발명에 따른 플래쉬 메모리 셀 형성 방법은 콘트롤 게이트용 마스크를 사용한 식각 공정으로 콘트롤 게이트를 형성하는 단계와, 플로팅 게이트를 형성하기 위한 자기정렬 식각 공정시 플로팅 게이트용 폴리실리콘막이 완충막으로 사용될 정도의 얇은 두께로 남아있도록 식각하는 단계와, 산화 공정으로 상기 폴리실리콘막의 얇은 부분을 산화시키는 단계로 이루어진 것을 특징으로 한다.The flash memory cell forming method according to the present invention for achieving the above object is a polysilicon for a floating gate during the self-aligned etching process for forming a control gate, and forming a control gate in an etching process using a mask for the control gate Etching the film so that it remains thin enough to be used as a buffer film, and oxidizing a thin portion of the polysilicon film by an oxidation process.

제1도는 플래쉬 메모리 셀의 형성 공정을 설명하기 위한 소자의 단면도.1 is a cross-sectional view of a device for explaining a process of forming a flash memory cell.

제2(a)도 내지 제2(c)도는 본 발명에 따른 플래쉬 메모리 셀의 형성 공정을 설명하기 위한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of a device for explaining a process of forming a flash memory cell according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11, 21 : 실리콘 기판 12, 22 : 터널 산화막11, 21: silicon substrate 12, 22: tunnel oxide film

13, 23 : 제1폴리실리콘막(플로팅 게이트) 14, 24 : 유전체막13, 23: first polysilicon film (floating gate) 14, 24: dielectric film

15, 25 : 제2폴리실리콘막(콘트롤 게이트) 16, 26 : 난반사막15, 25: second polysilicon film (control gate) 16, 26: diffuse reflection film

17 : 언더컷 27 : 감광막 패턴17: undercut 27: photoresist pattern

28 : 산화막28: oxide film

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제2(a)도 내지 제2(c)도는 본 발명에 따른 플래쉬 메모리 형성 공정을 설명하기 위한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of devices for describing a flash memory forming process according to the present invention.

제2(a)도를 참조하면, 실리콘 기판(21) 상부에 터널 산화막(22), 제1폴리실리콘막(23) 및 ONO 구조의 유전체막(24)을 순차적으로 형성한다. 제2폴리실리콘막(25) 및 난반사막(26)을 유전체막(24) 상에 순차적으로 형성한 후 콘트롤 게이트용 마스크를 사용한 리소그라피 공정으로 난반사막(26) 상에 감광막 패턴(27)을 형성하고, 감광막 패턴(27)을 식각 마스크로 하여 난반사막(26) 및 제2폴리실리콘막(25)을 순차적으로 식각한다. 제2폴리실리콘막(25)은 식각되어 콘트롤 게이트(25)역할을 한다.Referring to FIG. 2A, a tunnel oxide film 22, a first polysilicon film 23, and an ONO structure dielectric film 24 are sequentially formed on the silicon substrate 21. The second polysilicon film 25 and the diffuse reflection film 26 are sequentially formed on the dielectric film 24, and then the photoresist pattern 27 is formed on the diffuse reflection film 26 by a lithography process using a mask for a control gate. Then, the diffuse reflection film 26 and the second polysilicon film 25 are sequentially etched using the photosensitive film pattern 27 as an etching mask. The second polysilicon film 25 is etched to serve as a control gate 25.

제2(b)도를 참조하면, 감광막 패턴(27)이 존재하는 상태에서 자기정렬 식각법으로 유전체막(24) 및 제1폴리실리콘막(23)을 식각하는데, 이때 제1폴리실리콘막(23)을 완전히 식각하지 않고 터널 산화막(22) 상에 얇은 두께, 예를 들어 10 내지 ; 100Å의 두께만큼 남겨둔다. 이후 감광막 패턴(27)을 제거한다.Referring to FIG. 2 (b), the dielectric film 24 and the first polysilicon film 23 are etched by the self-aligned etching method in the state where the photosensitive film pattern 27 is present, wherein the first polysilicon film ( Thin thickness on the tunnel oxide film 22, for example, 10 to 10 without completely etching 23); Leave 100mm thick. Thereafter, the photoresist pattern 27 is removed.

제2(c)도를 참조하면, 산화공정을 실시하여 제1폴리실리콘막(23)의 얇은 부분을 산화시켜 산화막(28)을 형성시킨다. 산화되지 않고 남아 있는 제1폴리실리콘막(23)은 플로팅 게이트(23)역활을 한다.Referring to FIG. 2 (c), an oxidation process is performed to oxidize a thin portion of the first polysilicon film 23 to form an oxide film 28. The first polysilicon film 23 remaining without oxidation serves as the floating gate 23.

본 발명의 실시예에 의하면, 자기정렬 식각시 터널 산화막(22)이 식각 가스에 손상당하지 않도록 제1폴리실리콘막(23)을 일부 남겨둔 후 산화 공정에 의해 남겨진 제1폴리실리콘막(23)과 부분을 산화시키므로 형성된 산화막(28)이 제1폴리 실리 콘막 (23)과 터널 산화막(22) 사이에서 완충(buffer)역활을 하게 하여 터널 산화막(22)의 언더컷 현상 및 식각 공정으로 인한 결함 생성을 방지한다.According to the exemplary embodiment of the present invention, the first polysilicon film 23 left by the oxidation process after partially leaving the first polysilicon film 23 so that the tunnel oxide film 22 is not damaged by the etching gas during self-alignment etching and By oxidizing the portion, the formed oxide film 28 serves as a buffer between the first polysilicon film 23 and the tunnel oxide film 22, thereby creating defects due to the undercut phenomenon and etching process of the tunnel oxide film 22. prevent.

상술한 바와 같이 본 발명은 자기정렬 식각 공정시 식각 가스가 터널 산화막에 직접 반응되는 것을 막아주어 터널 산화막의 안정적인 특성을 확보하므로써 소자의 사이클링 특성, 전하량 유지 특성 및 신뢰성을 향상시킬 수 있는 탁월한 효과가 있다.As described above, the present invention prevents the etching gas from directly reacting to the tunnel oxide layer during the self-aligned etching process, thereby securing the stable characteristics of the tunnel oxide layer, thereby improving the cycling characteristics, the charge retention characteristics, and the reliability of the device. have.

Claims (2)

콘트롤 게이트용 마스크를 사용한 식각 공정으로 콘트롤 게이트를 형성하는 단계와, 플로팅 게이트를 형성하기 위한 자기정렬 식각 공정시 플로팅 게이트용 폴리 실리콘막이 완충막으로 사용될 정보의 얇은 두께로 남아있도록 식각하는 단계와, 산화 공정으로 상기 폴리실리콘막의 얇은 부분을 산화시키는 단계로 이루어진 것을 특징으로 하는 플래쉬 메모리 셀형성 방법.Forming a control gate by an etching process using a mask for the control gate, etching the polysilicon film for the floating gate to have a thin thickness of information to be used as a buffer during the self-aligned etching process for forming the floating gate, And oxidizing a thin portion of the polysilicon film by an oxidation process. 제1항에 있어서, 상기 자기정렬 식각 공정시 상기 폴리실리콘막은 10 내지 100Å의 두께만큼 남겨두는 것을 특징으로 하는 플래쉬 메모리 셀 형성 방법.The method of claim 1, wherein the polysilicon layer is left to a thickness of about 10 to about 100 microns in the self-aligned etching process.
KR1019970026329A 1997-06-20 1997-06-20 Manufacture of semiconductor KR100241512B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7645668B2 (en) 2006-09-18 2010-01-12 Samsung Electronics Co., Ltd. Charge trapping type semiconductor memory device and method of manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100464904B1 (en) * 1997-10-10 2005-04-19 삼성전자주식회사 Flash memory cell forming method by a self-aligned source etching
KR100684108B1 (en) * 2001-04-16 2007-02-16 삼성전자주식회사 Method of manufacturing non-volatile memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7645668B2 (en) 2006-09-18 2010-01-12 Samsung Electronics Co., Ltd. Charge trapping type semiconductor memory device and method of manufacturing the same

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