KR100239884B1 - Voltage level shift circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage level shift circuit of a semiconductor memory device. Specifically, in an erase operation of a flash memory device, an erase voltage of -10V is applied to a selected word line and a source line or a bulk is applied. In the preparation step for applying the 0V erase protection voltage to the bulk, the generation of the erase protection voltage is prevented from being delayed in accordance with the change of the power supply voltage, thereby reducing the voltage difference between the erase voltage terminal and the erase protection voltage terminal. The present invention relates to a voltage level shift circuit, which is maintained at, and suppresses the adoption of a high breakdown voltage transistor at the time of circuit fabrication, thereby improving the degree of integration.

Description

Voltage level shift circuit

The present invention relates to a semiconductor memory device, and more particularly, to a voltage level shift circuit of a semiconductor memory device.

1 shows a voltage level shift circuit of the prior art. As shown in FIG. 1, the conventional voltage level shift circuit includes a first power supply terminal 1 to which the ground voltage VSS is applied, a second power supply terminal 2 to which the power supply voltage VCC is applied, and a negative voltage ( And a third power supply terminal 3 to which Vneg) is applied. The third power supply terminal 3 is an output terminal of the external negative voltage generation circuit 100 generating an erase voltage of -10V.

Referring to FIG. 1, a conventional voltage level shift circuit includes a voltage detector 200 and a voltage level shifter 300. The voltage detector 200 receives the power supply voltage VCC and the negative voltage Vneg, detects a negative voltage Vneg of a predetermined level, and generates an erase protection voltage VH of 0V. The voltage level shifting unit 300 receives the negative voltage Vneg and the anti-erasing voltage VH in response to the control signal VS of a predetermined level applied from an address predecoder. One of (Vneg) and the erasing prevention voltage (VH) is selectively output.

The voltage detector 200 includes a first detection circuit 10, a second detection circuit 20, a third detection circuit 30, and an erase protection voltage output circuit 40.

The first detection circuit 10 includes a first P-type MOS transistor 101, a second P-type MOS transistor 102, a third P-type MOS transistor 103, and a first N-type MOS transistor 104. Consists of. The first P-type MOS transistor 101, the second P-type MOS transistor 102, and the third P-type MOS transistor 103 are P-type MOS diodes each having a gate and a drain coupled thereto. The first power supply terminal 1 is connected in series between the first node N1. The sum of the threshold voltages of the first, second, and third P-type MOS transistors 101, 102, and 103 is 5V. In the first N-type MOS transistor 104, a gate is connected to the first power supply terminal 1, a source is connected to the third power supply terminal 3, and a drain is connected to the first node N1. .

The second detection circuit 20 includes a second N-type MOS transistor 105, a fourth P-type MOS transistor 106, and a fifth P-type MOS transistor 107. In the second N-type MOS transistor 105, a drain is connected to the first power supply terminal 1, a gate is connected to the second power supply terminal 2, and a source is connected to the second node N2. In the fourth P-type MOS transistor 106, a source is connected to the second node N2, and a gate and a drain are coupled to serve as a resistance together with the second N-type MOS transistor 105. The fifth P-type transistor 107 has a source connected to the drain of the fourth P-type transistor 106, a gate connected to the first node N1, and a drain connected to the third power terminal 3. Is connected to.

The third detection circuit 30 includes a sixth P-type MOS transistor 108 and a third N-type MOS transistor 109. The sixth P-type MOS transistor 108 has a gate connected to the first power supply terminal 1, a source connected to the second power supply terminal 2, and a drain connected to the third node N3. The third N-type transistor 109 has a gate connected to the first power supply terminal 1, a source connected to the second node N2, and a drain connected to the third node N3.

The erasing prevention voltage output circuit 40 includes a first inverter 110 and a second inverter 111. The first inverter 110 receives the voltage of the third node N3 and inverts and outputs the voltage. The second inverter 111 receives an output voltage of the first inverter 110 and inverts the output voltage.

The voltage level shifting unit 300 includes a seventh P-type MOS transistor 113, an eighth P-type MOS transistor 114, a fourth N-type MOS transistor 115, a ninth P-type MOS transistor 116, and The fifth N-type MOS transistor 117 is configured. The seventh P-type transistor 113 has a gate connected to the first power supply terminal 1, a source applied with a predetermined control signal VS from the address predecoder, and a drain connected to the fourth node N4. It is connected. The eighth P-type transistor 114 has a source connected to an output terminal of the second inverter 111, a drain connected to the fourth node N4, and a gate connected to the fifth node N5. . The fourth N-type MOS transistor 115 has a source connected to the third power supply terminal 3, a drain connected to the fourth node N4, and a gate connected to the fifth node N5. The ninth P-type transistor 116 has a source connected to an output terminal of the second inverter 111, a gate connected to the fourth node N4, and a drain connected to the fifth node N5. have. The fifth N-type transistor 117 has a source connected to the third power supply terminal 3, a drain connected to the fifth node N5, and a gate connected to the fourth node N4.

2 is an operation timing diagram of a conventional level shift circuit having the configuration as described above.

Hereinafter, the operation of the voltage level shift circuit of the prior art will be described with reference to FIGS. 1 and 2.

First, a predetermined control signal VS is applied from the address predecoder through the control signal input terminal 112 and latched to the fourth node N4, and the negative voltage Vneg falls from 0V to -10V. To start. In the initial state, that is, the negative voltage level Vneg is the sum of the threshold voltage values of the first, second, and third P-type MOS transistors 101, 102, 103 connected in series with the first power supply terminal 1. In the section that does not reach about -5V, the voltage of the first node N1 changes to the same level as the negative voltage Vneg, and the change becomes slower as it approaches -5V. As the voltage of the first node N1 falls in this manner, the fifth P-type MOS transistor 107 is turned on so that the voltage level of the second node N2 gradually changes from ground to negative.

Now, when the negative voltage Vneg reaches -5V, which is the sum of the threshold voltage values of the first, second, and third P-type MOS transistors 101, 102, and 103, the voltage level of the first node N1 is Even if the negative voltage level Vneg continues to fall, it is maintained at about -5V. Accordingly, the fifth P-type MOS transistor 107 is turned off, so that the voltage of the second node N2 is maintained at a negative voltage of a predetermined level. At this time, the voltage of the second node N2 is applied to the source of the third N-type MOS transistor 109 which forms the MOS inverter together with the sixth P-type MOS transistor 108 so that the third N-type MOS transistor 109 is applied. Start to turn on. Accordingly, the voltage of the third node N3 changes to 0 V or less at the power supply voltage VCC level. The voltage of the third node is supplied to the voltage level shifting unit 300 through the first inverter 110 and the second inverter 111 to be changed to the 0V erasing prevention voltage VH. Meanwhile, the negative voltage Vneg drops to −10 V and is supplied to the voltage level shifting unit 300. Thus, according to the level of the control signal VS latched to the fourth node N4, one of the erasing prevention voltage VH and the negative voltage Vneg is selected and a row decoder through the output terminal 118. Is applied. That is, when the control signal VS is at the high level, the negative voltage Vneg is output to the column decoder, and when the control signal VS is at the low level, the erasure prevention voltage VS is output to the column decoder.

However, according to the related art described above, the fifth P-type MOS transistor 107 is gradually turned off when the negative voltage Vneg is about -5V, so that the voltage level of the second node N2 gradually moves. . On the other hand, the point where the voltage of the third node N3 transitions from the power supply voltage VCC level to 0V is the power supply voltage VCC supplied to the source of the sixth P-type MOS transistor 108 and the third N-type MOS transistor. It is determined by the difference between the voltages of the second nodes N2 applied to the source of 109. For this reason, when the level of the power supply voltage VCC changes, the section in which the voltage of the third node N3 transitions from the power supply voltage VCC level to 0V also moves to delay the generation of the 0V erasing prevention voltage VH. Occurs. As a result, the level of the negative voltage Vneg corresponding to the section in which the voltage level of the third node N3 changes to 0V may be higher than -5V.

Referring to FIG. 2, when the power supply voltage VCC is 2.5V, the erasing prevention voltage VH of 0V is generated when the negative voltage Vneg is about -5V, so there is no problem. On the other hand, in the case where the power supply voltage VCC is 3.5V, although the negative voltage Vneg continues to fall past -5V and becomes below -5.5V, 0V anti-erasing voltage VH is not generated yet. In this case, when the control signal VS of the voltage level shifting unit 300 is at a high level, the voltage difference applied between the source and the drain of the ninth P-type transistor 116 is 9V (= 3.5V-(-5.5V). ) In the same case, if the control signal VS of the voltage level shifting unit 300 is at the low level, the voltage difference applied between the source and the drain of the fifth N-type MOS transistor 117 becomes 9 V or more. In addition, if the level of the power supply voltage VCC is about 5V, a high voltage of 10V or more may be applied to both ends of each of the ninth P-type MOS transistor 116 or the fifth N-type MOS transistor 117. Then, when designing a voltage level shift circuit, a high breakdown voltage transistor must be employed, which causes a problem of lowering the density of the circuit.

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems, and the voltage level of the semiconductor memory device which generates an erase protection voltage at a negative voltage Vneg of a predetermined level regardless of the change of the power supply voltage VCC. It is to provide a shift circuit.

1 is a circuit diagram showing a voltage level shift circuit according to a conventional embodiment;

2 is an operation timing diagram of the circuit shown in FIG. 1;

3 is a circuit diagram showing a voltage level shift circuit according to an embodiment of the present invention;

4 is an operation timing diagram of the circuit shown in FIG. 3;

* Explanation of symbols on the main parts of the drawings

100: external negative voltage generation circuit 200: voltage detector

300: voltage level moving unit

According to an aspect of the present invention for achieving the above object, in the voltage level shift circuit of a semiconductor device, a voltage detector for generating a predetermined level of erasure prevention voltage by receiving a power supply voltage and a negative voltage from the outside, The negative voltage corresponding to the erase voltage of the predetermined level may be applied to the negative voltage and the erase protection voltage in response to a predetermined control signal applied from the outside by receiving the negative voltage from the outside and receiving an anti-erasing voltage of a predetermined level from the voltage detector. And a voltage level shifter for selectively outputting any one of the voltage level shifters to generate the anti-erasing voltage of a predetermined level upon detection of a negative voltage of a predetermined level.

In a preferred embodiment of this circuit, the voltage detector includes a ground terminal, a power supply voltage terminal to which the power supply voltage is applied, a negative voltage terminal to which the negative voltage is applied, a first node, the ground terminal, and the negative terminal. First detection means connected to a voltage terminal to detect a negative voltage of a predetermined level and applied to the first node, a second node, and the ground terminal connected to the power supply voltage and the negative voltage to receive the first voltage; Second detection means for applying a detection voltage of a predetermined level to the second node in response to the voltage of the node, a third node, connected to the ground terminal, receiving the power supply voltage, and applying a voltage to the voltage of the second node. In response, third detection means for applying a detection voltage of a predetermined level to said third node, and predetermined in response to a voltage of said third node of a predetermined level. Erasing prevention voltage output means for outputting the erasing preventing voltage at a level.

In a preferred embodiment of this circuit, the first detecting means comprises: a first N-type MOS transistor having a gate connected to the ground terminal and connected in series between the negative voltage terminal and the first node to form a current path; A first P-type MOS transistor with a source connected to the ground terminal and a gate and a drain connected, a second P-type MOS transistor with a source connected to a drain of the first P-type transistor and a gate and a drain connected thereto; And a third P-type MOS transistor having a source connected to the drain of the second P-type MOS transistor and a gate and a drain connected to the first node.

In a preferred embodiment of this circuit, the second detecting means comprises: a second N-type transistor having a drain connected to the ground terminal, a source connected to the second node, and a gate connected to the power supply voltage terminal; A fourth P-type MOS transistor connected with the second node, a gate and a drain connected with each other, a drain connected with a drain of the fourth P-type transistor, a source connected with the negative voltage terminal, and a gate connected with the first And a third N-type MOS transistor connected to the node.

In a preferred embodiment of this circuit, the third detecting means comprises: a fifth P-type transistor having a source connected to the power supply voltage terminal, a gate connected to the ground terminal, and a drain connected to the third node; And a fourth N-type MOS transistor connected to the third node, a gate connected to the ground terminal, and a source connected to the second node.

In a preferred embodiment of the circuit, the erasing prevention voltage output means includes a first inverter that receives the voltage of the third node and inverts it and outputs it, and a second inverter that receives and inverts the output voltage of the first inverter. It includes an inverter.

In a preferred embodiment of the circuit, the voltage level shifting unit comprises a ground terminal, a control signal input terminal to which the control signal is applied, a negative voltage terminal to which the negative voltage is applied, a fourth node, and a gate to the ground. A sixth P-type MOS transistor connected to a terminal, a source connected to the control signal input terminal, and a drain connected to the fourth node; a fifth node connected to an output terminal of the voltage level shift circuit; A seventh P-type MOS transistor connected to an output terminal of a second inverter, a drain connected to the fourth node, a gate connected to the fifth node, a source connected to the negative voltage terminal, and a drain connected to the fourth node; A fifth N-type MOS transistor connected with the gate and the fifth node, and a source connected to an output terminal of the second inverter. An eighth P-type MOS transistor connected with a drain connected with the fifth node and a gate connected with the fourth node, a source connected with the negative voltage terminal, a drain connected with the fifth node, and a gate connected with the fifth node And a sixth N-type MOS transistor connected to the four nodes.

According to another aspect of the invention, in a voltage level shift circuit of a semiconductor device, a ground terminal, a power supply voltage terminal to which a power supply voltage is applied, a negative voltage terminal to which a negative voltage is applied, a first node, and the ground First detection means connected to a terminal and the negative voltage terminal to detect and apply a negative voltage of a predetermined level to the first node, a second node, and the power supply voltage and the negative voltage connected to the ground terminal Second detection means for receiving and applying a predetermined level of detection voltage to the second node in response to the voltage of the first node; a third node; Third detection means for applying a detection voltage of a predetermined level to the third node in response to a voltage of; and a voltage of the third node N3 of a predetermined level. A voltage detector including an erase protection voltage output means for outputting an erase protection voltage of a predetermined level in response thereto, and receiving a negative voltage of the erase voltage level from the negative voltage terminal, and receiving the negative voltage of the predetermined level from the erase protection voltage output means. And a voltage level shifter configured to selectively output one of the negative voltage and the erasure prevention voltage in response to a predetermined control signal applied from an external device in response to an erase protection voltage. In the section where the negative voltage of the level is not detected, the output voltage of the erasing prevention voltage output means is the power supply voltage level, and the erasing prevention voltage output in the section after the negative voltage of the predetermined level is detected by the first detecting means. The output voltage of the means is It is characterized in that the voltage level.

In a preferred embodiment of the circuit, the first detecting means comprises: a first N-type MOS transistor having a gate connected to the ground terminal and connected in series between the negative voltage terminal and the first node to form a current path; A first P-type MOS transistor having a source connected to the ground terminal and a gate and a drain connected thereto, a second P-type MOS transistor having a source connected to a drain of the first P-type transistor and a gate and a drain connected thereto; And a third P-type MOS transistor having a source connected to the drain of the second P-type MOS transistor and a gate and a drain connected to the first node.

In a preferred embodiment of this circuit, the second detecting means comprises: a second N-type transistor having a drain connected to the ground terminal, a source connected to the second node, and a gate connected to the power supply voltage terminal; A fourth P-type MOS transistor connected with the second node, a gate and a drain connected with each other, a drain connected with a drain of the fourth P-type transistor, a source connected with the negative voltage terminal, and a gate connected with the first And a third N-type MOS transistor connected to the node.

In a preferred embodiment of this circuit, the third detecting means comprises: a fifth P-type transistor having a source connected to the power supply voltage terminal, a gate connected to the ground terminal, and a drain connected to the third node; And a fourth N-type MOS transistor connected to the third node, a gate connected to the ground terminal, and a source connected to the second node.

In a preferred embodiment of the circuit, the erasing prevention voltage output means includes a first inverter that receives the voltage of the third node and inverts it and outputs it, and a second inverter that receives and inverts the output voltage of the first inverter. It includes an inverter.

In a preferred embodiment of the circuit, the voltage level shifting unit comprises a ground terminal, a control signal input terminal to which the control signal is applied, a negative voltage terminal to which the negative voltage is applied, a fourth node, and a gate to the ground. A sixth P-type MOS transistor connected to a terminal, a source connected to the control signal input terminal, and a drain connected to the fourth node; a fifth node connected to an output terminal of the voltage level shift circuit; A seventh P-type MOS transistor connected to an output terminal of a second inverter, a drain connected to the fourth node, a gate connected to the fifth node, a source connected to the negative voltage terminal, and a drain connected to the fourth node; A fifth N-type MOS transistor connected with the gate and the fifth node, and a source connected to an output terminal of the second inverter. An eighth P-type MOS transistor connected with a drain connected with the fifth node and a gate connected with the fourth node, a source connected with the negative voltage terminal, a drain connected with the fifth node, and a gate connected with the fifth node And a sixth N-type MOS transistor connected to the four nodes.

According to such a circuit, a predetermined level of anti-erasing voltage is generated at a negative voltage of a predetermined level irrespective of the change of the power supply voltage.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3 to 4. In Figs. 3 to 4, the same reference numerals are given to the components having the same functions as the components shown in Figs.

3 is a circuit diagram illustrating a voltage level shift circuit according to an exemplary embodiment of the present invention. As shown in FIG. 3, the voltage level shift circuit includes a first power supply terminal 1 to which the ground voltage VSS is applied, a second power supply terminal 2 to which the power supply voltage VCC is applied, and a negative voltage Vneg. The 3rd power supply terminal 3 to which this is applied is provided. The third power supply terminal 3 is an output terminal of the external negative voltage generation circuit 100 generating an erase voltage of -10V.

Referring to FIG. 3, the voltage level shift circuit of the present invention includes a voltage detector 200 and a voltage level shifter 300. The voltage detector 200 receives the power supply voltage VCC and the negative voltage Vneg, detects a negative voltage Vneg of a predetermined level, and generates an erase protection voltage VH of 0V. The voltage level shifting unit 300 receives the negative voltage Vneg of the predetermined erasing voltage level and the erasing prevention voltage VH in response to the predetermined control signal VS applied from the address predecoder. One of (Vneg) and the erasing prevention voltage (VH) is selectively output.

The voltage detector 200 includes a first detection circuit 10, a second detection circuit 20, a third detection circuit 30, and an erase protection voltage output circuit 40.

The first detection circuit 10 includes a first P-type MOS transistor 201, a second P-type MOS transistor 202, a third P-type MOS transistor 203, and a first N-type MOS transistor 204. Consists of. The first P-type MOS transistor 201, the second P-type MOS transistor 202, and the third P-type MOS transistor 203 are P-type MOS diodes each having a gate and a drain coupled thereto. Each channel is connected in series between (1) and the first node N1. The sum of the threshold voltages of the first, second, and third P-type MOS transistors 201, 202, and 203 is 5V. The first N-type MOS transistor 204 has a gate connected to the first power terminal 1 and connected in series between the third power terminal 3 and the first node N1 to have a current path.

The second detection circuit 20 includes a second N-type MOS transistor 205, a fourth P-type MOS transistor 206, and a third N-type MOS transistor 207. In the second N-type MOS transistor 205, a drain is connected to the first power supply terminal 1, a gate is connected to the second power supply terminal 2, and a source is connected to the second node N2. In the fourth P-type MOS transistor 206, a source is connected to the source of the second N-type MOS transistor 205, and a gate and a drain are coupled to serve as a resistor together with the second N-type MOS transistor 205. . The third N-type MOS transistor 207 has a drain connected to the drain of the fourth P-type MOS transistor 206, a gate connected to the first node N1, and a source connected to the third power supply terminal 3. Is connected to.

The third detection circuit 30 includes a fifth P-type MOS transistor 208 and a fourth N-type MOS transistor 209. The fifth P-type MOS transistor 208 has a gate connected to the first power supply terminal 1, a source connected to the second power supply terminal 2, and a drain connected to the third node N3. The fourth N-type transistor 209 has a gate connected to the first power supply terminal 1, a source connected to the second node N2, and a drain connected to the third node N3.

The erasing prevention voltage output circuit 40 includes a first inverter 210 and a second inverter 211. The first inverter 210 receives the voltage of the third node N3 and inverts and outputs the voltage. The second inverter 211 receives the output voltage of the first inverter 210 and inverts the output voltage.

The voltage level shifting unit 300 includes a sixth P-type MOS transistor 113, a seventh P-type MOS transistor 114, a fifth N-type MOS transistor 115, an eighth P-type MOS transistor 116, and The sixth N-type MOS transistor 117 is formed. The sixth P-type MOS transistor 113 has a gate connected to the first power supply terminal 1, and applies a control signal VS from an address predecoder to the fourth node N4. The seventh P-type MOS transistor 114 has a source connected to the output terminal of the second inverter 111, a drain connected to the fourth node N4, and a gate connected to the fifth node N5. The fifth N-type MOS transistor 115 has a source connected to the third power supply terminal 3, a drain connected to the fourth node N4, and a gate connected to the fifth node N5. The eighth P-type transistor 116 has a source connected to an output terminal of the second inverter 111, a gate connected to the fourth node N4, and a drain connected to the fifth node N5. . The sixth N-type transistor 117 has a source connected to the third power supply terminal 3, a drain connected to the fifth node N5, and a gate connected to the fourth node N4.

According to such a circuit, the erasing prevention voltage VH is generated without a delay at the detection of the negative voltage Vneg of a predetermined level irrespective of the change of the power supply voltage VCC.

4 is an operation timing diagram according to an embodiment of the present invention having the above-described configuration.

3 to 4, first, a predetermined control signal VS is applied from the address predecoder to the control signal input terminal 112 so that the fourth node N4 may be applied. Is latched in. The level of negative voltage Vneg starts to fall from 0V to -10V. In an initial state, that is, in a period in which the negative voltage Vneg level does not reach about -5V, which is the sum of the threshold voltage values of the first, second, and third P-type MOS transistors 201, 202, and 203, The voltage of the first node N1 falls with the negative voltage Vneg. Accordingly, the third N-type MOS transistor 207 is maintained turned off, and the voltage level of the second node N2 is maintained at ground.

When the negative voltage Vneg reaches -5V, which is the sum of the threshold voltage values of the first, second, and third P-type MOS transistors 201, 202, and 203, even if the negative voltage Vneg continues to fall, The voltage level of one node N1 is maintained at about -5V. Accordingly, as the third N-type MOS transistor 207 is turned on, the voltage level of the second node N2 rapidly changes from the ground to the negative level. Then, the fourth N-type MOS transistor 209 is turned on so that the voltage level of the third node N3 is rapidly changed from the power supply voltage level VCC to a predetermined negative level. At this time, the voltage of the third node N3 is changed to 0V erasing prevention voltage VH through the first inverter 210 and the second inverter 211 and supplied to the voltage level shifting unit 300. On the other hand, the negative voltage Vneg of the third power supply terminal 3 is supplied to the voltage level shifting unit 300 while descending to −10 V, which is the erase voltage level.

According to the level of the control signal VS latched to the fourth node N4 of the voltage level shifting unit 300, one of the erasing prevention voltage VH and the negative voltage Vneg, which is the erasing voltage, is selected and the fifth node. It is output to the column decoder through N5 and output terminal 118. That is, when the control signal VS is at the high level, the negative voltage Vneg, which is the erase voltage, is output to the column decoder, and when the control signal VS is at the low level, the anti-erasing voltage VH is output to the column decoder. do.

In this manner, when the negative voltage Vneg of −5 V is detected by the first detection circuit 10, the voltage of the second node N2 rapidly increases as the third N-type MOS transistor 207 is turned on. The negative drop causes the third detection circuit 30 to be insensitive to the level of the power supply voltage VCC and the voltage of the third node N3 to drop rapidly to a low level. Therefore, when negative voltage Vneg of -5V is detected, the output voltage of the second inverter 211 goes from the power supply voltage VCC level to the 0V erasing prevention voltage VH level without a delay caused by the change in the power supply voltage VCC. Will change. Thus, the factor of applying high voltage in the voltage level moving part 300 is eliminated.

Referring to FIG. 4, regardless of whether the power supply voltage VCC is applied at 2.5V or 3.5V, the anti-erasing voltage VH of 0V is generated when the negative voltage Vneg is about -5V. . Therefore, even when the power supply voltage VCC is applied at 5V, the maximum voltage across each of the eighth P-type MOS transistor 116 and the sixth N-type MOS transistor 117 is maintained below 10V.

According to the present invention, the erasure prevention voltage generation of the voltage detector is performed without a delay at the negative voltage Vneg of the predetermined level irrespective of the change of the power supply voltage VCC, thereby preventing the high voltage from being applied to the voltage level shift circuit. have. Thus, in the design of the voltage level shift circuit, it is possible to suppress the use of the high breakdown voltage transistor to reduce the layout area of the voltage level shift circuit.

Claims (13)

In the voltage level shift circuit of a semiconductor device, A voltage detector 200 configured to receive a power supply voltage VCC and a negative voltage Vneg from the outside to generate an anti-erasing voltage VH of a predetermined level; An erase voltage of a predetermined level is applied in response to the negative voltage Vneg applied from the outside and an erase protection voltage VH of a predetermined level from the voltage detector 200 in response to a predetermined control signal VS applied from the outside. And a voltage level shifter 300 for selectively outputting one of the negative voltage Vneg and the anti-erasing voltage VH corresponding to the predetermined voltage, and detecting the negative voltage Vneg of a predetermined level. A voltage level shift circuit of a semiconductor memory device, characterized by generating an erase protection voltage (VH). The method of claim 1, The voltage detector 200 may include a ground terminal 1; A power supply voltage terminal 2 to which the power supply voltage VCC is applied; A negative voltage terminal 3 to which the negative voltage Vneg is applied; A first node N1; First detection means (10) connected to the ground terminal (1) and the negative voltage terminal (3) for detecting a negative voltage (Vneg) of a predetermined level and applying it to the first node (N1); A second node N2; It is connected to the ground terminal 1 and is supplied with the power supply voltage VCC and the negative voltage Vneg to the second node N2 in response to the voltage of the first node N1. Second detection means (20) for applying a detection voltage; A third node N3; Third detection means connected to the ground terminal 1 to receive the power supply voltage VCC and apply a detection voltage having a predetermined level to the third node N3 in response to a voltage of the second node N2. 30; And an erase protection voltage output means 40 for outputting the erase protection voltage VH at a predetermined level in response to the voltage of the third node N3 at a predetermined level. Circuit. The method of claim 2, The first detection means 10 has a first N-type Morse whose gate is connected to the ground terminal 1 and is connected in series between the negative voltage terminal 3 and the first node N1 to form a current path. A transistor 204; A first P-type MOS transistor (201) having a source connected to the ground terminal (1) and a gate and a drain connected thereto; A second P-type MOS transistor (202) having a source connected to the drain of the first P-type MOS transistor (201) and having a gate and a drain connected thereto; And a third P-type MOS transistor 203 having a source connected to the drain of the second P-type MOS transistor 202 and a gate and a drain connected to the first node N1. Voltage level shift circuit. The method of claim 2, The second detection means 20 has a second N-type MOS transistor having a drain connected to the ground terminal 1, a source connected to the second node N2, and a gate connected to the power supply voltage terminal 2. 205; A fourth P-type MOS transistor (206) having a source connected to the second node (N2) and a gate and a drain connected thereto; A third N-type MOS transistor 207 having a drain connected to the drain of the fourth P-type MOS transistor 206, a source connected to the negative voltage terminal 3, and a gate connected to the first node N1. The voltage level shift circuit of the semiconductor memory device comprising a. The method of claim 2, The third detecting means 30 includes a fifth P-type MOS transistor having a source connected to the power supply voltage terminal 2, a gate connected to the ground terminal 1, and a drain connected to the third node N3. 208; And a fourth N-type MOS transistor 209 having a drain connected to the third node N3, a gate connected to the ground terminal 1, and a source connected to the second node N2. A voltage level shift circuit of a semiconductor memory device. The method of claim 2, The erasing prevention voltage output means (40) includes a first inverter (210) for receiving the voltage of the third node (N3) and inverting the same; And a second inverter (211) for receiving the output voltage of the first inverter (210), inverting the output voltage, and outputting the inverted output voltage. The method of claim 1, The voltage level shifting unit 300 includes a ground terminal 1; A control signal input terminal 112 to which the control signal VS is applied; A negative voltage terminal 3 to which the negative voltage Vneg is applied; A fourth node N4; A sixth P-type MOS transistor (113) having a gate connected to the ground terminal (1), a source connected to the control signal input terminal (112), and a drain connected to the fourth node (N4); A fifth node (N5) connected with the output terminal (118) of the voltage level shift circuit; A seventh P-type MOS transistor (114) having a source connected to an output terminal of the second inverter (211), a drain connected to the fourth node (N4), and a gate connected to the fifth node (N5); A fifth N-type MOS transistor (115) having a source connected to the negative voltage terminal (3), a drain connected to the fourth node (N4), and a gate connected to the fifth node (N5); An eighth P-type MOS transistor (116) having a source connected to an output terminal of the second inverter (211), a drain connected to the fifth node (N5), and a gate connected to the fourth node (N4); And a sixth N-type MOS transistor 117 having a source connected to the negative voltage terminal 3, a drain connected to the fifth node N5, and a gate connected to the fourth node N4. A voltage level shift circuit of a semiconductor memory device. In the voltage level shift circuit of a semiconductor device, A ground terminal 1; A power supply voltage terminal 2 to which a power supply voltage VCC is applied; A negative voltage terminal 3 to which a negative voltage Vneg is applied; A first node N1; First detection means (10) connected to the ground terminal (1) and the negative voltage terminal (3) for detecting a negative voltage (Vneg) of a predetermined level and applying it to the first node (N1); A second node N2; It is connected to the ground terminal 1 and is supplied with the power supply voltage VCC and the negative voltage Vneg to the second node N2 in response to the voltage of the first node N1. Second detection means (20) for applying a detection voltage; A third node N3; Third detection means connected to the ground terminal 1 to receive the power supply voltage VCC and apply a detection voltage having a predetermined level to the third node N3 in response to a voltage of the second node N2. 30; A voltage detector (200) including an erase protection voltage output means (40) for outputting an erase protection voltage (VH) of a predetermined level in response to the voltage of the third node (N3) at a predetermined level; The negative voltage Vneg of the erasing voltage level is applied from the negative voltage terminal 3, and the predetermined anti-erasing voltage VH is applied from the erasing prevention voltage output means 40. In response to a control signal VS, a voltage level shifting unit 300 for selectively outputting one of the negative voltage Vneg and the anti-erasing voltage VH, to the first detection means 10 In the section where the negative voltage Vneg of the predetermined level is not detected, the output voltage of the anti-erasing voltage output means 40 is the power supply voltage VCC level, and the predetermined detection means 10 determines the predetermined voltage. In the period in which the negative voltage Vneg of the level is detected, the output voltage of the erasure prevention voltage output means 40 becomes a predetermined erasure prevention voltage level. Level shift circuit. The method of claim 8, The first detection means 10 has a first N-type Morse whose gate is connected to the ground terminal 1 and is connected in series between the negative voltage terminal 3 and the first node N1 to form a current path. A transistor 204; A first P-type MOS transistor (201) having a source connected to the ground terminal (1) and a gate and a drain connected thereto; A second P-type MOS transistor (202) having a source connected to the drain of the first P-type MOS transistor (201) and having a gate and a drain connected thereto; And a third P-type MOS transistor 203 having a source connected to the drain of the second P-type MOS transistor 202 and a gate and a drain connected to the first node N1. Voltage level shift circuit. The method of claim 8, The second detection means 20 has a second N-type MOS transistor having a drain connected to the ground terminal 1, a source connected to the second node N2, and a gate connected to the power supply voltage terminal 2. 205; A fourth P-type MOS transistor (206) having a source connected to the second node (N2) and a gate and a drain connected thereto; A third N-type MOS transistor 207 having a drain connected to the drain of the fourth P-type MOS transistor 206, a source connected to the negative voltage terminal 3, and a gate connected to the first node N1. The voltage level shift circuit of the semiconductor memory device comprising a. The method of claim 8, The third detecting means 30 includes a fifth P-type MOS transistor having a source connected to the power supply voltage terminal 2, a gate connected to the ground terminal 1, and a drain connected to the third node N3. 208; And a fourth N-type MOS transistor 209 having a drain connected to the third node N3, a gate connected to the ground terminal 1, and a source connected to the second node N2. A voltage level shift circuit of a semiconductor memory device. The method of claim 8, The erasing prevention voltage output means (40) includes a first inverter (210) for receiving the voltage of the third node (N3) and inverting the same; And a second inverter (211) for receiving the output voltage of the first inverter (210), inverting the output voltage, and outputting the inverted output voltage. The method of claim 8, The voltage level shifting unit 300 includes a ground terminal 1; A control signal input terminal 112 to which the control signal VS is applied; A negative voltage terminal 3 to which the negative voltage Vneg is applied; A fourth node N4; A sixth P-type MOS transistor (113) having a gate connected to the ground terminal (1), a source connected to the control signal input terminal (112), and a drain connected to the fourth node (N4); A fifth node (N5) connected with the output terminal (118) of the voltage level shift circuit; A seventh P-type MOS transistor (114) having a source connected to an output terminal of the second inverter (211), a drain connected to the fourth node (N4), and a gate connected to the fifth node (N5); A fifth N-type MOS transistor (115) having a source connected to the negative voltage terminal (3), a drain connected to the fourth node (N4), and a gate connected to the fifth node (N5); An eighth P-type MOS transistor (116) having a source connected to an output terminal of the second inverter (211), a drain connected to the fifth node (N5), and a gate connected to the fourth node (N4); And a sixth N-type MOS transistor 117 having a source connected to the negative voltage terminal 3, a drain connected to the fifth node N5, and a gate connected to the fourth node N4. A voltage level shift circuit of a semiconductor memory device.

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