KR100239709B1 - Method of manufacturing a contact plug - Google Patents
Method of manufacturing a contact plug Download PDFInfo
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- KR100239709B1 KR100239709B1 KR1019960059268A KR19960059268A KR100239709B1 KR 100239709 B1 KR100239709 B1 KR 100239709B1 KR 1019960059268 A KR1019960059268 A KR 1019960059268A KR 19960059268 A KR19960059268 A KR 19960059268A KR 100239709 B1 KR100239709 B1 KR 100239709B1
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- resistant metal
- gas
- etching
- contact hole
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- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000010410 layer Substances 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 claims abstract description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 22
- 229910052721 tungsten Inorganic materials 0.000 claims description 19
- 239000010937 tungsten Substances 0.000 claims description 19
- 238000001514 detection method Methods 0.000 claims description 2
- 239000003870 refractory metal Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 공정이 간단하게 구성되면서도 그 공정의 순수도가 유지될 수 있고, 원가 절감 및 관리 측면에서도 유리하도록 한 콘택플러그를 형성하기 위한 내열금속 에치백 공정에 관한 것으로, 하부에 형성된 제1전도층의 일부영역을 개방시키는 콘택홀에 가득 채워짐과 아울러 그 콘택홀의 주위에 형성된 층간절연층 위에 소정의 두께로 증착된 내열금속(Refractory metal)을 마스크 없이 식각하여 그 내열금속이 상기 콘택홀의 내부에만 남도록 하는 내열금속 플러그 형성공정에 있어서, 상기내열금속을 마스크 없이 식각하는 공정이 SF6가스를 공정가스로 사용하는 헬리콘 식각 시스템(HELICON ETCH SYSTEM)에서 이루어지는 것을 특징으로 한다. 따라서 상기와 같은 본발명은 내열금속에 대한 에치백공정이 3단계로 구성된 종래 기술에 비해서 공정이 단순하게 되는 효과와 함께 공정가스의 종류가 적어 순수도가 향상되는 효과와, 식각균일도도 약 3% 정도가 되는 효과가 발생한다.The present invention relates to a heat-resistant metal etchback process for forming a contact plug which allows the process to be simply configured but maintains the purity of the process and is advantageous in terms of cost reduction and management. In addition to filling the contact hole that opens a part of the layer, a resistive metal deposited to a predetermined thickness on the interlayer insulating layer formed around the contact hole is etched without a mask so that the heat-resistant metal is formed only inside the contact hole. In the process of forming a heat-resistant metal plug to remain, the process of etching the heat-resistant metal without a mask is performed in a helicon etching system using a SF 6 gas as a process gas. Therefore, the present invention as described above has the effect of simplifying the process compared to the prior art consisting of three steps of the etch back process for the heat-resistant metal, the effect of improving the purity of the less types of process gas, the degree of etching uniformity Effect of about% occurs.
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 제1전도층과 제2전도층을 접속(Contack)시키기 위하여 그 제1전도층과 제2전도층 사이의 층간절연층에 형성된 콘택홀에 콘택플러그(CONTACT PLUG)를 형성하기 위한 내열 금속 에치백 공정(REFRACTORY METAL ETCHBACK PROCESS)에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a contact plug in a contact hole formed in an interlayer insulating layer between a first conductive layer and a second conductive layer in order to connect the first conductive layer and the second conductive layer. RELATED METAL ETCHBACK PROCESS FOR FORMING (CONTACT PLUG).
반도체소자를 형성하는 공정에 있어서, 소정의 층간절연층을 사이에 두고 그의 위와 아래에 각각 형성되는 소정의 제1전도층과 제2전도층을 접속하기 위한 일반적인 콘택플러그 형성공정은,제1전도층 위에 층간절연층을 형성한 후, 그 층간절연층에 콘택홀을 형성하는 단계와, 그 위에 제2전도층을 형성하는 단계로 이루어진다. 이와 같은 콘택플러그 형성공정의 일실시예에 대해서 첨부된 도1a-도1c를 참조하여 설명하면 다음과 같다.In the process of forming a semiconductor device, a general contact plug forming process for connecting a predetermined first conductive layer and a second conductive layer formed above and below a predetermined interlayer insulating layer between the first conductive layer is a first conductive layer. After forming the interlayer insulating layer on the layer, forming a contact hole in the interlayer insulating layer, and forming a second conductive layer thereon. An embodiment of such a contact plug forming process will be described below with reference to FIGS. 1A-1C.
우선, 도1a에 도시된 바와 같이 소정의 제1전도층(11)이 형성된 실리콘기판(10)위에 층간절연층(20)을 증착한 후, 그를 패터닝하여 상기 제1 전도층(11)의 일부영역이 노출되는 콘택홀(30)을 형성한다.First, as shown in FIG. 1A, an interlayer insulating layer 20 is deposited on a silicon substrate 10 on which a predetermined first conductive layer 11 is formed, and then patterned to form part of the first conductive layer 11. The contact hole 30 exposing the region is formed.
이후, 상기 결과물의 전면에 제1내열금속(40)을 얇게 증착한 후, 그 위에 상기 콘택홀(30)의 내부(31)가 가득 채워질 때까지 제2내열금속(50)을 증착한다. 이때 상기 제1내열금속층은 Ti, Tiw, TiN과 같이 상기 제1전도층(11)에 대한 점착성이 우수한 내열금속으로 형성하고, 제2내열금속층은 텅스텐(W)으로 형성한다.Thereafter, the first heat resistant metal 40 is thinly deposited on the entire surface of the resultant, and then the second heat resistant metal 50 is deposited until the inside 31 of the contact hole 30 is filled thereon. In this case, the first heat resistant metal layer is formed of a heat resistant metal having excellent adhesion to the first conductive layer 11, such as Ti, Tiw, TiN, and the second heat resistant metal layer is formed of tungsten (W).
이어, 도1c에 도시된 바와 같이 상기 텅스텐층(50)과 제1내열금속층(40)을 연속적으로 에치백(Etchback)하여 그 텅스텐층(50)과 제1내열금속층(40)이 상기 콘택홀(30)에만 남아 있도록 한다.Subsequently, as illustrated in FIG. 1C, the tungsten layer 50 and the first heat resistant metal layer 40 are continuously etched back, and the tungsten layer 50 and the first heat resistant metal layer 40 are contact holes. Only remain at (30).
여기서, 상기 텅스텐층(50)과 제1내열금속층(40)을 에치백하는 종래 기술에 대해서 첨부한 도2 를 참조하여 설명하면 다음과 같다.Herein, a conventional technique for etching back the tungsten layer 50 and the first heat resistant metal layer 40 will be described with reference to FIG. 2.
도2에 도시된 도면은 도1b와 같이 소자의 전면에 증착된 텅스텐층(50)과 제1내열금속층(40)에 대한 에치백 공정이 3단계로 구성되었음을 보여주고 있는데, 제1단계는 SF6와, O2, He을 혼합한 가스로 텅스텐층(50)의 대부분을 균일하게 식각하는 단계로서, SF6와, O2, He의 유량(Flow)은 각각 160, 20, 150[SCCM]으로 설정하고, 압력은 700[mTorr], 파워(Power)는 400[W], 전극의 간격은 0.7[cm]로 한 상태에서 수행되고, 제2단계는 SF6와, Cl2, He을 혼합한 가스로 제1금속층(40)이 드러날 때까지 텅스텐(50)을 식각하는 단계로서, SF6와, Cl2, He의 유량은 각각 130, 70, 200[SCCM], 압력은 700[mTorr], 파워(Power)는 250[W], 전극의 간격은 0.7[cm]로 한 상태에서 수행되며, 제3단계는 Cl2와 He을 혼합한 가스로 잔류 텅스텐(50)과 제1금속층(40)이 전부 식각될 때까지 텅스텐(50)을 식각하는 단계로서, Cl2와 He의 유량은 각각 130,50[SCCM], 압력은 400[mTorr], 파워(Power)는 200[W], 전극의 간격은 0.55[cm]로 한 상태에서 수행된다. 이때, 상기 제2단계와 제3단계는 각각 식각종말점(END POINT DETECT)을 검출하면서 수행되는 단계로서, 제2단계는 제1금속층이 드러날 때 발생되는 빛을 검출하고 제3단계는 층간절연층이 드러날 때 발생되는 빛을 검출함으로써 식각종말점을 판단한다.FIG. 2 shows that the etch back process for the tungsten layer 50 and the first heat resistant metal layer 40 deposited on the front surface of the device as shown in FIG. 1B is composed of three steps. and 6, O 2, to a gas mixture of He comprising the steps of: uniformly etched most of the tungsten layer (50), SF 6 and, O 2, flow rate (flow) of He are respectively 160, 20, 150 [SCCM] The pressure is set to 700 [mTorr], the power is 400 [W], and the electrode is 0.7 [cm]. The second step is to mix SF 6 with Cl 2 and He. Etching tungsten (50) until the first metal layer (40) is exposed with a gas, and the flow rates of SF 6 , Cl 2 , and He are 130, 70, 200 [SCCM], and the pressure is 700 [mTorr]. , Power is 250 [W], the electrode spacing is 0.7 [cm], the third step is a gas mixed with Cl 2 and He is the residual tungsten (50) and the first metal layer (40) Etching tungsten (50) until all are etched, The flow rate of Cl 2 and He is 130,50 [SCCM], the pressure is 400 [mTorr], the power is 200 [W], and the electrode spacing is 0.55 [cm]. In this case, the second step and the third step are performed while detecting the END DETECT, respectively, the second step is to detect the light generated when the first metal layer is exposed, and the third step is the interlayer insulating layer The etching end point is determined by detecting light generated when the light is revealed.
그러나, 상기와 같이 제1내열금속과 텅스텐을 에치백하여 콘택플러그를 형성하는 내열금속 에치백 공정이 3단계로 구분된 종래 기술은, 공정이 복잡할 뿐만 아니라 많은 종류의 공정가스가 사용됨으로써 원하지 않는 부산물(Reaction product)이 발생하게 되는 문제점이 있었다. 그리고, 제2단계와 제3단계에서는 식각종말점(EPD)을 검출하기 위해 Cl2가스를 투입하고, 제1단계에서는 O2가스를 식각원으로 사용함으로써, 식각과 관련이 업는 불필요한 가스를 주입하게 되는 단점과 상기 O2가스가 챔버안에 있는 폴리머(Polymer) 등을 식각하게 됨에 따라 웨이퍼를 오염시키게 되는문제점이 있었다.However, the conventional technique in which the heat-resistant metal etchback process of etching back the first heat-resistant metal and tungsten to form a contact plug as described above is divided into three stages. There was a problem that does not occur by-products (Reaction product). In the second and third steps, Cl 2 gas is added to detect an etch endpoint (EPD), and in the first step, O 2 gas is used as an etching source, thereby injecting unnecessary gas related to etching. In addition, the O 2 gas has a problem of contaminating the wafer as the O 2 gas is etched from the polymer (Polymer).
이에 본 발명은 상기와 같은 문제점을 해결하기 위하여 창안한 것으로, 공정이 단순하면서도 그 공정의 순수도가 유지될 수 있고, 원가 절가 및 관리 측면에서도 효과를 극대화 시킬 수 있는 콘택플러그를 형성하기 위한 내열금속 에치백 공정을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, the process is simple, the purity of the process can be maintained, heat resistance for forming a contact plug that can maximize the effect in terms of cost reduction and management The purpose is to provide a metal etch back process.
도1a-도1c는 일반적인 내열금속 콘택플러그를 형성공정을 나타낸 공정 단면도.1A to 1C are cross-sectional views illustrating a process of forming a general heat resistant metal contact plug.
도2는 종래 기술에 따른 내열금속 에치백 공정을 나타낸 블럭도.Figure 2 is a block diagram showing a heat-resistant metal etch back process according to the prior art.
도3은 본 발명에 따른 내열금속 에치백 공정을 나타낸 블럭도.Figure 3 is a block diagram showing a heat-resistant metal etch back process according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 실리콘기판 11 : 제1 전도층10 silicon substrate 11: first conductive layer
20 : 층간절연층 30 : 콘택홀20: interlayer insulating layer 30: contact hole
40,41 : 제1내열금속층 50,51 : 텅스텐(W)층40,41: First heat resistant metal layer 50,51: Tungsten (W) layer
상기 목적을 달성하기 위한 본 발명은, 하부에 형성된 제1전도층의 일부영역을 개방시키는 콘택홀에 가득 채워짐과 아울러 그 콘택홀의 주위에 형성된 층간절연층 위에 소정의 두께로 증착된 내열금속(Refractory metal)을 마스크 없이 식각하여 그 내열금속이 상기 콘택홀의 내부에만 남도록 하는 내열금속 플러그 형성공정에 있어서, 상기 내열금속을 마스크 없이 식각하는 공정이 SF6가스를 공정가스로 사용하는 헬리콘 식각 시스템(HELICON ETCH SYSTEM)에서 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is filled with a contact hole for opening a partial region of the first conductive layer formed on the bottom and heat-resistant metal deposited to a predetermined thickness on the interlayer insulating layer formed around the contact hole (Refractory In the heat-resistant metal plug forming process in which the heat-resistant metal is etched without a mask so that the heat-resistant metal remains only inside the contact hole, the process of etching the heat-resistant metal without a mask uses a helicon etching system using SF 6 gas as a process gas. HELICON ETCH SYSTEM).
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도1a-도1c는 제1전도층과 제2전도층을 접속시키기 위한 텅스텐 콘택플러그 형성 공정을 나타낸 공정 단면도로서, 앞에서 설명한 바와 같이 제1전도층(11)이 형성된 실리콘기판(10) 위에 층간절연층(20)을 증착한 후, 그를 패터닝하여 상기 제1전도층(11)의 일부영역이 노출되는 콘택홀(30)을 형성하는 단계(도1a)와; 상기 결과물의 전면에 상기 제1전도층(11)에 대한 점착성이 우수한 제1내열금속(Ti,TiW, TiN)(40)을 얇게 증착한 후, 그 위에 상기 콘택홀(30)의 내부(31)가 가득 채워질 때까지 제2내열금속(W)(50)을 증착하는 단계(도1b)와; 상기 텅스텐층(50)과 제1내열금속층(40)을 마스크 없이 에치백(Etchback)하여 그 텅스텐층(50)과 제1내열금속층(40)이 상기 콘택홀(30)에만 남아 있도록 하는 단계(도1c)로 구성된다.1A to 1C are cross-sectional views illustrating a process of forming a tungsten contact plug for connecting a first conductive layer and a second conductive layer. As described above, an interlayer is formed on a silicon substrate 10 on which a first conductive layer 11 is formed. Depositing the insulating layer 20 and patterning the insulating layer 20 to form a contact hole 30 exposing a portion of the first conductive layer 11 (FIG. 1A); After depositing a thin layer of the first heat-resistant metal (Ti, TiW, TiN) 40 excellent in adhesion to the first conductive layer 11 on the entire surface of the resultant, the interior of the contact hole 30 thereon (31) Depositing the second heat-resistant metal (W) 50 until () is filled (FIG. 1B); Etching the tungsten layer 50 and the first heat resistant metal layer 40 without a mask so that the tungsten layer 50 and the first heat resistant metal layer 40 remain only in the contact hole 30 ( 1c).
이와 같은 텅스텐 콘택플러그 형성공정에 있어서, 상기 텅스텐층(50)과 제1내열금속층(40)을 마스크 없이 에치백하는 공정에 대한 본 발명의 바람직한 실시예는, 도 3에 도시된 바와 같이 SF6가스를 공정가스로 하는 1번의 에치백(제1단계)으로 이루어질 수 있는데, 그럴 경우 상기 에치백 공정은 헬리콘 식각 시스템(HELICON ETCH SYSTEM)에서 이루어지는 것이 바람직하다. 이때, 상기와 같이 공정가스를 SF6 가스로 하는 헬리콘 식각 시스템에서의 텅스텐(50)과 제1내열금속(40)에 대한 에치백 공정은, 압력을 약 5-10[mTorr] 정도로 하고, 소스 파워(SOURCE POWER)를 약 2000[W], 바이어스 파워(BIAS POWER)를 약 30[W] 정도로 하는 조건하에서 이루어질 수 있는데, 식각종말점(EPD)의 검출은 상기 제1내열금속(40)이 전부 식각됨으로써 그 표면이 드러나게 되는 하부의 층간절연층(20)으로부터 그가 식각될 때 방출하게 되는 400-500[nm]파장의 빛을 검출(DETECT)함으로써 달성한다.In such a tungsten contact plug forming process, a preferred embodiment of the present invention for the process of etching back the tungsten layer 50 and the first heat-resistant metal layer 40 without a mask, SF 6 as shown in FIG. It may be made of a single etchback (first step) using the gas as a process gas, in which case the etchback process is preferably performed in a helicon etching system (HELICON ETCH SYSTEM). At this time, the etchback process for the tungsten 50 and the first heat-resistant metal 40 in the helicon etching system using the process gas as SF6 gas as described above, the pressure is about 5-10 [mTorr], the source Under the condition that the power (SOURCE POWER) is about 2000 [W] and the bias power (BIAS POWER) is about 30 [W], the detection of the etch end point (EPD) is performed by all of the first heat resistant metal 40. This is achieved by detecting 400-500 [nm] wavelengths of light that will be emitted when it is etched from the underlying interlayer insulating layer 20 where the surface is exposed by etching.
상술한 바와 같이, 콘택플러그를 형성하기 위한 내열금속에 대한 에치백공정이 SF6가스를 공정가스로 하고 헬리콘 식각 시스템을 식각장비로 하는 단 1 번의 공정으로 이루어지는 본 발명은, 종래 기술에 비해서 공정이 단순하게 되면서도 그 공정의 순수도가 유지될 수 있고, 원가 절감 및 관리 측면에서도 유리하게 되는 효과가 있다. 그리고 식각균일도 측면에서도 약 3% 정도로 유지되는 효과가 있다.As described above, the present invention, in which the etchback process for the heat-resistant metal for forming the contact plug is performed in one step using SF 6 gas as the process gas and the helicon etching system as the etching equipment, is compared with the prior art. While the process is simplified, the purity of the process can be maintained and advantageous in terms of cost reduction and management. In addition, the etching uniformity is also maintained at about 3%.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960059268A KR100239709B1 (en) | 1996-11-29 | 1996-11-29 | Method of manufacturing a contact plug |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960059268A KR100239709B1 (en) | 1996-11-29 | 1996-11-29 | Method of manufacturing a contact plug |
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| Publication Number | Publication Date |
|---|---|
| KR19980040126A KR19980040126A (en) | 1998-08-17 |
| KR100239709B1 true KR100239709B1 (en) | 2000-01-15 |
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| KR1019960059268A KR100239709B1 (en) | 1996-11-29 | 1996-11-29 | Method of manufacturing a contact plug |
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| KR (1) | KR100239709B1 (en) |
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