KR100239443B1 - Digital output camera system - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital output camera system that simplifies the configuration for digital output between a camera unit employing a solid state imaging device (CCD) and a data receiving unit. Operation clocks Tclk1 and Tclk2 are output to synchronize the clock synchronization between the camera unit and the data receiver based on the data reception clock based on the reference clock signal Cclk and image data, and are synchronized to the pixel unit clock Pclk1. A data transmission control unit for outputting the data, a timing generator for outputting a timing signal Pclk2 for signal processing by the operation clock Tclk1, and an analog output to an image sensor and an image sensor operating according to the timing signal Analog / digital converter to convert signals into digital, converted by analog / digital converter A luminance / color signal processor configured to receive a digital signal and output image data synchronized with a pixel unit clock, and to transmit data control information and a data reception clock to the data transmission controller, and to receive data from the data transmission controller. It is configured to include a data receiving unit.

Description

Digital output camera system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital output camera, and more particularly, to a digital output camera system which simplifies the configuration for digital output between a camera unit and a data receiving unit of a solid state imaging device (CCD).

Hereinafter, a conventional digital output camera system will be described with reference to the accompanying drawings.

1 is a configuration diagram of a conventional digital output camera, and FIG. 2 is a relationship diagram of a timing generator and a synchronization signal generator of a conventional digital output camera.

In conventional cameras, the time required to compose one screen (one frame composition time) is changed based on international TV standards such as NTSC (National Television System Committee) and PAL (Phase Alternate Line), which are TV transmission and reception methods. There is no.

For example, in the case of NTSC, one frame composition time is fixed at 1/30 second.

On the other hand, the data transfer control unit for controlling data transfer to the display element 2 such as a personal computer (PC) is a time for configuring one frame according to the hardware performance of the display element 2 as the data receiver or according to the intention of the user. This is different from the camera unit 1.

That is, the basic clocks used for data transmission and reception between the camera unit 1 and the data transmission unit are completely separate. Thus, in order to compensate for the difference in the operation timing of the camera unit 1 and the operation timing in the processing speed of the data transmission unit, a frame memory unit 8 used as an intermediate buffer zone was required.

For this reason, the configuration of a conventional digital output camera using the frame memory section 8 is as shown in FIG.

First, the first clock oscillator 3 generating the reference oscillation clock Tclk of the timing generator 4 and the first clock oscillator 3 receive the signal and output a frame start pulse and a memory write control signal. And a timing generator 4 for transmitting a signal for converting an analog signal into a digital signal to the analog / digital converter 6, and an image sensor unit 5 for sensing an external image and sending the signal to the analog / digital converter 6. And a luminance / color signal processor 7 which receives the signal of the analog / digital converter 6 and transmits the data to the frame memory unit 8, and a data transmission control reference clock Cclk. Receiving the data of the frame memory unit 8 according to the clock signal of the second clock oscillator 9 and the second clock oscillator 9 and controlling the data read of the frame memory unit 8. Data transmission control And a display element (2) for transmitting data from the data transmission control section (10) to reproduce the image.

Here, the timing of the reference oscillation clock Tclk of the timing generator 4 and the reference oscillation clock Cclk of the data transmission control unit 10 have independent schemes.

In addition, the master clock (Mclk) of the entire camera unit 1 generally uses two or three divisions of Tclk.

In addition, as shown in FIG. 2, the conventional timing generator 4 and the synchronization signal generator 11 are connected to the synchronization signal generator 11 from the timing generator 4 in order to meet the TV standard such as NTSC or PAL. It operates by receiving the clock (Tclk / 2) divided by two Tclk oscillation clocks.

In addition, the timing generator 4 horizontally drives HD from the synchronization signal generator 11 to the timing generator 4 in order to identify the start of each line, i.e., HD drives horizontally by the number of pixels on a line. And a VD clocked by the timing generator 4 in order to identify the start of each field, that is, a VD clock that repeats the number of lines determined by the TV standard from the synchronization signal generator 11 and operates. .

The BLK generated from the synchronization signal generator is a blanking pulse, and the SYNC is a composite signal for inserting horizontal and vertical signals.

That is, the synchronization signal generator 11 produces a pulse conforming to the TV standard and feeds the reference pulse of all clocks produced by the timing generator by feeding back the reference pulse to the timing generator 4.

However, if there is no need to match the screen standard to the TV standard such as NTSC or PAL, it is not necessary to work hard to synchronize.

The conventional digital output camera system as described above has the following problems.

In the conventional digital output camera system, timing deviation occurs because the operation timing management of the camera unit and the data transmission control unit is performed independently.

In the prior art, there is an inconvenience of using a frame memory unit to overcome this problem, which causes a complicated structure of the camera.

The present invention has been made to solve the above problems, the digital output camera system that can solve the time deviation according to the data reception of the camera unit and the data receiving unit, that is, the display element itself without the configuration of a separate frame memory The purpose is to provide.

1 is a block diagram of a conventional digital output camera

2 is a relationship between a timing generator and a synchronization signal generator of a conventional digital output camera

3 is a block diagram of the present invention digital output camera

4 is a data reception timing diagram of a digital output camera of the present invention.

* Description of the symbols for the main parts of the drawings *

21: camera unit 22: display element

23: timing generator 24: image sensor

25: Analog / Digital Converter

26: luminance / color (Y / C) signal processor 27: clock oscillator

28: data transmission control unit

Tclk1: Timing Generator's Operating Clock

Tclk2: Operation Clock of Timing Generator by Data Enable Signal

Pclk1: Pixel unit clock for data transfer

Pclk2: Pixel Clock Generated from Tclk1

Cclk: reference oscillation clock for data transmission control

DE: data enable signal

The digital output camera system of the present invention for achieving the above object is a camera of a digital output transmission system, receiving a reference clock signal (Cclk) and image data output from the clock oscillator based on the data reception clock camera A data transmission control unit for outputting an operation clock Tclk1 (Tclk2) and outputting data synchronized with the pixel unit clock Pclk1 in order to synchronize the clock synchronization between the unit and the data receiving unit, and a signal by the operation clock Tclk1. A timing generator for outputting a timing signal Pclk2 for processing, an image sensor operated by the timing signal, an analog / digital converter for converting an analog signal output to the image sensor, and a analog / digital converter Luminance for receiving digital signals and outputting image data synchronized with the pixel-by-pixel clock / La and a signal processor, to the data transmission control unit having a receive clock of the control information and data from the data, is characterized in that comprises a data receiver receiving the transmitted data from the data transmission control.

The digital output camera system of the present invention is a general stand-alone camera, that is, an environment of a receiving end such as a personal computer (PC) having a right to receive data by using a unique clock oscillator to break away from a camera implementing a unique signal standard (NTSC or PAL, etc.). To fit in.

That is, it has the concept of the subordinate camera in which the camera part depends on the data receiving part.

The camera system of the present invention is a system in which the determination of the operation clock of the camera unit 21 is dependent on the display element 22, that is, the data transmission control unit by the control information and the data reception clock output from the display element 22. The operation timings of the data processing blocks such as the image sensor unit 24, the analog / digital converter 25, the luminance / color signal processor 26, and the like are determined by the operation clocks Tclk1 and Tclk2 set at 28.

That is, the data processing blocks are operated by the pixel clock Pclk2 generated by the operation clock Tclk1 to output data in pixel clock units.

Such a digital output camera system of the present invention will be described in detail with reference to the accompanying drawings.

3 is a configuration diagram of the digital output camera of the present invention, Figure 4 is a data reception timing diagram of the digital output camera of the present invention.

As shown in FIG. 3, the digital output camera according to the present invention first receives a reference oscillation clock signal Cclk for data transmission control output from the clock oscillator 27 and sets the operation clocks Tclk1 and Tclk2 as timing generators. 23, i.e., the operation clock Tclk1 and Tclk2, which are the system reference, are outputted and synchronized to the pixel unit clock Pclk1 in order to match the clock synchronization between the camera unit and the data receiving unit, that is, the display element 22. A data transmission control unit 28 for outputting the received data, a timing generator 23 for transmitting the clock signal Pclk2 to the analog-to-digital converter 25 according to the operation clock Tclk1 (Tclk2) signals, and a clock; An image sensor 21 that is operated by a signal Pclk2 and senses an external image, and converts an image of the image sensor 24 into a digital signal according to a clock signal Pclk2 of the timing generator 23. Analog / digital conversion 25, a luminance / color signal processor 26 which receives the digitally converted signal and transmits the data to the data transmission control unit 28 in units of Pclk2, and receives the control information and data by the data transmission control unit 28. And a display element 22, such as a personal computer (PC), which sends a clock and also receives data from the data transmission control unit 28 and receives data in Pclk units.

Here, the clock signal Cclk output from the clock oscillator 27 is a data transmission control reference oscillation used to determine the speed of data to be received by the display element 22 such as a personal computer (PC). It is a clock.

The clocks divided by n based on the data transmission control reference oscillation clock Cclk, that is, the operation clocks Tclk1 and Tclk2 transmitted to the timing generator 23, are the reference oscillation clocks Tclk1 and the data enable (Tclk1) of the timing generator. There is a reference clock Tclk2 of the timing generator by the DE: Data Enable signal.

Pclk1 is a unit clock of the pixel, and Pclk2 is a pixel clock generated from Tclk1.

Here, the definition of the n division clock defines Pclk as the speed at which data can be received from the display element 22, and defines a clock speed of 2 or 3 times Pclk as Tclk, and divides it by the speed difference between Cclk and Tclk. Is defined.

For example, if the clock speed of the data transmission controller is 10 MHz and the speed of receiving data from the display device 22 is in units of 1 MHz, then Pclk becomes 1 MHz, and since Tclk is more convenient to calculate than 2 divisions, Tclk becomes 2 MHz.

Therefore, if the data transmission control section divides 5 times on the basis of 10 MHz, there is no time difference in data processing between the data transmission section and the camera section, and thus no intermediate buffer frame memory is required.

For example, when a data delay occurs for a specific time while receiving data from the display element 22, the information is fed back to the data transmission control unit 27 of the camera unit 21. You can delay Tclk by time. As such, when data breaks occur intermittently, a timing signal may be received from the receiver and delayed based on Cclk.

As shown in FIG. 4, the data reception timing diagram showing that the data reception unit composed of the display element 22 and the camera unit 21 can be completely synchronized on a pixel basis is shown in the reference oscillation clock of the timing generator 23. The Tclk1 oscillates by repeating the high signal and the low signal regularly, and makes two cycles of the reference oscillation clock Tclk1 of the timing generator 23 one cycle, that is, having a frequency that is 1/2 times the Tclk1 frequency. There is a unit clock Pclk1 of the pixel Pixel.

In order to synchronize such a signal on a pixel-by-pixel basis, a data enable signal (DE) is received from a display element 22 such as a personal computer (PC) (where the high signal of the data enable signal receives data. A low means a waiting state to receive a signal.) The reference oscillation clock of the timing generator 23 is only a timing clock that receives the enable signal, that is, a high signal of the data enable signal DE. The clock pulses of Tclk1 and the unit clock Pclk1 of the pixel are driven to drive the reference clock Tclk2 of the timing generator by the data enable signal and the clock pulses of Pclk1 generated from Tclk1 to Pclk2.

In this way, a digital enable signal can be applied to achieve complete synchronization on a pixel-by-pixel basis.

The digital output camera system of the present invention as described above has the following effects.

First, the configuration can be simplified since there is no need to use a frame memory unit for timing buffer for digital output.

Second, since the data receiver, i.e., the display device and the camera unit, can be completely synchronized on a pixel basis, power consumption due to unnecessary timing deviation can be reduced.

Claims (1)

In the camera of the system which transmits a digital output, Operation clocks Tclk1 and Tclk2 are outputted in order to match the clock synchronization between the camera and the data receiver based on the data reception clock by receiving the reference clock signal Cclk and image data output from the clock oscillator. A data transmission control unit for outputting data synchronized with Pclk1; A timing generator for outputting a timing signal Pclk2 for signal processing by the operation clock Tclk1; An image sensor operated by the timing signal, an analog / digital converter for converting an analog signal output to the image sensor into digital, and receiving a digital signal converted by an analog / digital converter and outputting image data synchronized with a pixel unit clock Luminance / color signal processor, And a data receiver which sends data control information and a data reception clock to the data transmission controller, and receives data from the data transmission controller.

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