JPH026469Y2 - - Google Patents

Description

[Detailed explanation of the invention] This invention has different numbers of horizontal and vertical pixels,
The present invention relates to an image signal conversion device configured to extract a standard television video signal from a raster scan dot image generator whose scanning frequency is different from that of the Japanese standard television system.

Recently, with the development of microcomputers, office computers, etc., these computers have come to be frequently used for various data processing. Many of the data, charts, etc. processed by these computers are displayed on the display of an image monitor, and there is a desire to incorporate such data, charts, etc. into broadcast programs. However, computer video monitors mainly use raster scan type dot image generators, and this method depends on the number of pixels,
It differs from the standard television system in terms of scanning frequency, interlacing, etc.

In order to make the image on the display of a computer image monitor conform to the standard, measures such as taking the image on the cathode ray tube (CRT) display with a standard television camera are taken, but the image quality deteriorates and the display and camera horizontal,
Bars appear in the camera output image due to the difference in vertical scanning frequency, making it difficult to use the image signal from the dot image generation circuit (CRTC) directly for broadcasting.

On the other hand, conventionally, format conversion devices have been used to convert television signals of different formats such as PAL format to NTSC format, and vice versa. There are DVE devices for special effects, but they all process only standard television signals and have the drawback of requiring complex circuitry and large amounts of memory. Therefore, such a format conversion device cannot be immediately used to extract a standard format television signal from a raster scan dot image generator, and even if it were possible to do so, it would be complicated, expensive, and complicated. It lacks versatility, and it has been difficult to easily apply this type of image to broadcast programs.

Therefore, in view of the above points, the purpose of this invention is to
It is an object of the present invention to provide an image signal converting device suitably configured to easily extract a standard television image signal from a raster scan dot image generating device.

In order to achieve such an object, the present invention stores an image composed of the number m of horizontal dots, the number n of vertical dots, and the number l of vertical retrace dots, and in response to the application of a clock signal, m× A dot image generation circuit outputs n-dot dot image signals in a predetermined order and also outputs a vertical retrace signal _, and receives a horizontal scanning synchronization signal of standard television system horizontal scanning frequency _H , and A first clock generation circuit generates one clock, and receives the horizontal scanning synchronization signal to generate a frequency _dp = l/l - (n - 262.5 + k) m _H (however, when n is an odd number, k = 0, a second clock generating circuit that generates a clock _for an odd field vertical retrace period (k=0.5 when n is an even number); a third clock generation circuit that generates a clock for the even field vertical retrace period of k)·m _H , and the vertical retrace signal generated by the dot image generation circuit and the odd and even field vertical retrace period of the standard television system. The first clock, the odd field vertical blanking interval clock, and the even field vertical blanking interval clock from the first, second, and third clock generation circuits are arranged in a predetermined order and timing based on the first, second, and third clock generation circuits. It is characterized by comprising a switching circuit that switches and takes out the output.

The present invention will be described in detail below with reference to the drawings.

First, the present invention points out that in order to convert the image signal of the dot image generation circuit (CRTC) into a standard format image signal, synchronization with the standard format signal can be achieved by controlling the CRTC with a standard format synchronization signal. It was created by focusing on

The CRTC dot clock D _clk is a one-pixel clock, and based on its frequency _d , the CRTC image signal, horizontal synchronization frequency _hrtc , and vertical synchronization frequency
_vrtc , horizontal retrace signal HRTC, vertical retrace signal VRTC
is occurring.

Dot clock required for one horizontal scan of CRTC
The relationship between these signals and the standard synchronization signal when a dot image is constructed by m the number of D _clks , n the number of scanning lines in one field, and l the number of vertical retrace scanning lines is shown below.

1 CRTC horizontal signal synchronization The relationship between _hrtc and _d is shown in equation (1).

l/ _hrtc = m/ _d (1) In order to match the horizontal synchronization frequency _H of the standard system and the horizontal synchronization frequency _hrtc of the CRTC, the relationship of the following equation (2) must hold.

_hrtc = _H (2) From equations (1) and (2), _d = m _H (3) From equation (3), if _H is multiplied by m, _hrtc will synchronize with _H ,
Image signals during the horizontal scanning period of CRTC are synchronized with the standard method.

2 Synchronization of vertical signals of CRTC In order to synchronize vertical image signals of CRTC, time correction is performed during the VRTC period of CRTC.
The CRTC image signal matches the standard synchronization signal.

The relationship between the time difference t between one field of the standard method and the CRTC is as shown in equation (4).

t=｜525/2 _H −n/ _H | =｜(262.5−n)H｜ (4) If a VRTC with time correction performed by this time difference t is formed, the vertical synchronization frequency _v of the standard method and
The vertical synchronization frequency _VRTC of CRTC matches. Dot clock to generate VRTC at that time
If the frequency of D _clk is _di , then (i) When t>0, that is, from the standard method
When CRTC has fewer scanning lines: VRTC = l/ _H + | 525/2 _H - n/ _H | = l/ _H + | 525-2n/ _H | = l/ _hrtc = ml/ _{di di} = 2 ml / _H (2l+｜525−2n｜ Therefore, _di = 2ml/{(2l+｜525−2n｜) _H }
(5) (ii) When t=0, that is, when both numbers of scanning lines are equal: VRTC=l/ _H =ml/ _di Therefore, _di = m _H (6) (iii) When t<0, that is, From the standard method
When CRTC has more scanning lines: VRTC=l/ _H −|525/2 _H −n/ _H | =ml/ _di Therefore, _di =2ml/{(2l−|525−2n|) _H }
(7) are obtained respectively.

The frequency of the CRTC dot clock D _clk varies depending on each value of the time difference t, that is, the number of vertical scanning lines of the CRTC, and equations (5), (6), and (7) hold true.

If the excess or deficiency in the number of CRTC scanning lines is controlled by the VRTC period and the frequency _di of the dot clock D _clk , the frequency of _{the VRTC} can be corrected.

However, in this case, when the number of scanning lines in one frame of CRTC is an odd number, the phase of the CRTC image signal and the horizontal scanning line of the standard method match, but when the number of scanning lines of the CRTC is an even number, the phase of the CRTC image signal matches the phase of the horizontal scanning line of the standard method. The horizontal phase is shifted in the vertical direction by 1/2H.

When the number of CRTC scanning lines is an even number
If VRTC is controlled by D _clk , which increases _H by 1/2H in odd fields and decreases _H by 1/2H in even fields, the CRTC image signal will match the standard synchronization.

The VRTC correction relationship for CRTC odd and even fields is shown below.

The relationship between VRTC (VRTCo) for odd fields is as shown in equation (8) below.

VRTCo=l/ _H +｜525/2 _H −n/ _H ｜+
1/2 _H = l/ _hrtcp = ml/ _dp (8) The relationship between VRTC (VRTCe) in an even field is as shown in equation (9) below.

VRTCe=l/ _H +｜525/2 _H −n/ _H |−
1/2 _H = l/ _hrtce = ml/ _de (9) where, _hrtcp : Horizontal synchronization frequency for odd field VRTC correction _dp : Dot clock frequency that generates horizontal synchronization frequency _hrtcp for odd field VRTC correction _hrtce : Even number Horizontal synchronization frequency _de for VRTC correction of field: Dot clock frequency that generates horizontal synchronization frequency _hrtce for VRTC correction of even field From equations (8) and (9), (i) When t>0, _dp = ml _H / (l+｜-n+263｜) (10) _de = ml _H / (l+｜-n+262｜) (11) (ii) When t<0, _dp = ml _H / (l-｜n-263｜) (12) _de = ml _H / (l - | n - 262 |) (13) Based on the relationships in equations (11) to (14) above, the new number of lines BL in the vertical retrace period to be converted is 2n
<525, for odd fields,
As shown in FIG. 1A, BL=l+(263-n), and for even fields, as shown in FIG. 1B, BL=1+(262-n).
If 2n>525, for odd fields, BL=l-(n-263), as shown in Figure 1C.
Similarly, for even fields, the first
As shown in Figure D, BL=l-(n-262).

From these equations (10), (11), (12) and (13), CRTC
In order to match the image signal with the standard synchronization signal, count the number of CRTC D _clocks (m), the number of scanning lines (n), and the number of vertical retrace scanning lines (l), and perform the necessary calculations based on these values. By multiplying _H based on the result, various D _clk can be generated from the CRTC image signal to generate an image signal that matches the standard synchronization signal.

Depending on the number n of scanning lines of CRTC, D _clk generated by equation (3) and equations (5), (6) and (7) or (10), (11), (12)
By switching the D _clk generated in equation (13) at the VRTC timing, a CRTC image signal matching the standard synchronization signal can be obtained.

FIG. 2 shows an example of the basic configuration of the image signal converter of the present invention, which is configured based on the formulas explained above, where 101 receives an HD signal as a standard horizontal scanning synchronization signal. , a frequency m _H that is m times the horizontal scanning frequency _H of the standard television signal.
A first clock generating circuit 102 that generates a first clock CL receives the HD signal and generates a frequency _dp =l/l-(n-262.5+k)·m _H , where k: k when n is an odd number. 103 is a second clock generating circuit that generates a clock CLo for the vertical retrace period of an odd field where n is an even number and k is 0.5.
A third clock generating circuit 104 receives the signal and generates an even field vertical retrace period clock CLe of frequency _de =l/l-(n-262.5-k) _.mH . Odd and even field vertical blanking signal VBLo and VBLe and CRTC vertical blanking signal
A switching circuit that receives VBL as a control signal, switches each clock CL, CLo, and CLe from the first, second, and third clock generation circuits 101, 102, and 103 in a predetermined order and timing, and outputs the clock signal SCL. , 105 is
An image composed of a number m of horizontal dots, a number n of vertical dots, and a number l of vertical blanking dots is stored,
In response to the application of the clock signal SCL from the switching circuit 104, a dot image signal of m×n dots is output in a predetermined order, and a vertical retrace signal VBL is output, thereby outputting the image converted to the standard format. This is a dot image generation circuit (CRTC) that obtains

Next, a third specific example of the image signal conversion device of the present invention will be described.
As shown in the figure. Here, 1 is a horizontal dot clock counting circuit (HDCC), and in this HDCC, CRTC
Dot clock D _clk required for one horizontal period of 105
Count several meters and send the value to horizontal dot clock generator circuit (HDCG) 2 and correction calculation circuit (CMDP).
Lead to 5. HDCG2 is a circuit that generates D _clk of CRTC105 locked to _H as shown in equation (3),
The details are shown in Fig. 4, which consists of a PLL multiplier circuit, that is, a PLL circuit 10, a VCO circuit 11, and a feedback programmable 1/m counter circuit 12, which multiplies the input _H by the count value m of the HDCC1. generates the first clock _d = m _H , and this _d
The output is supplied to the dot clock switching circuit (DCSW) 9.

A vertical scanning line counting circuit (VLCT) 3 counts the number of scanning lines of the CRTC 105 and supplies the value n to the CMDP 5. 4 is a vertical blanking counter circuit (VBCT), and this VBCT
4, the number of scanning lines in the VRTC period of the CRTC 105 is counted, and the value 1 is led to the CMDP5.
CMDP5 is HDCC1, VLCT3 and VBCT4
Based on these values, formulas (5), (6), and (7), or (10), (11), and (12) are provided according to the CRTC conditions. ) and (13), and the results are supplied to an odd field correction dot clock generation circuit (OCDG) 6 and an even field correction dot clock generation circuit (ECDG) 7. This CMDP5, as shown in Figure 5,
The configuration may be such that arithmetic processing is performed with a minimum CPU circuit configuration, where 13 is a CPU, 14 is an input/output circuit, 15 is a PROM, and 16 is a data bus. Here, if the CRTC image is generated by a computer, the CMDP 5 may be processed by the CPU of the computer itself, and in that case, the CMDP 5 as shown in FIG. 4 is unnecessary.

The odd field correction dot clock generation circuit (OCDG) 6 and the even field correction dot clock generation circuit (ECDG) 7 can have the same circuit configuration as HDCG2, and the correction dot clock frequency _dp is determined by the value of CMDP5.
The clocks CLo and _CLe for odd field and even field vertical retrace periods with and de are generated, respectively, and these correction dot clocks are generated.
CLo and CLe are supplied to a corrected dot clock switching circuit (CDSW) 8 which supplies standard odd and even field vertical retrace signals VBLo and
By receiving VBLe as a switching control input, the correction dot clocks CLo and CLe are switched according to the odd and even fields at the timing of these VBLo and VBLe signals, and the switching output is supplied to the dot clock switching circuit (DCSW) 9. During the vertical retrace period of the CRTC 105, the DCSW9 performs the following according to the odd and even fields:
The CRTC 105 is switched to the VRTC period correction dot clock D _clk to drive the CRTC 105 and its image signal is synchronized to the standard method. By performing image processing on this CRTC image signal and a standard synchronization signal, the CRTC 105 signal can be converted into a standard television image signal.

As is clear from the above, according to the present invention, a dot image signal can be easily converted into a standard television signal by adding a conversion circuit to the standard television system to the dot image generation circuit (CRTC). . Furthermore, the present invention has a simple circuit configuration, so the device can be constructed at low cost.

Since the present invention can extract CRTC image signals with different horizontal frequencies and different numbers of vertical scanning lines as standard monochrome signals, it is easy to apply the present invention to colorization. In this case, for example, R, G, and B standardized image signals are extracted from CRTC, and these R, G,
If the B signal is converted to an NTSC signal using the standard synchronization signal and color subcarrier, dot images can also be transmitted to cameras and VTRs that are driven by the same signal.
It can be used directly as an image signal material similar to
It can be widely applied to the field of program production. Therefore, according to the present invention, equipment such as character generators and graphic generators can be easily used for program production, so image materials can be used in a variety of ways for broadcasting stations, production, and education. has advantages. Furthermore, since the present invention applies the clock continuously, a simple and inexpensive dynamic RAM can be used.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the time conversion of the vertical retrace period in the present invention, Fig. 2 is a block diagram showing an example of the basic configuration of the present invention, and Fig. 3 shows a specific example of the configuration of Fig. 1. The block diagrams, FIGS. 4 and 5, are block diagrams each showing a specific example of the configuration of each part shown in the second figure. 101...first clock generation circuit, 102...
Second clock generation circuit, 103...Third clock generation circuit, 104...Switching circuit, 105...Dot image generation circuit, 1...Horizontal dot clock counting circuit, 2...Horizontal dot clock generation circuit, 3...
...Vertical scanning line counting circuit, 4...Vertical retrace counting circuit, 5...Correction calculation circuit, 6...Odd field correction dot clock generation circuit, 7...Even field correction dot clock generation circuit, 8...Correction dot clock switching circuit , 9...Dot clock switching circuit, 10...PLL circuit, 11...VCO circuit,
12...Programmable counter circuit, 13...
CPU, 14...Input/output circuit, 15...PROM,
16...Data bus.

Claims (1)

[Claims for Utility Model Registration] An image composed of m horizontal dots, n vertical dots, and l vertical blanking dots is stored, and in response to the application of a clock signal, a dot image of m×n dots is created. A dot image generation circuit that outputs signals in a predetermined order and also outputs a vertical retrace signal, and receives a horizontal scanning synchronization signal of a standard television system with a horizontal scanning frequency of _H to generate a first clock of a frequency of _mH . A first clock generation circuit receives the horizontal scanning synchronization signal and generates a frequency _dp = l/l - (n - 262.5 + k) m _H (however, when n is an odd number, k = 0, and when n is an even number, it is a second clock generating circuit that generates a clock for the odd field vertical retrace period ( _k = 0.5) _; a third clock generating circuit that generates a clock for the even field vertical retrace period; and a third clock generating circuit that generates a clock for the even field vertical retrace period, and based on the vertical retrace signal generated by the dot image generating circuit and the odd and even field vertical retrace signals of the standard television system. , a switch for switching and extracting the first clock, the odd field vertical blanking period clock, and the even field vertical blanking period clock from the first, second, and third clock generation circuits in a predetermined order and timing; An image signal conversion device characterized by comprising a circuit.