JPH0362686A - Television receiver - Google Patents

Abstract

PURPOSE:To eliminate deviation of a spatial sample position by deviating a phase by a prescribed clock for each horizontal period so as to write a small pattern use video signal into a memory. CONSTITUTION:A satellite broadcast signal is converted into a video signal SV1 of high definition TV system via a MUSE decoder 13. A ground broadcast signal is fed to a coefficient device 29, a delay element 27 and a coefficient 28 via a detection circuit 23 and an A/D converter 26 and written in a memory circuit 31 via an adder 30 in alternate fields. The coefficient multiplied by the coefficient devices 29, 28 is controlled by a large pattern synchronizing signal and a small pattern synchronizing signal. Moreover, a clock signal is extracted from an output video signal of the circuit 23 at a VCO 38 and formed to be clocks whose phases are retarded by 1/4 clock period each via a phase shift circuit 41 and fed to the converter 26 and the circuit 31. The output of the circuit 31 is inserted by an insertion circuit 16 into a large pattern as a small pattern picture of the same band as that of the signal SV1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to, for example, a television receiver that displays a screen based on a standard television system video signal on a part of the screen based on a high-definition television system video signal. in between.

[Prior Art] In television receivers, so-called picture-in-picture is known, in which a screen of the stomach is displayed as a small screen on a certain screen.

In recent years, in addition to the standard television system, high-definition television systems have been proposed as television systems. It is possible to display the following.

[Problem N to be solved by the invention] However, in a standard television system, for example, the NTSC system, the screen aspect ratio is 4=3 and the number of scanning lines is 525/
In contrast, in high-definition television systems, the screen aspect ratio is 16:9 and the number of scanning lines is 112.
5 pieces/frame.

Therefore, it is not possible to easily display a screen based on a standard television system video signal on a part of the screen based on a high quality television system video signal.

Therefore, in the present invention, for example, it is possible to satisfactorily display a screen based on a standard television system video signal on a part of the screen based on a high-definition television system video signal.

[Means for Solving the Problems] A television receiver according to the present invention displays a screen based on a second video signal of a standard television system on a part of the screen based on a first video signal of a high-definition television system. A television receiver comprising means for generating a first clock signal synchronized with a synchronization signal included in the first video signal, and synchronized with a color burst signal included in the second video signal, means for generating a second clock signal having a frequency 3/2 times that of the color subcarrier;
Write with a phase shift of /4 clock cycles,
and a memory device that is read using the first clock signal.

[Function] In order to insert a small screen image having the same signal band as a high definition television signal onto a large screen, the video signal for the small screen is written into memory at a frequency 372 times the color subcarrier, and the high definition television signal is inserted into the memory. The signal may be read using a frequency that is 1/2 times the nuclear power double frequency for the John signal.

Then, the frequency of 3/2 times the color subcarrier is shifted in phase by 174 clock periods for each scanning line and each frame. Therefore, when a small screen video signal is written into the memory using a second clock signal having a frequency 372 times that of the color subcarrier, the sample positions of each scanning line are spatially shifted.

In the above configuration, the phase of this second clock signal is shifted by 1/4 clock cycle every horizontal interval, and the small screen video signal is written to the memory, so the spatial sample position is shifted. That will no longer be the case.

[Embodiment] As a method for band-compressing and transmitting a high-definition television video signal, a multiplex subsampling transmission method using inter-field and inter-frame offset subsampling is known.

As one of the multiple subsample transmission methods, M U
S E (Multiple 5ub-Nyquist
A method called sampling encoding has been proposed.

In such a MUSE method decoder, the transmission signal is A/D converted and digital signal processing is performed to restore the original high-quality video signal, which is then D/A converted to an analog signal. .

In this case, the clock signal for A/D conversion and digital signal processing is formed by dividing the frequency of a 97.2 MHz original oscillation signal that is phase-synchronized with the synchronization signal included in the video signal.

Furthermore, in the current standard television system, such as the NTSC system, when extracting the necessary color information from the carrier color signal,
A 3.58 MHz color subcarrier synchronized with the color burst signal included during the horizontal blanking period is generated.

Therefore, in a television receiver that displays a small screen using an NTSC video signal on a part of the screen using a high-definition television video signal, when writing and reading out the small screen video signal to the field memory, the writing frequency is 3.58MHz L/ times (K, L=1.2
．． 3. ...), and the readout frequency is 1/Q times the original oscillation frequency of 97.2MHz (Q = 1. 2.
), since no new oscillator is required, the configuration is simple and economical.

Figure 1 shows PinP (picture in picture)
1 is a conceptual diagram of a high-definition television receiver, 2 is a picture tube, 3 is a large screen using a high-definition television system video signal, and 4 is a small screen using a standard television system, for example, an NTSC system video signal. It is.

Here, when reading the video signal for the small screen, if the reading frequency of the memory circuit '#i31, which will be described later, is selected to be 1/2 of the nuclear power double frequency, this will match the maximum clock frequency of the digital signal processing of the MUSE decoder. Tame, M
A small screen video having the same signal band as the USE decoded signal can be displayed on a large screen.

To realize this relationship, the write frequency to the memory circuit 31 is set to 5.37 MHz (L = 3. to 2), and the read frequency from the field memory is set to 48.6 MHz (9 MHz).
7.2 MHz÷2, that is, Q=2).

In the case where the frequency relationship is selected, the second
This will be explained with reference to the figures.

The frequency fsc of the color subcarrier and the original oscillation frequency fOC can be expressed accurately by the following equation.

... (1) foc=2'X3'X55 (Hz)
(2) Furthermore, the horizontal scanning frequency fH (HD) of the high-definition television system and the horizontal scanning frequency fH (NTSC) of the NTSC system are respectively expressed by the following equations.

fH(HD)=2X33X5' (Hz)...
(3)・−・・(4) Since the unit expressing the size of a pixel has different dimensions in the horizontal and vertical directions, first find the relationship between the two.

Here, [TV line] is used as a unit in the vertical direction, and [sec] is used as a unit in the horizontal direction to mean the time required to scan the pixel.

From the BTA S-001 standard, aspect ratio 9:16, sample rate 1/74.25MHz, and number of effective scanning lines is 1.
035 (TV book) and the number of effective pixels is 1920, the relationship between this is: ・ ・ ・ (5) In other words, 52 XI lX23XfH (HD) [TV book] = 3
[sec]... (6) It becomes.

In addition, M (MAN) scan lines of the small screen video signal are formed from the N scan lines of the NTSC system, and the MUS
When inserting as a small-screen video signal into the high-definition television system video signal output from the E-decoder before 12/11 time axis expansion, the following steps are required to obtain an aspect ratio of 3:4 x 11/12. The relationship must hold true.

525 X ηV X M/N [TV book] : x[
sec]=3: 4X11/12
・ ・ ◆ (7>ηV: Current broadcasting vertical effective scanning period rate = 0.935X: Small screen horizontal effective scanning time, that is, (8).

Substituting equation (6) into equation (8), (9) Also, if the clock frequency at which the small screen video signal is written to the memory is WC, and the clock frequency at which it is read from the memory is RCK, (0) ηH : Current broadcasting horizontal effective scanning period rate = 0° 3.

In other words, (1 1) becomes.

Calculating this equation (11), we get (1 2) becomes.

That is, 1°446 . . . If a scanning line conversion is performed from a book to a single line, a small screen without graphic distortion can be displayed.

However, it is not easy to strictly convert from 1.446♦ scanning lines to one scanning line, and the circuit scale becomes large. Therefore, scanning line conversion is facilitated by setting a permissible range for graphic distortion.

For example, if a value of ±1% is set as the allowable range of graphic distortion, N/M should be within the range of the following equation.

... (13) If the natural numbers that make N and M the smallest within this range are selected, N/M = 13/9. In other words, it is sufficient to convert the scanning lines from 13 to 9.

The conversion from 13 to 9 scanning lines will be described below.

For example, in FIG. 2, when the current signal is C, the current signal C is multiplied by a coefficient of 4/9, the signal B one horizontal period ago is multiplied by a coefficient of 5/9, and these are added. Thus, an H scanning line signal can be obtained. When the current signal is C', multiply the current signal C' by a coefficient of 6/9,
By multiplying the signal B' of one horizontal period before by a coefficient of 3/9 and adding these, the scanning line signal of ■' can be obtained.

An embodiment of the present invention will be described below with reference to FIG. M[ as a high definition television signal
The ISE signal is illustrated.

In the figure, a satellite broadcast signal received by an antenna 11 is supplied to a tuner 12, and an M
The USE signal is supplied to the MUSE decoder 13. This MUSE signal is band-compressed to 8°1 MHz on the transmitting side, and the MUSE decoder 13 converts the MUSE signal from A/D to digital signal processing, and converts it into a high-definition television system with a sampling frequency of 48.6 MHz. A signal SVI is obtained.

In this case, the voltage 1t11j oscillator 14 outputs a clock signal synchronized with the same amount signal included in the MUSE signal, and digital signal processing is performed based on this clock signal.

The video signal SVI output from the decoder 13 in this way
is supplied to the insertion circuit 16 as a large screen video signal.

The vertical synchronization signal and horizontal synchronization signal formed by the MUSE decoder 13 are supplied to the memory control circuit 25 as large-screen synchronization signals.

The terrestrial broadcast signal received by the antenna 21 is sent to the tuner 22.
The intermediate frequency signal from the tuner 22 is supplied to an intermediate frequency amplification and detection circuit 23, and this circuit 2
The NTSC video signal SV2 output from A/
The signal is supplied to the D converter 26.

The video signal SV2 converted into a digital signal by the A/D converter 26 is supplied to a coefficient unit 29 composed of a ROM (read only memory), multiplied by a predetermined coefficient by this coefficient unit 29, and then sent to an adder 30. This video signal SV2 is also supplied to a coefficient unit 28 constituted by a ROM via a delay element 27 having a delay time of one horizontal period, and after being multiplied by a predetermined coefficient by this coefficient 628, it is sent to an adder. 3
0. The output signal of the adder 30 is supplied as a write signal to the field memories 32 and 33 of the memory circuit 31, and is written into these memories 32 and 33 in field alternation.

The video signal SV2 from the circuit 23 is supplied to a sync separation circuit 24, and the vertical sync signal and horizontal sync signal separated by the sync separation circuit 24 are supplied to the memory control circuit 25 as a small screen sync signal.

The coefficient multiplied by the coefficient multipliers 28 and 29 is calculated by the memory control circuit 25 based on the large screen synchronization signal and the small screen synchronization signal.
controlled by For example, Ei No. 1118 SV2,
In the case of FIG. 2C, the coefficient of the coefficient multiplier 29 is set to 4/9, and the coefficient of the coefficient multiplier 28 is set to 5/9. Since these coefficients circulate every 13 scanning lines, a 4-bit address signal is supplied from the memory control circuit 25 to the ROM with coefficients 828.29 for control. This 4-bit address signal is generated by a hexadecimal counter which is reset by, for example, a small-screen vertical synchronization signal and which uses a small-screen horizontal synchronization signal as a clock signal.

In this way, the current signal output from the A/D converter 26 and the signal output from the delay element 27 delayed by one horizontal period are each multiplied by a predetermined coefficient by the coefficient multipliers 29 and 28, and then added. 30, and conversion from 13 to 9 scanning lines is performed.

Further, the video signal SV2 from the circuit 23 is transmitted to the band amplifier circuit 3.
The color burst signal extracted by this band amplification circuit 36 is supplied to a phase detection circuit 37. The phase error signal from this phase detection circuit 37 is supplied to a voltage controlled oscillator (VCO) 3B, and this voltage controlled oscillator 38
The output signal is supplied to the phase detection circuit 37 via a frequency divider @39 with a frequency division ratio of 1/3.

These phase detection circuit 37, voltage controlled oscillator 3, and frequency divider 39 constitute a so-called APC circuit, and the voltage controlled oscillator 38 outputs a 3.58 MHz color subcarrier that is phase synchronized with the color burst signal. A sine wave signal with a frequency of is output. This sine wave signal is waveform-shaped (not shown) and then supplied to a frequency divider 40 with a frequency division ratio of 1/2.

Further, the horizontal synchronization signal separated by the equal amount separation circuit 24 is 4
The signal is supplied to a road counter 35 to obtain a signal of four horizontal periods. These four horizontal periodic signals are supplied to the changeover switch 34 as a control signal.

On the other hand, the output signal of the frequency divider 40 is supplied to a phase shift circuit 41, and four clock signals whose phase is delayed by 1/4 clock cycle (the frequency is 5° 37 MHz) are sent to the changeover switch 34 a, b, c.

d is supplied to each terminal.

The output signal selected as a + b * C + d every horizontal period by the control signal from the quaternary counter 35 is supplied to the AD converter 26 as a clock signal for sampling, and is also supplied to the memory circuit 31 as a clock signal for writing. Supplied as a clock signal.

The frequency of 5.37 MHz is 136 f of the horizontal frequency.
5/4 times, 17 per scan line and per frame
The phase is shifted by 4 clock cycles. If this signal is used as it is as a clock signal, a sampling pattern as shown in FIG. 4 will result, resulting in spatial positional deviation.

In the figure, ○ is the sample position in the 4n-th frame, × is the 40,011-th frame, Δ is the 40,000-2nd frame, and 1 is the sample position in the 4n-1,000-3rd frame.

In this example, the phase shift circuit 41 and the changeover switch 3
By providing 4 and 5,37M, the phase is shifted by 174 clock periods every horizontal interval as described above.
Since the Hz signal is used as the clock signal, such spatial positional deviations are corrected.

Further, a signal with a frequency of 97.2 MH2O is output from the voltage controlled oscillator 14, and this signal is supplied to a frequency divider 15 with a frequency division ratio of 1/2.
A signal with a frequency of z is output, and this signal is sent to the memory circuit 3.
1 as a read clock signal.

The memory control circuit 25 also determines whether the large screen and small screen video signals are of the first field or the second field based on the large screen synchronization signal and the small screen synchronization signal. is determined.

Reading from the memory circuit 31 is performed vIvs so as to read from the field memory that is not being written. At this time, based on the above-described determination result, the video signal S
When VI is the second field and the small screen video signal read from the memory circuit 31 is from the first field, the reading of the small screen video signal is 1.
It is controlled to delay by a scanning line.

The small screen video signal SV3 read from the memory circuit #i31 is supplied to the insertion circuit 16.

This insertion circuit 16 inserts the small screen video signal SV3 into the large screen video signal S1 supplied from the MUSE decoder 13. The composite video signal output from this insertion circuit 16 is supplied to a time axis expansion circuit 17 and
11 time axis extensions are performed. This is because the video signal SVI output from the MUSE decoder 13 is time-axis compressed to 11/12.

The composite video signal outputted from the time axis expansion circuit 17 is converted into an analog signal by the D/A converter 18 and then supplied to the picture tube 20 via the video amplification circuit 19. As a result, on the picture tube 20, a screen based on the video signal SV3 is displayed on a part of the screen based on the video signal SVI.

Note that in this example, only the luminance signal has been explained to simplify the explanation, but the color signal is also processed in the same way.

According to this example, the clock frequency read from the memory circuit 31 is 48.6 MHz, which matches the maximum clock frequency of the digital signal processing of the MUSE decoder. Screen images can be projected on a large screen.

In that case, the 3/58MHz 3/58MHz signal is shifted in phase by 174 clock cycles for each horizontal period.
2 +l! Since a signal having a frequency of I is used as a writing clock signal, spatial positional deviation can be corrected.

In addition, in the above embodiment, NTSC is used as the standard method.
Although the system is shown, it can be similarly applied to the PAL system and the SECAM system.

[Effects of the Invention] As explained above, according to the present invention, when a small screen image having the same signal band as a high-definition television signal is inserted into a large screen, a frequency 3/2 times the color subcarrier is used. rice cake,
Since the small screen video signal is written in the memory with the phase shifted by 1/4 clock cycle every horizontal period, the spatial sample position will not shift.

[Brief explanation of drawings]

1, 2, and 4 are diagrams for explaining the present invention, and FIG. 3 is a configuration diagram showing one embodiment of the present invention. 11.21 ◆ 12.22 ・ 13 ・ 14.38 ・ 15.39゜l 6 ◆ 17 ・ 18 ◆ 19 ・ 20 ・ 23 # 24 ・ 25 # ◆・Antenna・・Tuner◆・MUSE decoder・・Voltage controlled oscillator 0... Frequency divider... Insertion circuit... Time axis expansion circuit... D/A converter... Video amplification circuit... Picture tube... Intermediate frequency amplification and detection circuit... Synchronization separation circuit... Memory control circuit 28゜32゜26...A/D converter 27・◆・Delay element 29...Coefficient unit 30...Adder 31・◆Content memory circuit 33...Field memory 34...Selector switch 35 ◆◆・Quaternary counter 36... Bandwidth amplifier circuit 37... Phase detection circuit 41... Phase shift circuit

Claims (1)

[Claims] (1) In a television receiver that displays a screen based on a second video signal of a standard television system on a part of the screen based on a first video signal of a high-definition television system, the content contained in the first video signal is The first signal synchronized with the synchronization signal
means for generating a second clock signal synchronized with the color burst signal included in the second video signal and having a frequency 3/2 times that of the color subcarrier; and a memory device that writes the video signal No. 2 by shifting the phase of the second clock signal by 1/4 clock cycle every horizontal period, and reads the video signal using the first clock signal. television receiver.