KR100236023B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and to provide a liquid crystal display device suitable for improving the reliability of the device by reducing the contact resistance by forming a plurality of through holes in the storage capacitor region.

The liquid crystal display of the present invention is a liquid crystal display having a thin film transistor composed of a gate electrode, a source and a drain electrode and a storage capacitor, which is formed on the front surface including the upper electrode of the thin film transistor and the storage capacitor. A passivation layer having a plurality of through holes formed to expose an upper electrode, and a pixel electrode formed on the passivation layer to be in electrical contact with the storage upper electrode through the plurality of through holes and to be in electrical contact with the drain electrode. It is characterized by.

Description

Liquid crystal display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device in which a plurality of through holes are formed in a storage capacitor area so as to reduce contact resistance and to improve device reliability.

In general, the liquid crystal display device includes a liquid crystal encapsulated between the upper and lower plates, and the upper and lower plates.

Here, the upper plate is arranged with a color filter layer of R (red), G (green), and B (blue) to represent the common electrode and color, and the lower plate is disposed at the intersections of the data lines, the scan lines, and the respective intersections arranged on the matrix. The thin film transistor and the pixel electrode are disposed.

That is, the thin film transistor including the gate electrode G, the source electrode S, and the drain electrode D is formed at a predetermined interval on the lower plate.

Each pixel region is connected to the drain electrode D of each thin film transistor to form a pixel electrode.

On the other hand, a black matrix layer for blocking light of portions other than the pixel electrodes formed on the lower plate is formed at a predetermined interval on the upper plate, and R, G, B color filter layers for expressing color on the upper plate between each black matrix layer. Is formed.

A common electrode is formed over the color filter layer and the black matrix layer.

Hereinafter, a conventional liquid crystal display will be described with reference to the accompanying drawings.

FIG. 1 is a layout diagram according to a conventional liquid crystal display, and FIG. 2 is a diagram along the line AA ′ of FIG. 1.

First, as shown in FIG. 2, the conventional liquid crystal display includes a gate electrode 23 and a lower electrode of the storage capacitor having a predetermined interval on the transparent insulation engine 21 and having the anodic oxide film as the first insulating layer 22. 23a), a second insulating layer 24 formed on the ground including the engine 21, a semiconductor layer 25 formed in a predetermined region on the second insulating layer 24 to sufficiently cover the gate electrode 23, and Source / drain electrodes 26 and 26a formed on the semiconductor layer 25 on the gate electrode 23 at regular intervals, and formed between the source / drain electrodes 26 and 26a and the semiconductor layer 25. an upper electrode 26, the source / drain electrodes 27 and 27a and a storage capacitor of the storage capacitor formed on the n + layer 25a and the second insulating layer 24 on the lower electrode 23a of the storage capacitor. Passivation layer 28 formed on the front surface, including the upper electrode 26, the passivation And a pixel electrode 29 formed on the passivation layer 28 so as to contact the drain electrode 27a and the upper electrode 26 of the storage capacitor through the through hole of the base layer 28. .

The n + layer 25a is simultaneously patterned when patterning the source / drain electrodes 26 and 26a.

In the liquid crystal display having such a structure, the contact resistance of the through hole formed in the storage capacitor region is increased.

That is, as shown in FIG. 2, the first capacitor is formed by the upper electrode of the lower electrode, the insulating layer, and the capacitor of the storage capacitor, and the second capacitor is formed by the upper electrode, the foreign material layer, and the pixel electrode of the capacitor. Is formed.

In this case, the foreign material layer is generated in the process of patterning the passivation layer 28 to form a through hole, which increases the contact resistance between the pixel electrode 29 and the storage capacitor upper electrode 26 through the through hole.

That is, in the conventional liquid crystal display, since one through hole is formed in the storage capacitor region, the contact resistance per unit area increases accordingly.

In other words, the contact area of the pixel electrode 29 in contact with the storage capacitor upper electrode 26 through the through hole is small, thereby increasing the contact resistance.

This can be confirmed by the following equation.

It can be seen from the above equation that as the area S increases, the capacitance C increases. Where ε is the dielectric constant of the dielectric.

Such a conventional liquid crystal display has the following problems.

First, since the electrode of the storage capacitor and the pixel electrode are contacted through a single through hole, the contact area is small and a large amount of foreign material layer is formed at the interface.

Second, the contact area is small, the contact resistance is increased, and the small contact area reduces the capacity of the storage capacitor.

An object of the present invention is to provide a liquid crystal display device suitable for increasing the capacity of a storage capacitor by reducing the contact resistance and increasing the contact area by forming a plurality of through holes to solve the above problems.

1 is a layout diagram of a conventional liquid crystal display.

2 is a cross-sectional view of a conventional liquid crystal display device taken along the line AA ′ of FIG. 1.

3 is a layout diagram of a liquid crystal display of the present invention.

Figure 4a is a cross-sectional view taken along the line AA 'of 3 degrees.

4b is a cross-sectional view taken along line B-B 'of FIG.

5A to 5D are sectional views of the manufacturing process of the liquid crystal display device of the present invention.

6 is a layout diagram showing another embodiment according to the present invention.

7 is a cross-sectional view taken along the line AA ′ of FIG. 6.

* Explanation of symbols for main parts of the drawings

41 engine 42 anodized film

43: first gate electrode 43a: second gate electrode

44: second leading layer 45: semiconductor layer

45a: n + layer 46, 46a: source / drain electrode

47: upper electrode of the storage capacitor 48: passivation layer

49: pixel electrode

The liquid crystal display of the present invention for achieving the above object is a liquid crystal display having a thin film transistor and a storage capacitor consisting of a gate electrode, a source and a drain electrode, the front surface including the thin film transistor and the upper electrode of the storage capacitor A passivation layer formed on the passivation layer and having a plurality of through holes formed to expose the capacitor upper electrode, and a pixel electrode formed on the passivation layer to be in contact with the storage upper electrode through the plurality of through holes and to be in electrical contact with the drain electrode. Characterized in that comprises a.

Hereinafter, a liquid crystal display of the present invention will be described with reference to the accompanying drawings.

3 is a layout diagram of a liquid crystal display according to the present invention, and FIG. 4A is a cross-sectional view taken along line AA ′ of FIG. 3. 4B is a cross-sectional view taken along the line BB ′ of FIG. 3.

First, FIG. 3 illustrates that a plurality of through holes are formed in an area of the storage capacitor to connect the upper electrode and the pixel electrode of the storage capacitor.

4A is a cross-sectional view taken along line AA ′ of FIG. 3, and the first gate electrode 43 and the lower electrode of the storage capacitor are formed with the anodic oxide film 42 as the first insulating layer at a predetermined interval on the transparent insulation engine 41. Predetermined on the second insulating layer 44 to include the second gate electrode 43a, the second insulating layer 44 formed on the entire surface including the anodic oxide film 42, and the first gate electrode 43. The semiconductor layer 45 formed in the region, the source electrode 46 and the drain electrode 46a formed at predetermined intervals on the semiconductor layer 45, the semiconductor layer 45 and the source / drain electrode 46. N + layer 45a formed between the first and second electrodes 46a, the upper electrode 47 of the storage capacitor formed on the second insulating layer 44 on the second gate electrode 43a, and the upper electrode 47 of the storage capacitor. Passivation layer 48 formed on the front surface including a, and on the storage capacitor upper electrode 47 A plurality of through holes formed through the sieve layer 48, a drain electrode 46a through the passivation layer 48, and a top electrode 47 of the storage capacitor through the plurality of through holes. And a pixel electrode 49.

The storage capacitor is implemented by the second gate electrode 43a and the upper electrode 47 of the storage capacitor using the second insulating layer 44 as a dielectric film.

In this case, since the pixel electrode 49 is in contact with the upper electrode 47 of the storage capacitor, the pixel electrode 49 is contacted through a plurality of through holes, thereby having a small contact resistance.

In addition, since a plurality of through holes are formed, foreign matter is significantly reduced in patterning the passivation layer 48 to form the through holes.

The n + layer 45a patterns the source / drain electrodes 46 and 46a and patterns the mask as the mask.

4B is a cross-sectional view taken along the line B-B 'of FIG. 3, and shows that the pixel electrode 49 is formed without overlapping with the data line.

The manufacturing process of the liquid crystal display device having such a structure is as follows.

5A to 5D are sectional views of the manufacturing process of the liquid crystal display device of the present invention.

First, as shown in FIG. 5A, the first gate electrode 52 and the second gate electrode 53 are formed to have a predetermined distance from each other by forming and patterning a metal layer on the transparent insulation engine 51.

In this case, the first gate electrode 52 is used as the gate electrode of the thin film transistor, and the second gate electrode 53 is used as the lower electrode of the storage capacitor to be formed in a later process.

The first and second gate electrodes 52 and 53 are anodized to form an anodized film 54 on the surface thereof, and an insulating layer 55 is formed on the entire surface including the substrate 51.

Subsequently, as shown in FIG. 5B, after the semiconductor layer 56 is formed on the insulating layer 55, the semiconductor layer 56 is patterned to remain only in the thin film transistor region and the n + layer 56a is formed on the semiconductor layer 56. The source / drain electrode material of the thin film transistor is formed on the entire surface including the n + layer 56a and then patterned to form a source electrode 57 and a drain electrode 57a, and the patterned source / drain electrode 57 is formed. The n + layer 56a is selectively removed using 57a) as a mask.

Subsequently, an upper electrode 58 of the storage capacitor is formed on the second gate electrode 53a.

In this case, the upper electrode 58 and the source / drain electrode materials 57 and 57a of the storage capacitor are patterned in the same process as the same material.

Next, as shown in FIG. 5C, a passivation layer 59 is formed on the entire surface including the source / drain electrodes 57 and 57a and the upper electrode 58 of the storage capacitor, and the passivation layer 59 is illustrated in FIG. 5D. ) Is formed to form a through hole to expose a predetermined portion of the surface of the drain electrode 57a, and a plurality of through holes are formed to expose the surface of the upper electrode of the storage capacitor.

Subsequently, a pixel electrode material is formed on the entire surface and patterned to form the pixel electrode 60.

6 is a layout showing another embodiment according to the present invention and 7 is a cross-sectional view taken along line A-A 'of 6 degrees.

That is, as shown in FIG. 6, the through-hole formed in the storage capacitor region 63 even in a structure in which the pixel electrode 62 is overlapped on the data line 61 (hereinafter referred to as POD: Pixel on Data) is formed. A plurality of holes 64 are formed.

7 shows a cross-sectional view of the overlapping pixel electrode 62 on the data line 61.

As described above, the liquid crystal display of the present invention forms a plurality of through holes in the storage capacitor region, thereby increasing the contact area between the pixel electrode and the upper electrode of the storage capacitor and thus reducing the contact resistance.

In addition, the capacity of the storage capacitor increases as the contact area increases.

Claims (3)

A liquid crystal display device having a thin film transistor and a storage capacitor including a gate electrode, a source, and a drain electrode, the liquid crystal display comprising: a plurality of through holes formed on a front surface of the thin film transistor and an upper electrode of the storage capacitor and exposing a top capacitor electrode; And a pixel electrode formed on the passivation layer to be in contact with the storage upper electrode and electrically contact the drain electrode through the formed passivation and the plurality of through holes. The liquid crystal display of claim 1, wherein the lower electrode of the storage capacitor is the gate electrode material and the upper electrode of the storage capacitor is the same material as the source and drain electrodes of the thin film transistor. A liquid crystal display device comprising a first substrate, a second substrate, and a liquid crystal enclosed therebetween, the thin film transistor and the storage capacitor formed on the second substrate facing the first substrate, an upper portion of the thin film transistor and the storage capacitor. A passivation layer formed on the front surface including the electrode and having a plurality of through holes formed to expose the upper electrode of the storage capacitor, and a pixel electrode formed on the passivation layer to contact the upper electrode of the storage capacitor through the plurality of through holes. Liquid crystal display device comprising a.