KR100235559B1 - Power protection circuit for insulated gate bipolar transistor - Google Patents

Abstract

[purpose]

The present invention precisely detects the overcurrent flowing through the collector stage of the IGBT to softly block the IGBT gate voltage so as to change gradually, thereby preventing malfunction in the circuits at the later stage.

[Configuration]

The present invention provides a sensing unit comprising a first comparator, a second comparator, a third comparator, and a first flip-flop for controlling a sensing signal and an input signal for preventing short-circuit current and over-current, and detecting the detected sensing signal in a first manner. A first delay circuit which is delayed for a predetermined period through the buffer, a fourth comparator controlled by the output of the first delay circuit, a second flip flop controlled by the fourth comparator and a second inverter to the third buffer; A second delay circuit connected to the second delay circuit for delaying the detected detection signal through a second buffer for a predetermined period, a fifth comparator controlled by an output of the second delay circuit, and a third flip controlled by the fifth comparator A control unit including a flop, a first transistor unit, a second transistor unit, a third transistor unit, and the first, second, and third transistor units 31, 32 controlled by an output from the sensing unit and the control unit. IGBT section controlled by 33 It is composed of an output unit including a.

Description

Gate Insulated Transistor Power Protection Circuit

1 is a circuit diagram in the prior art.

2 is an IGBT protection circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

100 detection unit 200 control unit

300: output unit

11, 12, 13: first comparator, second comparator, third comparator

14: first flip-flop 15: first half electric

21: the first buffer 22: the second buffer

23: first delay circuit 24: second delay circuit

25: fourth comparator 26: fifth comparator

27a: second flip flop 27b: third flip flop

28a: Second semi-circuit 28b: Third semi-circuit

29: third buffer 34: IGBT unit

31, 32, 33: first transistor section, second transistor section, third transistor section

The present invention relates to a gate protection transistor (IGBT: Insulated Gate Bipolar Transistor (IGBT)) power protection circuit, and when the overcurrent flows to the collector terminal of the IGBT power, it detects the overcurrent and gates the gate of the IGBT. And a gate insulating transistor power protection circuit for stabilizing power by cutting off).

In general, an IGBT circuit is composed of transistors and used for high power, and consists of two emitters of transistors and uses a resistor on one of the two emitters to sufficiently lower the high voltage so that the circuit can be used in the circuit. By sensing the current of the emitter by using a resistor as described above, the sensed current is fed back to the sense input to prevent malfunction caused by overcurrent and short circuit current.

FIG. 1 is a circuit diagram of the related art. The detection unit 100 detects detection signals for short current protection (SCP) and over current protection (OCP), and the detected detection signal. The controller 200 is configured to delay and control a predetermined time period, and the output unit 300 outputs the delayed and controlled sensing signal in association with the sensing unit 100.

The sensing unit 100 controls the first comparator 11 having the short-circuit current prevention detection function, the second comparator 12 having the overcurrent protection detection function, an input signal, and an output of the second comparator 12. A first flip flop 14 and a first inverter 15 connected to an output terminal of the first flip flop 14 to invert a signal.

The control unit 200 is a first buffer 21 which is an OR gate for controlling the output of the first sensing unit 100 as an input, and a first delaying signal of the first buffer 21 for a predetermined time. A delay circuit 23, a second flip-flop 27a for controlling the first delay circuit 23 and an input signal, and a second inverter 28a for inverting the outputs of the second flip-flop 27a; And a second buffer 29, which is an OR gate for controlling the input signal.

The output unit 300 may include a first transistor unit 31 for controlling the output of the controller 200, a second transistor unit 32 for controlling another output of the sensing unit 100, and the second transistor unit 32. It consists of an IGBT 34 which is controlled by the 1st transistor part 31 and the 2nd transistor part 32, and outputs it.

In the circuit of the related art configured as described above, when the current of the IGBT 34 flows more than 53A, when the voltage of the sensing input, which is the IGBT current sensing terminal, is detected as overcurrent, If the input voltage of the first comparator 11 and the second comparator 12 is 0.5V or more, an overcurrent protection (OCP; hereinafter OCP) operation is performed, and if it is 0.75V or more, a short circuit current prevention (SCP; hereinafter SCP) is called. ) To operate. In the above operation, in order to prevent malfunction due to peak current due to noise, the signal at the output terminal (a) of the controller 200 becomes high after a delay of about 10 ms.

Then, the output is always low regardless of the input signal, and the output of the IGBT unit 34 is blocked by the OCP and SCP operations.

In addition, when the current between the collector emitter of the IGBT 34 flows about 53A or more, the second comparator 12 operates to block the gate of the IGBT 34 and flows about 80A or more. The second comparators 12 all operate to block the IGBT 34 by controlling the gate of the IGBT 34.

However, in the conventional circuit, since the operating voltage level interval between the first comparator 11 of SCP and the second comparator 12 of the OCP is too large and does not shut off the correct soft gate, it may cause malfunction in the circuit connected to the output terminal. There was a problem.

Therefore, the present invention has been made to solve the above-mentioned conventional problems. The main object of the present invention is to detect the overcurrent flowing through the collector stage of the IGBT so that the IGBT gate voltage is softly changed so as to gradually change, thereby malfunctioning the circuit of the subsequent stage. It is to prevent.

And a characteristic configuration for this, a sensing unit consisting of a first comparator, a second comparator, a third comparator, a first flip-flop for detecting the detection signal for short-circuit current prevention and over-current protection, and the detected detection signal A first delay circuit delayed for a predetermined period through the first buffer, a fourth comparator controlled by the output of the first delay circuit, a second flip flop controlled by the fourth comparator, and a third through the second inverter A second comparator connected to a buffer and delaying the detected detection signal through a second buffer for a predetermined period, a fifth comparator controlled by an output of the second delay circuit, and a fifth comparator controlled by the fifth comparator And a control unit including a third flip-flop, and an output unit including a first transistor unit, a second transistor unit, a third transistor unit, and an IGBT unit controlled by an output from the sensing unit and the control unit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings and examples.

2 is an IGBT protection circuit diagram of the present invention, wherein the circuit of the present invention includes a sensing unit 100 for controlling a detection signal and an input signal for short-circuit current protection and over-current protection, and a detection signal detected by the detection unit for a predetermined period of time. And a control unit 200 for delaying and controlling the output unit 300, and an output unit 300 configured to cut off the voltage of the IGBT 34 by a signal output from the control unit 200.

The detection unit 100 and the first comparator 11, which is an op amp (OP Amp) to compare the input signal to a reference voltage of 0.75V and another input signal as another input to prevent short-circuit current The second comparator 12, which is an op amp to compare the input signal with a reference voltage of 0.5V and the other input signal, to prevent overcurrent, and the one input is a reference voltage to prevent overcurrent. Is set to 0.6V, and the output of the third comparator 13 and the first comparator 11, which are op amps, for comparing the input signal with another input as S input, and the input signal as R input. Is composed of a first flip flop 14 which is an RS flip flop.

The control unit 200 is an OR gate having an output of the second comparator 12 of the sensing unit 100 and the output of the first inverter 15 as an input, and a first buffer 21 and the first buffer. A first delay circuit 23 connected to the output of the buffer 21 to delay the signal by about 10 Hz, and an output of the first delay circuit 23 as one input and a reference voltage configured at another input A second flip-flop 27a and a second flip-flop, which are RS flip-flops for comparing the fourth comparator 25 and the output of the fourth comparator 25 as R inputs and an input signal as S inputs. A second invertor 28a connected to the non-inverting output terminal of 27a) and a NOR gate having the (a) output of the second inverter 28a as one input and the input signal as another input. A second buffer 22 configured as an OR gate having an output of the third comparator 13 of the sensing unit 100 and an output of the first inverter 15 as an input. Wow The second delay circuit 24, which is connected to the output of the second buffer 22 to delay the signal by about 5 kHz, and the output of the second delay circuit 24 as one input, and constitutes a reference voltage at another input. A third flip-flop 27b and a third flip-flop, which are RS flip-flops for which an output of the fifth comparator 26 and an output of the fifth comparator 26 are input as S and an input signal is input as R. And a third inverter 28b connected to the inverting output terminal of the 27b to invert the output.

The output unit 300 includes a first transistor unit 31 for short-circuit current control, a second transistor unit 32 and a third transistor unit 33 for overcurrent control, and the first, second and third transistors. It consists of the IGBT part 34 controlled by the part 31,32,33.

The first transistor unit 31 inputs the non-inverting output of the third buffer 29 of the control unit 200 as a base of the first transistor 1 having a voltage Vcc2 connected to the collector. The inverting output of the third buffer 29 connects the collector to the emitter of the first transistor 1 and to the base of the second transistor 2 to which the emitter is grounded. The emitter of the third transistor 3 in which the voltage Vcc1 is connected to the collector and the voltage Vcc2 is connected to the base is the fourth transistor 4 in which the emitter of the first transistor 1 is connected to the base and the emitter is grounded. Connect to the collector of). The emitter of the third transistor 3 is connected to the base of the seventh transistor 7, which is an IGBT, through the first resistor R1.

The second transistor unit 32 connects the output of the first inverter 15 of the sensing unit 100 to the base of the fifth transistor 5 in which the emitter is grounded, and the collector has a second resistance. It is configured by connecting to the base of the 7 transistor (7).

The third transistor unit 33 connects the output of the third inverter 28b of the controller 200 to the base of the sixth transistor 6 having the emitter grounded, and the collector connects the seventh through a third resistor. It is constructed by connecting to the base of the transistor (7).

The IGBT unit 34 is configured such that the voltage Vcc is connected to the collector and the emitter is grounded.

The following describes the operating state of the present invention configured as described above.

Overcurrent according to the condition of the second comparator 12 in which the voltage of the sensing input for sensing the current flowing from the collector of the seventh transistor 7 which is the IGBT 34 to the emitter is 0.5 V as the reference voltage for the non-inverting input. In the case of the preventive operation, after the output from the second comparator 12 is delayed by about 10 ms in the first delay circuit 23 for preventing malfunction due to noise through the first buffer 21, the second flip-flop ( If point (A) becomes high through 27a), the output becomes low regardless of the input signal.

When the voltage of the sense input is an overcurrent prevention operation according to the condition of the third comparator 12 where 0.6 V is used as the reference voltage for the non-inverting input, the second comparator 12 and the third comparator 13 After the output is delayed by about 5 ms in the second delay circuit 24 for preventing malfunction due to noise through the second buffer 22, the third flip-flop 27b and the third inverter 28b (b) ) Point becomes high and the sixth transistor 6 is turned on and at the same time, the point A becomes high after about 10 ms and the operation of the seventh transistor 7 of the IGBT 34 is switched rapidly. Rather, the switch is switched to have a certain time as described above, so that the switch is softly switched off.

When the voltage of the sense input is a short circuit current protection operation according to the condition of the first comparator 11 in which 0.75 V is used as a reference voltage for the non-inverting input, the second comparator 12 and the second comparator 12 are operated in the same manner as the over current protection operation. Since the output from the third comparator 13 is delayed through the first delay circuit 23 and the second delay circuit 24, the sudden operation of the seventh transistor 7 is prevented and the circuit of the subsequent stage malfunctions due to the transient voltage. To prevent.

As described in detail above, the present invention is to more precisely detect the overcurrent when the overcurrent flows through the collector of the IGBT, and to softly shut off the gate of the IGBT. The delayed circuit is used again to prevent a malfunction caused by an overshoot or the like in the IGBT element as well as in a circuit at a later stage.

Claims (6)

A detector for controlling a detection signal and an input signal for preventing short circuit current and overcurrent, a controller for delaying and controlling a detection signal detected by the detector for a predetermined time, and an output controlled by a signal output from the controller A gate insulated transistor power protection circuit comprising a portion; The sensing unit may include: a first comparator comparing the sensing signals input for preventing short circuit current; a second comparator comparing the sensing signals for preventing overcurrent; a third comparator comparing the sensing signals to prevent overcurrent; A first flip-flop for inputting an output of the first comparator and an input signal, and a first inverter for inverting the output of the first flip-flop; The controller may include a first buffer configured to receive an output of the second comparator and an output of the first inverter, a first delay circuit connected to an output of the first buffer to delay a signal, and the first delay. A fourth comparator for inputting the output of the circuit and a reference signal, a second flip-flop for inputting the output of the fourth comparator and the input signal, a second inverter for inverting the output of the second flip-flop, A third buffer having the output of the second half as an input, a second buffer having the output of the third comparator and the output of the first half as the input of the sensing unit, and a signal connected to the output of the second buffer A second delay circuit for delaying the signal; a fifth comparator for inputting the output and the reference voltage of the second delay circuit; a third flip-flop for inputting the output of the fifth comparator and the input signal; Third inversion to invert the output of the three flip flops It is composed of; The output unit is controlled by a first transistor unit controlled by the output of the third buffer of the control unit, a second transistor unit controlled by the output of the first half of the sensing unit, and controlled by the output of the third half unit of the control unit And a IGBT portion controlled by an output of the third transistor portion and the first to third transistor portions. 2. The transistor of claim 1, wherein the third transistor unit connects the output of the third inverter of the controller to the base of the first transistor 6 having the emitter grounded, and the collector is connected to the second transistor 7 through the resistor R3. The gate insulation transistor power protection circuit, characterized in that connected to the base of the). 2. The gate isolation transistor power protection circuit according to claim 1, wherein the first to third flip flops use an RS flip flop. The gate protection transistor power protection circuit of claim 1, wherein the first and second buffers use an OR gate. The reference voltage input to the first comparator is 0.75V, the reference voltage input to the second comparator is 0.5V, the reference voltage input to the third comparator is 0.6V. Gate isolation transistor power protection circuit. 2. The gate isolation transistor power protection circuit of claim 1, wherein the first delay circuit delays about 10 milliseconds and the second delay circuit delays about 5 milliseconds.