KR100234388B1 - Crystalizing method of silicon film - Google Patents
Crystalizing method of silicon film Download PDFInfo
- Publication number
- KR100234388B1 KR100234388B1 KR1019960037228A KR19960037228A KR100234388B1 KR 100234388 B1 KR100234388 B1 KR 100234388B1 KR 1019960037228 A KR1019960037228 A KR 1019960037228A KR 19960037228 A KR19960037228 A KR 19960037228A KR 100234388 B1 KR100234388 B1 KR 100234388B1
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- silicon thin
- crystallization
- seed layer
- amorphous silicon
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 21
- 239000010703 silicon Substances 0.000 title claims abstract description 21
- 239000010409 thin film Substances 0.000 claims abstract description 52
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 28
- 238000002425 crystallisation Methods 0.000 claims abstract description 21
- 230000008025 crystallization Effects 0.000 claims abstract description 19
- 239000010408 film Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000001678 irradiating effect Effects 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 15
- 239000004065 semiconductor Substances 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 6
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
Abstract
시드층을 안정적으로 제공하여 균일하고 그레인의 크기가 큰 다결정실리콘층을 얻을 수 있는 실리콘박막의 결정화 방법에 대해 기재되어 있다. 이 방법은 투명기판상에 시드층을 형성하는 단계와, 상기 시드층상에 결정화를 위한 개구부를 구비한 절연막을 형성하는 단계와, 상기 절연막상에 결정화할 비정질 실리콘박막을 형성하는 단계와, 상기 비정질 실리콘박막상에 레이저를 조사하여 이를 결정화하는 단계를 구비하여 이루어진 것을 특징으로 한다. 따라서, 결정화하려는 비정질 실리콘박막을 모두 용융시켜도 상기한 별도의 시드층에 의하여 항상 결정화를 위한 시드가 제공되므로 공정의 마아진을 크게 할 수 있음은 물론, 실리콘박막을 충분히 용융시킬 수 있으므로 다결정실리콘의 그레인 크기가 증가된다. 또한, 상기 개구부를 중심으로 결정화가 진행되므로 결정화의 위치를 조정하기 용이하며 그레인의 크기도 균일하게 되어 소자특성의 균일도를 높일 수 있게 된다.Discloses a method of crystallizing a silicon thin film in which a seed layer is provided stably to obtain a polycrystalline silicon layer which is uniform and has a large grain size. The method includes the steps of forming a seed layer on a transparent substrate, forming an insulating film having an opening for crystallization on the seed layer, forming an amorphous silicon thin film to be crystallized on the insulating film, And irradiating a laser beam onto the silicon thin film to crystallize the thin film. Therefore, even if all of the amorphous silicon thin films to be crystallized are melted, the seed for crystallization is always provided by the separate seed layer, so that the process margin can be increased and the silicon thin film can be sufficiently melted. The size is increased. Further, crystallization progresses around the opening, so that it is easy to adjust the position of the crystallization and the size of the grain becomes uniform, so that the uniformity of the device characteristics can be improved.
Description
본 발명은 실리콘박막의 결정화 방법에 관한 것으로, 특히 레이저(laser)를 이용한 실리콘박막의 결정화 방법에 관한 것이다.The present invention relates to a method for crystallizing a silicon thin film, and more particularly, to a method for crystallizing a silicon thin film using a laser.
지금까지의 표시장치(display units)의 대명사이던 음극선관(CRT: Cathode-Ray Tube)를 대신하여 저전력소모 및 경박단소화가 가능한 새로운 표시소자로서 LCD(Liquid Crystal Display), PDP(Plasma Display Panel), EL(Electro-Luminescence)등의 각종 표시장치가 개발되었는데, 그 중에서도 특히 LCD는 전기장에 의하여 분자의 배열이 변화하는 액정의 광학적 성질을 이용하는 액정기술과 반도체기슬을 융합한 대표적인 평판 표시장치이다.PDPs (Plasma Display Panels), PDPs (Plasma Display Panels), and PDPs (Plasma Display Panels) as new display devices capable of reducing power consumption and light weight and small size in place of cathode ray tubes (CRTs) Various display devices such as EL (Electro-Luminescence) have been developed. Among them, LCD is a typical flat panel display device in which liquid crystal technology that utilizes the optical properties of liquid crystal in which the arrangement of molecules is changed by an electric field is combined with semiconductor technology.
이러한 LCD의 스위칭소자로 박막트랜지스터(Thin Film Transistor; 이하, TFT로 약하여 칭함)가 사용되고 있다. 이 TFT의 채널로 사용되는 반도체층을 다결정실리콘으로 제작(이하, 다결정실리콘-TFT라 칭함)하려는 경우에, 먼저 유리기판상에 형성된 비정질 상태의 실리콘박막을 결정화해야 할 필요가 있다. 다결정실리콘-TFT의 반도체층인 다결정실리콘을 형성하는 대표적인 결정화 방법은 레이저를 이용하는 방법이다.Thin film transistors (hereinafter, abbreviated as TFTs) are used as switching elements of LCDs. When a semiconductor layer used as a channel of the TFT is made of polycrystalline silicon (hereinafter, referred to as a polycrystalline silicon TFT), it is first necessary to crystallize the amorphous silicon thin film formed on the glass substrate. A typical crystallization method for forming polycrystalline silicon which is a semiconductor layer of a polycrystalline silicon-TFT is a method using a laser.
도 1은 종래 실리콘박막의 결정화 방법을 설명하기 위한 단면도로서, 도면부호, 100은 투명기판을, 10은 상기 투명기판(100)상에 형성된 비정질 상태의 실리콘 박막을 각각 나타낸다.1 is a cross-sectional view for explaining a conventional method of crystallizing a silicon thin film, in which reference numeral 100 denotes a transparent substrate and 10 denotes a silicon thin film in an amorphous state formed on the transparent substrate 100, respectively.
상기 도 1을 참조하여 종래 실리콘박막의 결정화 방법을 설명하면, 이 방법은 단순히 레이저를 비정질의 실리콘박막에 조사하여 실리콘 박막을 일시적으로 용융 및 냉각시킴으로써 결정화를 수행한다. 이 때, 조사하는 레이저의 에너지밀도에 따라 비정질 실리콘박막의 용융정도 및 그에 따른 결정화의 상태가 변화한다.Referring to FIG. 1, a conventional method of crystallizing a silicon thin film will be described. In this method, a laser is irradiated to an amorphous silicon thin film to temporarily crystallize the silicon thin film by melting and cooling. At this time, depending on the energy density of the laser to be irradiated, the degree of melting of the amorphous silicon thin film and the state of crystallization accordingly change.
예를 들어, 레이저의 에너지 밀도를 높이면 비정질 실리콘박막은 표면으로부터 더 깊은 곳까지 용융되는데 에너지밀도가 증가할 수록 용융되는 양이 많아지며, 소정의 임계 에너지밀도 이상에서는 비정질 실리콘박막이 완전히 용융되어 버린다. 결정화되는 다결정실리콘의 그레인(grain)의 크기는 조사되는 레이저의 에너지밀도에 비례한다(즉, 비정질 실리콘박막이 많이 용융될수록 그레인 크기가 증가된다). 이는 임계 에너지 이하의 에너지밀도에서는 비정질 실리콘박막의 윗쪽(표면쪽) 만이 용융되었다가 냉각되는 과정을 통해 작은 그레인으로 결정화되는 것이며, 임계 에너지밀도에 근접한 레이저의 에너지밀도에서는 아랫쪽의 소량의 비정실 실리콘박막만 남고 나머지는 거의 용융된 상태(nearly complete melting)이므로 용융되지 않는 실리콘박막이 시드(seed)로서 작용하여, 결국 큰 그레인으로 결정화된다. 다만, 레이저의 에너지 밀도를 상기에서 언급한 임계 에너지밀도 이상으로 하여 비정질 실리콘박막이 완전히 용융되면, 시드로서 작용할 아무런 실리콘박막도 남지 않으며, 불규칙한 핵형성 및 결정성장에 의거하여 결정화가 일어나기 때문에 오히려 그레인의 크기가 감소되어 버린다.For example, if the energy density of the laser is increased, the amorphous silicon thin film is melted from the surface to a deeper place. The amount of melting is increased as the energy density is increased, and the amorphous silicon thin film is completely melted at a predetermined threshold energy density or more . The size of the grain of the polycrystalline silicon to be crystallized is proportional to the energy density of the irradiated laser (i.e., the larger the amorphous silicon thin film is, the larger the grain size is). This is because at the energy density below the critical energy, only the upper side (surface side) of the amorphous silicon thin film is melted and then crystallized into a small grain through the cooling process. In the laser energy density close to the critical energy density, The remaining thin film is almost completely melted, so that the silicon thin film which is not melted acts as a seed and eventually crystallizes to a large grain. However, if the amorphous silicon thin film is completely melted by setting the energy density of the laser to be equal to or higher than the above-mentioned critical energy density, no silicon thin film to serve as a seed remains and crystallization occurs due to irregular nucleation and crystal growth. Is reduced.
다결정실리콘-TFT는 가능한 한 그레임의 크기가 큰 다결정 실리콘층을 이용하여 제작하는 것이 유리하며, 이때문에 종래에는 레이저의 에너지밀도를 임계 에너지밀도에 가능한 한 근접하도록 하여 최소한의 시드 역할을 담당할 비정질 실리콘박막이 남도록 하는 방법을 사용하였다. 그러나, 종래의 방법에서 큰 그레인을 얻을 수 있는 에너지밀도의 구간은 매우 좁기 때문에 공정수행시의 허용가능한 마아진 (margin)의 폭이 매우 작은 어려움이 있었다.It is advantageous to fabricate a polycrystalline silicon-TFT using a polycrystalline silicon layer having a large grain size as much as possible. Therefore, conventionally, the energy density of the laser is made as close as possible to the critical energy density, A method of leaving an amorphous silicon thin film was used. However, in the conventional method, since the interval of the energy density at which a large grain can be obtained is very narrow, there is a very small allowable margins at the time of performing the process.
또한, 결정화한 다결정실리콘에 있어서 그레인이 임의로 위치하기 때문에, 이러한 조건의 결정화영역을 예컨대 TFT의 채널영역이 형성되는 반도체패턴으로 사용할 경우에는 균일한 소자특성을 확보하기 어려운 문제점이 있다. 즉, 종래의 방법에 의하면, 재결정화시에 시드로서 작용하는 용융되지 않은 영역이 재결정화 영역중에 불규칙하게 분포되게 된다. 불규칙하게 분포된 시드중에서 서로간의 거리가 소정거리 이상으로 되면, 재결정화가 원활히 이루어지지 못하게 되는 문제가 발생된다.Further, since grains are randomly located in the crystallized polycrystalline silicon, there is a problem that it is difficult to ensure uniform device characteristics when the crystallization region having such a condition is used, for example, as a semiconductor pattern in which a channel region of a TFT is formed. That is, according to the conventional method, the unfused region serving as a seed at the time of recrystallization is irregularly distributed in the recrystallized region. If the distance between the irregularly distributed seeds is more than a predetermined distance, there arises a problem that recrystallization can not be performed smoothly.
본 발명이 이루고자 하는 기술적 과제는, 상기한 바와 같은 종래기술의 문제점을 해결하기 위하여 별도의 시드층을 구비함으로써 결정화를 위한 공정상의 마아진을 크게 하는 한편, 그레인의 크기와 분포가 균일한 다결정실리콘을 제조함으로써 균일한 소자특성을 얻을 수 있도록 한 실리콘박막의 결정화 방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of fabricating a polycrystalline silicon having a uniform grain size and distribution, And to provide a method of crystallizing a silicon thin film which can obtain uniform device characteristics.
제1도는 종래 실리콘박막의 결정화 방법을 설명하기 위한 단면도,FIG. 1 is a cross-sectional view for explaining a conventional silicon thin film crystallization method,
제2a도 내지 제2c는 본 발명에 따른 실리콘박막의 결정화 방법을 설명하기 위한 공정순서도.FIGS. 2 (a) to 2 (c) are process flow diagrams illustrating a method of crystallizing a silicon thin film according to the present invention. FIG.
제3도는 박막트렌지스터의 채널이 형성되는 영역의 결정성을 조절하기 위한 개구부의 배열예를 나타낸 도면.FIG. 3 is a view showing an example of arrangement of openings for controlling the crystallinity of a region where a channel of a thin film transistor is formed; FIG.
상기 과제를 이루기 위하여 본 발명에 의한 실리콘박막의 결정화 방법은, 기판상에 실리콘막을 증착하여 시드층을 형성하는 단계와, 상기 시드층상에, 상기 시드층의 일부를 노출시키는 개구부를 구비한 절연막을 형성하는 단계와, 상기 시드층의 노출된 영역과 상기 절연막을 덮도록 결정화할 비정질 실리콘막을 형성하는 단계, 및 상기 비정질 실리콘박막에 레이저를 조사하여 상기 비정질 실리콘박막을 결정화하는 단계를 구비하여 이루어진다.According to another aspect of the present invention, there is provided a method of crystallizing a silicon thin film, comprising: forming a seed layer by depositing a silicon film on a substrate; forming an insulating film on the seed layer, Forming an amorphous silicon film to be crystallized so as to cover the exposed region of the seed layer and the insulating film; and crystallizing the amorphous silicon thin film by irradiating a laser beam onto the amorphous silicon thin film.
본 발명에 의한 실리콘박막의 결정화 방법에 의하면, 결정화하려는 비정질 실리콘박막을 모두 용융시켜도 상기한 별도의 시드층에 의하여 항상 결정화를 위한 시드가 제공되므로 공정의 마아진을 크게 할 수 있음은 물론, 실리콘박막을 충분히 용융시킬 수 있으므로 다결정실리콘의 그레인 크기가 증가된다. 또한, 상기 개구부를 중심으로 결정화가 진행되므로 결정화의 위치를 조정하기 용이하며, 그레인의 크기도 균일하게 되어소자특성의 균일도를 높일 수 있게 된다.According to the method for crystallizing a silicon thin film according to the present invention, even if all of the amorphous silicon thin films to be crystallized are melted, the seed for crystallization is always provided by the separate seed layer, so that the process margin can be increased, The grain size of the polycrystalline silicon is increased. Further, crystallization progresses around the opening, so that the position of crystallization can be easily adjusted, the size of the grain can be uniform, and the uniformity of device characteristics can be improved.
이하, 첨부한 도면을 참조하여 본 발명을 설명하기로 한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 실리콘박막의 결정화 방법을 설명하기 위한 공정순서도로서, 도 1에 도시된 구성요소와 동일한 구성요소에 대해서는 동일한 도면부호를 붙이고 그 설명은 생략하기로 한다.2A to 2C are flow charts for explaining a method of crystallizing a silicon thin film according to the present invention. The same constituent elements as those shown in FIG. 1 are denoted by the same reference numerals, and a description thereof will be omitted.
도 2a는 시드층(20)의 형성공정을 도시한 것으로, 투명기판(100)상에 예컨대 비정질 실리콘박막 혹은 다결정실리콘막을 소정 두께 증착하여 시드층(20)을 형성한다.2A illustrates a process of forming the seed layer 20. A seed layer 20 is formed on the transparent substrate 100 by depositing a predetermined thickness of, for example, an amorphous silicon thin film or a polysilicon thin film.
도 2b는 절연막(22) 및 개구부(30)의 형성공정을 도시한 것으로, 먼저 상기 시드층(20)위에 절연막(22) 예컨대 산화막을 소정 두께로 증착한 후, 이 절연막(22)에 대하여 통상의 사진식각공정을 실시함으로써, 상기 시드층(20)의 일부를 노출시키는 개구부(30)를 형성한다.2B shows a process of forming the insulating film 22 and the opening 30. Firstly, an insulating film 22 such as an oxide film is deposited on the seed layer 20 to a predetermined thickness, The opening 30 for exposing a part of the seed layer 20 is formed.
도 2c는 반도체층(24)의 형성공정을 도시한 것으로, 상기 개구부가 형성된 결과물 전면에 예컨대 비정질 실리콘박막을 소정 두께로 증착하여 결정화할 반도체층(24)을 형성한다.FIG. 2C shows a process of forming the semiconductor layer 24, and a semiconductor layer 24 to be crystallized is formed by depositing, for example, an amorphous silicon thin film to a predetermined thickness on the entire surface of the resultant formed with the openings.
다음으로, 상기 비정질 실리콘박막(24)에 레이저를 조사하여 상기 비정질 실리콘박막(24)을 결정화한다. 이때, 조사하는 레이저의 에너지밀도를 상기 비정질 실리콘박막(24)이 완전히 용융되는 임계 에너지밀도 이상으로 하는 경우에도, 상기 절연막(22)의 하부에 위치하는 시드층(20)이 시드로 작용하기 때문에 개구부를 중심으로 상기 비정질 실리콘박막(24)이 다결정실리콘으로 결정화된다.Next, the amorphous silicon thin film 24 is irradiated with a laser to crystallize the amorphous silicon thin film 24. At this time, even when the energy density of the laser to be irradiated is made equal to or higher than the critical energy density at which the amorphous silicon thin film 24 is completely melted, the seed layer 20 located under the insulating film 22 acts as a seed The amorphous silicon thin film 24 is crystallized into polycrystalline silicon around the opening.
즉, 종래의 방법에서는 조사하는 레이저의 에너지밀도를 엄정하게 제어하여 시드로 작용할 최소량의 비정질 실리콘박막이 남도록 해야만 하였으나, 본 발명에 의하면 결정화하려는 상기 비정질 실리콘박막(24)이 완전히 용융되어도 상기 시드층(20)에 의해 결정화가 안정적으로 진행되며, 이에 따라 공정상의 허용 마아진이 대폭적으로 향상된다.That is, in the conventional method, the energy density of the laser to be irradiated is strictly controlled so that a minimum amount of amorphous silicon thin film to serve as a seed remains. However, according to the present invention, even if the amorphous silicon thin film 24 to be crystallized is completely melted, The crystallization progresses stably by the heat treatment section 20, thereby greatly improving the permissible margin of the process.
또한, 상기 비정질 실리콘박막(24)을 충분히 용융시키므로 그레인의 크기도 종래의 방법에 비하여 증가된다.Further, since the amorphous silicon thin film 24 is sufficiently melted, the grain size is increased as compared with the conventional method.
한편, 본 발명에 의하면 상기 도 2c에서 알 수 있는 바와 같이 결정화가 상기 절연막(22)의 개구부를 중심으로 진행되므로 개구부의 배열을 조절하여 결정화를 자유롭게 조절할 수 있다. 상기 개구부 주변의 그레인의 크기 분포는 조사되는 레이저의 에너지밀도는 물론 개구부의 크기와 모양등에 따라 변화한다. 따라서, 개구부의 크기와 모양, 및 수와 배열등을 조절하여 결정화를 조절할 수 있게 된다. 예를 들어, TFT의 경우에 소자의 특성에 가장 큰 영향을 미치는 부분은 채널이 형성되는 영역인 바, 이 부근에 상기 개구부를 적절히 배치하면 균일한 그레인의 다결정실리콘을 형성할 수 있게 된다.According to the present invention, as shown in FIG. 2C, since the crystallization proceeds around the opening of the insulating film 22, the crystallization can be freely controlled by adjusting the arrangement of the openings. The size distribution of the grain around the opening varies depending on the size and shape of the opening as well as the energy density of the laser to be irradiated. Therefore, the crystallization can be controlled by controlling the size and shape of the openings, and the number and arrangement thereof. For example, in the case of a TFT, a portion having the greatest influence on the characteristics of a device is a region where a channel is formed. If the opening is appropriately disposed in the vicinity of the channel, polycrystalline silicon of uniform grain can be formed.
도 3은 TFT의 채널이 형성되는 영역의 결정성을 조절하기 위하여 상기 절역막(22)상의 개구부의 배열예를 나타낸 도면으로, 도면부호 30은 반도체층의 박막패턴을 나타내고, 35는 게이트전극의 패턴을 나타낸다. 또한, 도면부호 d는 개구부간의 거리를 나타낸다.3 is a view showing an example of arrangement of openings on the trimming film 22 in order to control the crystallinity of the region where the channel of the TFT is formed. In FIG. 3, reference numeral 30 denotes a thin film pattern of the semiconductor layer, Pattern. Also, reference numeral "d" denotes the distance between the openings.
도 3을 참조하면, 상술한 바와 같이 TFT의 채널은 상기 반도체층의 박막패턴(30)과 게이트전극의 패턴(35)이 교차하는 영역에 형성되며, 본 발명에서는 도 3에 도시한 바와 같이 TFT의 채널이 형성되는 영역에 간격(d)로 배열된 개구부를 설치하여, 모든 채널영역이 시드의 영향하에 재결정화되도록 함으로써, 일정한 그레인 크기를 갖는 다결정실리콘으로 결정화할 수 있게 된다. 즉, 비정질 실리콘박막의 결정화는 상기 개구부를 중심으로 진행되며, 이에 따라 TFT의 채널영역은 균일하고, 그레인의 크기가 큰 다결정실리콘으로 결정화된다.3, the channel of the TFT is formed in a region where the thin film pattern 30 of the semiconductor layer and the pattern 35 of the gate electrode cross each other, as described above. In the present invention, It is possible to crystallize polycrystalline silicon having a constant grain size by providing openings arranged in the region where the channels of the channel region are formed with intervals d so that all the channel regions are recrystallized under the influence of the seed. That is, the crystallization of the amorphous silicon thin film proceeds around the opening, whereby the channel region of the TFT is uniform and crystallized into polycrystalline silicon having a large grain size.
상술한 본 발명에 의하면, 결정화할 영역을 충분히 용융시킨 상태에서의 결정화가 가능하므로 공정상의 허용 마아진이 확대되고 결정화된 다결정실리콘의 그레인이 종래에 비하여 확대되는 효과를 얻을 수 있다.According to the present invention described above, since the crystallization can be performed in a state in which the region to be crystallized is sufficiently melted, the allowable margin in the process can be enlarged and the effect of enlarging the grain size of the crystallized polycrystalline silicon can be obtained.
또한, 균일하고 집중적인 결정화가 필요한, 예컨대 TFT의 채널영역과 같은 영역에 대해서 시드층을 제공하기 위한 개구부를 적절히 배치함으로써 결정화의 균일도를 높일 수 있으며, 이로써 제작이 완료된 소자들에 있어서 균일한 소자특성을 확보할 수 있게 된다.In addition, it is possible to increase the uniformity of the crystallization by appropriately arranging the openings for providing the seed layer for the region such as the channel region of the TFT which requires uniform and intensive crystallization, for example, Characteristics can be secured.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960037228A KR100234388B1 (en) | 1996-08-30 | 1996-08-30 | Crystalizing method of silicon film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960037228A KR100234388B1 (en) | 1996-08-30 | 1996-08-30 | Crystalizing method of silicon film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980017448A KR19980017448A (en) | 1998-06-05 |
| KR100234388B1 true KR100234388B1 (en) | 1999-12-15 |
Family
ID=19472001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960037228A KR100234388B1 (en) | 1996-08-30 | 1996-08-30 | Crystalizing method of silicon film |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100234388B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100482461B1 (en) * | 1998-10-28 | 2005-09-02 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing polysilicon thin film transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02194522A (en) * | 1989-01-23 | 1990-08-01 | Fuji Electric Co Ltd | Manufacture of soi substrate |
| JPH04186722A (en) * | 1990-11-20 | 1992-07-03 | Seiko Epson Corp | Manufacture of crystalline semiconductor thin film |
-
1996
- 1996-08-30 KR KR1019960037228A patent/KR100234388B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02194522A (en) * | 1989-01-23 | 1990-08-01 | Fuji Electric Co Ltd | Manufacture of soi substrate |
| JPH04186722A (en) * | 1990-11-20 | 1992-07-03 | Seiko Epson Corp | Manufacture of crystalline semiconductor thin film |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980017448A (en) | 1998-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6755909B2 (en) | Method of crystallizing amorphous silicon using a mask | |
| KR100698056B1 (en) | Laser Beam Pattern Mask and the Method for Crystallization with the Same | |
| US7507645B2 (en) | Method of forming polycrystalline semiconductor layer and thin film transistor using the same | |
| US7781765B2 (en) | Mask for crystallizing polysilicon and a method for forming thin film transistor using the mask | |
| US5888839A (en) | Method of manufacturing semiconductor chips for display | |
| US7927936B2 (en) | Laser mask and crystallization method using the same | |
| GB2338343A (en) | Method for fabricating thin film transistor | |
| US6686978B2 (en) | Method of forming an LCD with predominantly <100> polycrystalline silicon regions | |
| US7384476B2 (en) | Method for crystallizing silicon | |
| US7700892B2 (en) | Sequential lateral solidification device and method of crystallizing silicon using the same | |
| KR100269312B1 (en) | Method for crystallization of silicon film and fabricating method for thin film transistor-liquid crystal display using the same | |
| US7767558B2 (en) | Method of crystallizing amorphous silicon and device fabricated using the same | |
| US6396560B1 (en) | Method of producing liquid crystal display panel | |
| KR100234388B1 (en) | Crystalizing method of silicon film | |
| KR100484399B1 (en) | mask for silicon crystallization and silicon crystallization method | |
| KR100238211B1 (en) | Crystallization method for silicon film | |
| KR100525443B1 (en) | Device for Crystallization and method for Crystallization with the same | |
| US7026201B2 (en) | Method for forming polycrystalline silicon thin film transistor | |
| KR19980060717A (en) | Crystallization Method of Silicon Thin Film | |
| US7696449B2 (en) | Silicon crystallizing device | |
| US6607971B1 (en) | Method for extending a laser annealing pulse | |
| KR100243276B1 (en) | Manufacturing method of polysilicon thin film using laser annealing and the manufacturing method of thin film transistor using the same | |
| KR20020005815A (en) | Method for crystallizing amorphous silicon thin film using electron beam for liquid crystal display | |
| KR20010000607A (en) | Method for crystallizing amorphous silicon thin film | |
| KR20040000185A (en) | a thin film transistor array panel and a fabricating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20070827 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |