KR100234370B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100234370B1 KR100234370B1 KR1019970006242A KR19970006242A KR100234370B1 KR 100234370 B1 KR100234370 B1 KR 100234370B1 KR 1019970006242 A KR1019970006242 A KR 1019970006242A KR 19970006242 A KR19970006242 A KR 19970006242A KR 100234370 B1 KR100234370 B1 KR 100234370B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000011810 insulating material Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000005121 nitriding Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000002209 hydrophobic effect Effects 0.000 claims description 4
- 239000002002 slurry Substances 0.000 claims description 4
- 125000002887 hydroxy group Chemical group [H]O* 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 229910000077 silane Inorganic materials 0.000 description 6
- 238000005498 polishing Methods 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
반도체 기판상에 소정 패턴을 형성하고, 상기 결과물상에 제1 절연막을 형성하고, 상기 제1 절연막의 단차가 높은 영역상에만 선택적으로 친수성막(hydrophilic layer)을 형성한 후, 상기 결과물상에 소수성(hydrophobicity)을 띠는 유기계 절연 물질을 이용하여 제2 절연막을 형성하는 것을 특징으로 하는 반도체 장치의 평탄화 방법이 개시된다.A predetermined pattern is formed on the semiconductor substrate, a first insulating film is formed on the resultant, and a hydrophilic layer is selectively formed only on a region where the step height of the first insulating film is high. Disclosed is a method of planarizing a semiconductor device, wherein the second insulating film is formed using an organic insulating material having hydrophobicity.
본 발명에 의하면, 반도체 장치의 글로벌 평탄화를 달성할 수 있다.According to the present invention, global planarization of a semiconductor device can be achieved.
Description
본 발명은 반도체 장치의 평탄화 방법에 관한 것으로 특히, 하지막 의존성을 갖는 물질을 이용하는 반도체 장치의 글로벌 평탄화를 달성하는 방법에 관한 것이다.The present invention relates to a planarization method of a semiconductor device, and more particularly, to a method for achieving global planarization of a semiconductor device using a material having underlying film dependence.
반도체 소자가 고집적화 됨에 따라 사진 식각 공정의 마진을 확보하고 배선 길이를 최소화하기 위해 하부 구조를 평탄화시키는 기술이 한층 중요해지고 있다. 평탄도를 높이기 위한 방법으로는 BPSG 리플로우 (borophosphosilicate glass reflow), 알루미늄 리플로우, 스핀 온 글라스(spin on glass: SOG), 에치백(etch back) 및 화학 기계적 폴리싱(chemical mechanical polishing: CMP)등의 방법이 있다.As semiconductor devices are highly integrated, technology for flattening the underlying structure is becoming more important in order to secure a margin of a photolithography process and minimize wiring length. Methods to improve flatness include BPSG reflow (borophosphosilicate glass reflow), aluminum reflow, spin on glass (SOG), etch back and chemical mechanical polishing (CMP). There is a way.
CMP공정은 슬러리(slurry)와 패드의 마찰력을 이용하여 글로벌(global)평탄화를 달성하는 방법으로서 리플로우 공정이나 에치백 공정으로는 달성하기 힘든 글로벌 평탄화 및 저온 평탄화를 이룰 수 있어 차세대 평탄화 기술로 주목받고 있다.CMP process is a method to achieve global leveling by using friction between slurry and pad.As a next-generation planarization technology, it is possible to achieve global planarization and low temperature planarization which cannot be achieved by reflow process or etchback process. I am getting it.
일반적으로, 반도체 소자는 소정의 패턴 사이즈, 패턴 밀도 및 패턴 단차를 가지고 있는데, CMP공정에 의해 달성되는 평탄도는 폴리싱되는 막의 하부에 형성된 패턴의 밀도가 높을수록, 패턴 단차가 낮을수록, 패턴 사이즈가 작을수록 높아진다. 특히, 폴리싱되는 막이 하부 패턴의 단차로 인해 불량한 평탄도를 갖는 경우에는 CMP공정 후에 폴리싱된 막의 특정 부위가 오목해지는 디싱(dishing) 현상이 발생된다.In general, semiconductor devices have a predetermined pattern size, pattern density, and pattern step. The flatness achieved by the CMP process is characterized by the higher the density of the pattern formed under the film to be polished, the lower the pattern step, and the pattern size. The smaller is, the higher. In particular, when the film to be polished has poor flatness due to the step difference of the lower pattern, dishing phenomenon occurs in which a specific portion of the polished film becomes concave after the CMP process.
이러한 디싱(dishing)현상은 후속 공정에서 공정 결함을 유발하여 반도체 소자의 신뢰성을 저하시키므로, 이를 방지하기 위해서 우수한 평탄도 특성을 갖는 절연막을 형성할 필요가 있다.Such dishing causes process defects in subsequent processes, thereby lowering the reliability of the semiconductor device. Therefore, it is necessary to form an insulating film having excellent flatness characteristics in order to prevent this.
본 발명의 기술적 과제는 하지막 의존성을 갖는 물질을 이용하여 반도체 장치의 평탄화 방법을 제공하는 것이다.An object of the present invention is to provide a planarization method of a semiconductor device using a material having an underlying film dependency.
도 1a 내지 도 1c는 본 발명에 따른 반도체 장치의 평탄화 방법을 도시하는 단면도들이다.1A to 1C are cross-sectional views showing a planarization method of a semiconductor device according to the present invention.
본 발명의 기술적 과제를 달성하기 위하여 반도체 기판상에 소정 패턴을 형성하고, 상기 결과물상에 제1 절연막을 형성하고, CMP 공정을 실시하여 상기 제1 절연막의 단차가 높은 영역상에만 선택적으로 친수성막(hydrophilic layer)을 형성하고, 상기 결과물상에 하지막 의존성을 갖는 유기계 절연 물질을 증착하여 제2 절연막을 형성한다.In order to achieve the technical object of the present invention, a predetermined pattern is formed on a semiconductor substrate, a first insulating film is formed on the resultant product, and a CMP process is performed to selectively select a hydrophilic film only on a region having a high step height of the first insulating film. (hydrophilic layer) is formed, and an organic insulating material having underlying film dependency is deposited on the resultant to form a second insulating film.
상기 제1 절연막은 P-SiH4산화막(plasma based SiH4oxide), 실리콘 질화막(SiN), P-TEOS USG 또는 O3-TEOS USG으로 형성되는 것이 바람직하다.The first insulating layer is preferably formed of a P-SiH 4 oxide (plasma based SiH 4 oxide), silicon nitride (SiN), P-TEOS USG or O 3 -TEOS USG.
상기 제2 절연막은 O3-TEOS USG 또는 O3-HMDS USG로 형성되는 것이 바람직하다.The second insulating layer is preferably formed of O 3 -TEOS USG or O 3 -HMDS USG.
이하, 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail.
실란(SiH4)등을 반응 물질로 하는 경우에는 절연막의 단차 도포성(step coverage) 및 평탄도 특성이 불량한 반면, TEOS(Tetraethyl- orthosilicate: Si(OC2H5)4)와 같은 유기계 절연 물질로 절연막을 형성하는 경우에는 우수한 단차 도포성 및 평탄도 특성을 얻을 수 있다.In the case of using silane (SiH 4 ) as a reactive material, an organic insulating material such as TEOS (Tetraethyl- orthosilicate: Si (OC 2 H 5 ) 4 ) is poor while the step coverage and flatness characteristics of the insulating film are poor. In the case of forming the insulating film, excellent step coatability and flatness characteristics can be obtained.
즉, 실란(SiH4)을 반응 물질로 하는 종래의 절연막 형성 공정은 플라즈마중에서 실란(SiH4)과 산소가 반응하여 SiO2분자가 생성된 후 이것이 기판상에 퇴적되는 반면에, TEOS는 유동성을 가지고 단차부에서 흘러내리므로 평탄도가 우수한 절연막이 얻어진다.That is, in the conventional insulating film forming process using silane (SiH 4 ) as a reaction material, silane (SiH 4 ) reacts with oxygen in a plasma to form SiO 2 molecules, which are then deposited on a substrate, whereas TEOS is fluid. Since it flows in the stepped portion, an insulating film excellent in flatness is obtained.
한편, 유기계 절연 물질은 하지(下地) 의존성 즉, 친수성(hydrophilicity)을 띠는 하지막상에서는 증착 속도가 느리고 소수성(hydrophobicity)을 띠는 하지막상에서는 상대적으로 증착 속도가 높은 성질을 갖고 있다.On the other hand, the organic insulating material has a property of having a slow deposition rate on a base film having hydrophilicity, and a relatively high deposition rate on a hydrophobic base film having a hydrophilicity.
따라서, 단차가 높은 하지막상에는 친수성막(hydrophilic layer)을 형성하여 그 상부에 형성되는 절연막의 증착 속도를 낮추고, 단차가 낮은 하지막상에는 소수성막(hydrophobic layer)을 형성하여 그 상부에 형성되는 절연막의 증착 속도를 높이면 우수한 평탄도 특성을 갖는 절연막을 얻을 수 있다.Therefore, a hydrophilic layer is formed on the base film having a high level of step, thereby lowering the deposition rate of the insulating film formed thereon, and a hydrophobic layer is formed on the base film having a low level, and formed on the top layer. By increasing the deposition rate of the insulating film having an excellent flatness characteristics can be obtained.
이와 같은 유기계 절연 물질의 하지 의존성은 질화 처리(nitridation) 공정을 수행함으로써 제거될 수 있다.The base dependence of the organic insulating material may be removed by performing a nitriding process.
도 1a 내지 도 1c는 본 발명의 일 실시예를 설명하기 위한 단면도들이다.1A to 1C are cross-sectional views illustrating an embodiment of the present invention.
도 1a는 소정의 패턴(102)이 형성된 반도체 기판(100)상에 제1 절연막(104)을 증착한 결과를 도시한다.FIG. 1A illustrates a result of depositing a first
먼저, 소정의 패턴(102)이 형성된 반도체 기판(100)상에 질화 처리(nitridation)를 행한다. 이때, 상기 질화 처리 공정은 NH3플라즈마 가스를 이용하여 수행할 수 있다. 상기 질화 처리 공정은 후속 공정에서 형성되는 제1 절연막(104)의 하지 의존성을 제거하기 위한 것이며, 제1 절연막(104)의 하지 의존성이 문제되지 않는 경우에는 생략할 수 있다.First, nitriding is performed on the
이어서, 상기 결과물상에 O3-TEOS USG(undoped silicate glass)로 이루어진 제1 절연막(104)을 형성한다. 상기 O3-TEOS USG는 상압(atmospheric pressure)하의 오존(O3) 분위기에서 TEOS(tetraethylorthosilicate)를 반응 물질로 하여 화학 기상 증착(chemical vapor deposition: CVD)법으로 형성한다. 이때, 하부 패턴이 단차를 가지므로, 그 상부에 형성된 상기 제1 절연막(104) 또한 어느 정도의 단차를 갖는다. 즉, 상기 제1 절연막(104)은 상기 패턴(102)이 형성된 영역에서는 높은 단차를 갖고 상기 패턴(102)이 형성되지 않은 영역에서는 낮은 단차를 갖게된다.Subsequently, a first insulating
상기 제1 절연막(104)은 P-SiH4산화막(plasma based-silane oxide), 실리콘 질화막(SiN) 또는 P-TEOS USG(plasma based TEOS USG)으로도 형성할 수 있다.The first
상기 P-SiH4산화막(plasma based-silane oxide)은 산화성 가스 분위기에서 실란(SiH4)을 반응 물질로 하여 플라즈마 화학 기상 증착법으로 형성하며, P-TEOS USG는 불순물을 첨가하지 않은 상태에서 TEOS(tetraethyl -orthosilicate)를 반응 물질로 하여 산화성 가스 분위기의 플라즈마 화학 기상 증착법으로 형성한다.The P-SiH 4 oxide film (plasma based-silane oxide) is formed by plasma chemical vapor deposition using silane (SiH 4 ) as a reactant in an oxidizing gas atmosphere, and P-TEOS USG is formed of TEOS (without addition of impurities). Tetraethyl-orthosilicate) is used as a reactant and is formed by plasma chemical vapor deposition in an oxidizing gas atmosphere.
도 1b는 CMP공정을 이용하여 상기 제1 절연막(104)을 선택적으로 폴리싱한 결과를 도시한다.FIG. 1B shows a result of selectively polishing the first
상기 결과물에 대하여 OH기를 포함한 슬러리(slurry)를 이용하여 CMP 공정을 실시한다. 이때, 상기 CMP 공정은 단차가 높은 영역에 위치한 제1 절연막(104)의 상부만을 선택적으로 식각하여 CMP 폴리싱층(106)을 형성한다.상기 CMP 공정은 OH기를 포함한 슬러리를 이용하므로, 상기 CMP 폴리싱층(106)은 친수성을 갖게 된다.The resultant is subjected to a CMP process using a slurry containing OH groups. In this case, the CMP process selectively etches only the upper portion of the first
도 1c는 상기 결과물상에 O3-TEOS USG로 이루어진 제2 절연막(108)을 형성한 결과를 도시한다.FIG. 1C shows a result of forming a second
상기 결과물상에 상압(atmospheric pressure)하의 오존(O3) 분위기에서 화학 기상 증착법(CVD)으로 TEOS(tetraethylorthosilicate)를 상기 결과물상에 증착하여 O3-TEOS USG로 이루어진 제2 절연막(108)을 형성한다.Tetraethylorthosilicate (TEOS) is deposited on the resultant by chemical vapor deposition (CVD) in an ozone (O 3 ) atmosphere under atmospheric pressure on the resultant to form a second
상기 TEOS는 소수성을 갖고 있으므로 친수성을 띠는 상기 CMP 폴리싱층(106)상에서는 느린 속도로 증착된다. 따라서, 상기 제2 절연막(108)은 단차가 높은 영역상에는 얇게 형성되고 단차가 낮은 영역상에는 상대적으로 두껍게 형성되어 우수한 평탄도 특성을 나타낸다.Since the TEOS is hydrophobic, it is deposited at a slow rate on the hydrophilic
여기서, 상기 제2 절연막(108)은 O3-HMDS USG로도 형성할 수 있으며, 상기 O3-HMDS USG는 하지 의존성을 갖는 유기계 절연 물질인 HMDS(hexamethyldisilazane)을 반응 물질로 하여 상압(atmospheric pressure)하의 오존(O3) 분위기에서 화학 기상 증착법(chemical vapor deposition: CVD)으로 형성한다.Here, the second
한편, 도시되지는 않았으나, 상기 제2 절연막(108)상에 P-TEOS 산화막 또는 통상의 실리콘 산화막을 증착한 후 CMP 공정을 실시하면, CMP 공정시에 일반적으로 야기되는 디싱(dishing) 현상은 발생되지 않는다.Although not shown, when a CMP process is performed after depositing a P-TEOS oxide film or a conventional silicon oxide film on the second
본 발명에 의하면, 넓은 범위에 이르는 글로벌 평탄화를 달성할 수 있다.According to the present invention, global flattening over a wide range can be achieved.
본 발명은 상기 실시예에 한정되지 않으며 본 발명의 기술적 범위내에서 당업자에 의해 다양하게 변형될 수 있다.The present invention is not limited to the above embodiments and can be variously modified by those skilled in the art within the technical scope of the present invention.
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