KR100230910B1 - Viterbi decoder for hdtv - Google Patents

Abstract

The present invention relates to a Viterbi decoder of a high-definition television that enables the eight-state Viterbi decoder and the four-state Viterbi decoder used in the GA standard HDTV receiver to be reconstituted as one Viterbi decoder.

According to the present invention, when the state transition table for the four-state Viterbi decoder is extended to eight states when the NTSC interference cancellation filter is not used, the state transition is the same except for the state transition table and the channel symbol for the eight-state Viterbi decoder. This means that the structure of the Viterbi decoder of 8 states is the same as that of the 8 state extended to 8 state, and only the branch metric computing device is different. By changing, one Viterbi decoder can be used as a four-state and eight-state Viterbi decoder.

Description

Viterbi decoder of high definition TV

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi Decoder for high definition television (hereinafter referred to as HDTV). In particular, the present invention relates to an 8-state Viterbi decoder and a 4-state beater used in a HDTV receiver of a GA (Grand Alliance) standard. A Viterbi decoder of a high definition television that enables a non-decoder to be implemented as one Viterbi decoder.

Recently, the digital transmission system proposed by the US GA for terrestrial broadcasting adopts NTSC interference cancellation filter and trellis coding to maximize the service area. The reason for using the NTSC interference cancellation filter is to reduce NTSC interference in HDTV receivers as the GA standard HDTV system receives coexisting channel interference by sharing channels with existing NTSC broadcasting.

However, the use of the NTSC interference cancellation filter reduces the performance of white noise by about 3.5dB compared to the case where the NTSC interference cancellation filter is not used. As a result, GA used the NTSC interference cancellation filter only when the degree of NTSC interference was large. Otherwise, the NTSC interference cancellation filter was not used.

By deciding the standard, the HDTV receiver requires an 8-state Viterbi decoder when the NTSC interference cancellation filter is used to decode the trellis coded signal, and a 4-state Viterbi decoder when the NTSC interference cancellation filter is not used. It became.

Accordingly, there is a problem in that the hardware is complicated and the cost is increased by separately configuring the 8-state Viterbi decoder and the 4-state Viterbi decoder.

The present invention is to solve this problem, an 8-state Viterbi that can be used when the NTSC interference cancellation filter is not used while having the same state transition as the 8-state Viterbi decoder required when the NTSC interference cancellation filter is used. It is an object of the present invention to provide a Viterbi decoder of high definition television that implements a decoder so that two decoders can be made into one decoder.

Viterbi decoder of the high-definition television according to the present invention for achieving this object is an adder for adding a received symbol and a reference symbol, and an adder / subtracter for adding 8 or subtracting 8 to the output of the adder according to a sign bit. And comparing the magnitudes of the outputs of the adder and the output of the adder / subtracter, respectively, with the magnitudes of the outputs of the first and second squares, and outputting a selection signal to select a smaller value. And an NTSC interference cancellation filter in a branch metric computing device for an 8-state Viterbi decoder composed of a multiplexer for selecting and outputting the output of the first or second square part according to the selection signal of the comparator. According to the bit further comprising a switching unit for controlling the addition unit and the addition / subtraction unit may implement a four-state and eight-state Viterbi decoder as one Viterbi decoder It is characterized by a lock.

1 is a block diagram illustrating a four-state grid encoder used in a general HDTV system.

2 is a state transition table for a typical four-state Viterbi decoder.

3 is a state transition table for a typical eight-state Viterbi decoder.

4 is a block diagram of a branch metric computing device for implementing the Viterbi decoder of FIG.

5 is a block diagram of an 8-state grid encoder outputting the same symbol as the grid encoder of FIG.

6 is a state transition table for the lattice encoder of FIG.

7 is a block diagram of a branch metric computing device for a Viterbi decoder according to the present invention.

8 shows reference symbols used in FIG. 7. FIG.

* Explanation of symbols for main parts of the drawings

21: Adder 22: Adder / Subtracter

23, 24: 1st, 2nd square part 25: comparison part

26: switching unit

First, prior to describing the present invention, a general background for implementing the present invention will be described.

FIG. 1 is a block diagram illustrating a lattice coder necessary for implementing a conventional four-state Viterbi decoder. Two memories S0 delaying 12 symbols for the remaining lower 1 bit without encoding the upper 1 bit. Through the convolutional encoder of (S1), 2 bits of coded bits having a state number of 4 are changed, and 3 bits of the upper 1 bit and the encoded lower 2 bits are one of eight symbols through the mapper (1). It is selected and output.

The relationship between the state transition and the input and the channel symbol for the grid encoder may be represented by a state transition table as shown in FIG. The names of the states of this state transition table represent the states of memories S0 and S1 of the grid encoder in decimal. For example, state 2 means that S1 has 1 and S0 has 0 in the memory of the grid encoder.

In the state transition table, the input is a decimal representation of the inputs a1 and a2 of the grid encoder. For example, input 2 means that a1 has 1 and a2 has 0 in the grid encoder. The method of reading the state transition table is as follows.

If the current state of the grid encoder of FIG. 1 is 1 and the input is 3, the next state is 0 and the channel symbol is 5. If the current state is 3 and the channel symbol is -1, the previous state is 2 and the input is 1.

The four-state Viterbi decoder when the NTSC interference cancellation filter is not used can be designed using the information of the state transition table of FIG.

On the other hand, the Viterbi decoder by GA is composed of a module for calculating the metric and a module for determining the output. When the state transition is possible for each state, the module that calculates the metric has the smallest value among the sum of the metric value of the transition state and the distance between the channel symbols and the received symbol. Determined by the metric.

The process of calculating the metric is as follows.

Equation (1) can be changed as follows to reduce the amount of calculation.

The state transition table of FIG. 2 shows that i, j = 0,1,2,3, k = 1,2.

For j, there are two states that can be transitioned for each state, so we only need to calculate it twice.

On the other hand, when the NTSC interference cancellation filter is used, the 8-state Viterbi decoder can be designed using a method of designing a Viterbi decoder for 1-D channel.

In this case, since the value of memory D (delay) in the NTSC interference cancellation filter is unknown, a Viterbi decoder which treats this as a new state is also required.

FIG. 3 shows a state transition table for an 8 state Viterbi decoder when NTSC interference cancellation filter is used. The relationship between state transition including memory D and input and channel symbols is different from that of the memory of the grid encoder. The states obtained by combining the state of the grid encoder and the state of memory D in the NTSC interference cancellation filter are named in order from 0 to 7, irrespective of the state.

In the state transition table for the 8-state Viterbi decoder, a2 is encoded using a difference code among the inputs of the lattice encoder, and then combined with a1 to be displayed in decimal.

As shown in FIG. 3, the values of i, j, and k are i, j = 0,1, ........ 7, k = 1, 2, 3 when the metric is calculated. Therefore, three calculations are required to calculate the branch metric for each state transition. In other words, for each state transition, three blocks are needed to calculate the branch metric.

However, when k is 1 and 3, it has the same high input bit. The corresponding channel symbols are separated by 8 and +8, respectively, for the channel symbols of k. In this case, it is possible to decode using only a value close to the received symbol, without having to distinguish when k is 1 and k is 3.

r> s _ij2 if r is closer to _ij3 s (s = _ij2 +8) _ij1 than s (s = -8 _ij2). Conversely, if r <s _ij2, r is closer to s _ij1 than s _ij3 . Therefore, if only the sign of rs _ij2 is known, a value close to r of s _ij1 and s _ij3 can be determined.

The equation for calculating the branch metrics for the 8 states of the Viterbi decoder in case of using the NTSC interference cancellation filter is as follows.

Here, sgn (x) is +1 if x> 0, 0 if x = 0, and -1 if x <0.

By changing the formula for calculating the branch metric to (3), the blocks needed to calculate the branch metric can be reduced from three to two.

4 is a block diagram for calculating the excitation metric that implements equation (3) as a circuit, and includes an adder 11 that adds a received symbol and a reference symbol. An adder / subtracter 12 that adds or subtracts 8 to the output of the adder 11 according to a sign-bit, and the output and adder / subtracter 12 of the adder 11 Select to select a smaller value by comparing the magnitudes of the outputs of the first and second squares 13, 14 and the outputs of the first and second squares 13, 14, respectively, squared A comparator 15 for outputting a signal and a multiplexer MUXO for selecting and outputting the outputs of the first or second squares 13 and 14 according to the selection signal of the comparator 15. Consists of

A case of calculating the branch metric in the case where the operation of the conventional branch metric calculation circuit of the above configuration transitions from the state j to the state I will be described as an example.

First, the adder 11 adds the received symbol r and the reference symbol -S _ij2 to obtain rS _ij2 , and the first square part 12 squares the output of the adder 11 to _obtain a distance between r and S _ij2 . Obtain Here, the reference symbol is a negative value of S _ij2 , and the Euclidean distance function (d (a, b) = (ab) ² ) is used as the distance function.

The adder / subtracter 12 adds 8 to the output of the adder 11 when the sign bit is 1, and subtracts 8 from the output of the adder 11 when the sign bit is 0. That is, if rS _ij2 is negative, the output of the adder / subtracter 12 is rS _ij1 , and if rS _ij2 is positive, the output of the adder / subtractor 12 is _rSij3 .

Here, the sign bit has a value of 1 when the sum of the received symbol and the reference symbol is negative, has a value of 0 when 0 or a positive number, and the subtraction / adding unit 12 has a sign of 1 If the sign bit is 0, subtraction is performed. And if the system uses a two's complement to represent negative numbers, the sign bit is equal to the MSB of the output of the adder 11.

On the other hand, the second square section 14 squares the output of the addition / subtraction portion 12 calculates a distance between r and the distance between _ij1 S, or r and S _ij3.

In addition, the comparison unit 15 compares the distances calculated by the first and second square units 13 and 14, selects a small value, and outputs a selection signal to the multiplexer MUXO. The flexor MUXO selects and outputs a smaller value among the outputs of the first or second square units 13 and 14 according to the selection signal from the comparator 15, and outputs the multiplexer. ) Is the branch metric to get.

5 is a block diagram illustrating a configuration of an 8-state lattice encoder in which the 4-state is extended to 8 states so as not to affect decoding, except that there is one extra memory S2. Is the same as

Therefore, the encoder of FIG. 1 and the encoder of FIG. 5 output the same value for the same input when the initial states of the memories of the encoder are the same. That is, the signal encoded by the lattice coder of FIG. 1 can be decoded using a Viterbi decoder for the lattice coder of FIG.

The relationship between the state transition and the input and channel symbols for the eight-state grid encoder may be represented by a state transition table as shown in FIG. 6, and the names of the states of the state transition table may include memory S0, S1, S1, The state of (S2) is shown in decimal. The input is a decimal representation of the inputs a1 and a2 of the grid encoder.

Here, in FIG. 6, the state transition table for the 8 state grid encoder or the 8 state grid encoder of FIG. 5 is extended to 8 states so as not to affect decoding. Therefore, the NTSC interference cancellation filter is not used in comparison with FIG. If not.

Comparing the state transition table of FIG. 3 and FIG. 6, it can be seen that FIG. 3 and FIG. 6 are identical except for the channel symbol. This means that the state transition of FIG. 3 and the state transition of FIG. 6 are the same.

That is, the structure of the Viterbi decoder for FIG. 3 and the Viterbi decoder for FIG. 6 are identical. The Viterbi decoder for FIG. 3 and the Viterbi decoder for FIG. 6 differ only in the channel symbols that are compared when computing the branch metric.

Therefore, the present invention can use a Viterbi decoder as a Viterbi decoder for FIG. 3 by changing the channel symbols to be compared when calculating the branch metric using the switching means, and as a Viterbi decoder for FIG. It would also be available. That is, it can be used when the NTSC interference cancellation filter is used as one Viterbi decoder and when the NTSC interference cancellation filter is not used.

FIG. 7 is a block diagram illustrating a branch metric computing device for a Viterbi decoder in which a four-state Viterbi decoder and an eight-state Viterbi decoder are combined according to the present invention. 21), an adder / subtracter 22 that adds 8 or subtracts 8 to the output of the adder 21 according to whether a sign bit and an NTSC interference cancellation filter are used, and the adder First and second square parts 23 and 24 that square the output of 21 and the output of the add / subtract part 22, respectively, and the first and second square parts 23 and 24, respectively. A comparator 25 for outputting a first selection signal sel1 to compare the magnitude of the output of the output signal and selecting the smaller value, and the first or the second signal according to the first selection signal sel of the comparator 25. The multiplexer (MUX1) for selecting and outputting the outputs of the squares (23) and (24), and the adder (21) provides a reference penalty depending on whether the NTSC interference cancellation filter is used or not. The switching unit 26 controls the addition or subtraction of the addition / subtraction unit 22 according to the use of the NTSC interference cancellation filter and the sign bit.

The switching unit 26 provides a reference symbol value input to the adder 21 as 1 when the NTSC interference cancellation filter is used according to the second selection signal sel2, and 0 when the NTSC interference cancellation filter is not used. When the second select signal sel2 is 0 and the second select signal sel2 is 0, the adder / subtractor 22 performs subtraction only. When the second select signal sel2 is 1, the signed bit ( In accordance with Sign-Bit, the addition / subtraction section 22 is constituted by an AND gate AND1 for adding or subtracting.

In the present invention configured as described above, the adder 21 adds the received symbol and the reference symbol.

At this time, the second multiplexer (MUX2) is 0 when the NTSC interference cancellation filter is not used so that the reference symbol input to the adder 21 depends on whether the NTSC interference cancellation filter is used. In use, a corresponding reference symbol is input to the adder 21 according to the value of the second selection signal sel2 having a value of 1.

Accordingly, the adder 21 adds and outputs the received reference symbol and the received reference symbol according to whether the NTSC interference cancellation filter is used.

The adder / subtracter 22 adds or subtracts from the constant 8 input according to the second selection signal sel2 and the sign bit (Sign-Bit).

That is, when the NTSC interference cancellation filter is not used, the second selection signal sel2 is 0, so the output of the AND gate AND1 is 0 regardless of the sign bit (Bit-Bit). (22) performs subtraction unconditionally.

When the NTSC interference cancellation filter is used, the second selection signal sel2 is 1, so the adder / subtracter 22 adds or subtracts according to the sign bit (Sign-Bit). That is, when the sign bit (Bit-Bit) input to the AND gate AND1 is 0, the output of the AND gate AND1 is 0, so the addition / subtraction unit 22 performs subtraction. When the sign bit is 1, the AND gate ( Since the output of AND1) is 1, the addition / subtraction section 22 adds.

Meanwhile, the output of the adder 21 and the output of the adder / subtracter 22 are squared by the squares 23 and 24, respectively, and then input to the comparator 25 to compare the magnitudes thereof. The comparator 25 outputs a first selection signal sel1 to select a small value according to the comparison result.

Accordingly, the multiplexer MUX1 selects and outputs a smaller value among the outputs of the first or second square units 23 and 24 according to the first selection signal sel1 from the comparator 25. , The output of the multiplexer MUX1 becomes the branch metric obtained.

8 shows the reference symbols used in the Viterbi decoder according to the present invention for each state transition. Here, weak NTSC interference is a reference symbol corresponding to the case where the NTSC interference cancellation filter is not used. Strong NTSC interference is a reference symbol corresponding to the case of using an NTSC interference cancellation filter.

As described above, the present invention can be designed and manufactured easily by using a general Viterbi decoder design method, and the hardware is simplified and the cost can be reduced by reducing the number of blocks required to calculate branch metrics. Will be.

Claims (7)

An adder 21 that adds a received symbol and a reference symbol, and an adder / subtracter 22 that adds 8 to or subtracts 8 from the output of the adder 21 according to whether the NTSC interference cancellation filter is used or signed bits. ), First and second square parts 23 and 24 that square the output of the adder 21 and the output of the adder / subtracter 22, respectively, and the first and second square parts ( 23) compares the magnitudes of the outputs of (24) and selects a smaller value, and the first or second squares (23), (24) in accordance with the output of the comparator (25). And a switching unit 26 for controlling the adder 21 and the adder / subtracter 22 according to whether or not the multiplexer MUX1 and NTSC interference canceling filter are selected and outputted. Viterbi decoder of high-definition television, characterized by having a branch metric computing device configured. The apparatus of claim 1, wherein the switching unit (26) includes a multiplexer (MUX2) for allowing a reference symbol to be input to the adder (21) according to whether the NTSC interference cancellation filter is used, and whether or not to use the NTSC interference cancellation filter. Viterbi decoder of high-definition television, characterized in that it comprises an AND gate (AND1) which causes the addition / subtraction section (22) to add or subtract according to bits. The Viterbi decoder of claim 1 or 2, wherein the addition / subtraction section (22) performs only subtraction regardless of the sign bit when the NTSC interference cancellation filter is not used. The Viterbi decoder of claim 1 or 2, wherein the addition / subtraction section (22) adds or subtracts according to the sign bit when the NTSC interference cancellation filter is used. An adder 21 that adds a received symbol and a reference symbol, and an adder / subtracter 22 that adds 8 to or subtracts 8 from the output of the adder 21 according to whether the NTSC interference cancellation filter is used or signed bits. ), First and second square parts 23 and 24 that square the output of the adder 21 and the output of the adder / subtracter 22, respectively, and the first and second square parts ( 23) compares the magnitudes of the outputs of the outputs 24 and selects a smaller value, and the first or second squares 23, 24 according to the output of the comparison unit 25; Multiplexer (MUX1) for selecting and outputting the output of the multiplier (MUX1), multiplexer (MUX2) for inputting the reference symbol according to whether the NTSC interference cancellation filter is used or not, and use of the NTSC interference cancellation filter, and High-definition teller characterized in that it comprises an AND gate (AND1) for the addition / subtraction unit 22 to add or subtract according to the sign bit The Viterbi decoder of vision. 6. The Viterbi decoder of claim 5, wherein the addition / subtraction section (22) performs only subtraction regardless of the sign bit when the NTSC interference cancellation filter is not used. 6. The Viterbi decoder of claim 5, wherein the addition / subtraction section (22) adds or subtracts according to a sign bit when the NTSC interference cancellation filter is used.

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