KR100345450B1 - Apparatus and method for encoding and decoding of intra block prediction - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to an intra block prediction encoding and decoding apparatus and a method thereof.

2. Technical problem to be solved by the invention

The present invention inserts data of block (0) of MB (even number, n) into block position (3) when the address map of macro blocks is an even line slice, and MB when an odd line slice is inserted. It is configured to store the data of block (3) of (odd, n) in block (0) and the data of blocks (4) and (5) to block (6) and (7) It is an object of the present invention to provide an intra block prediction encoding and decoding apparatus and method for improving the processing speed according to encoding and decoding.

3. Summary of Solution to Invention

An apparatus for predictive encoding and decoding of an intra block, comprising: quantization means for quantizing a speech signal; Inverse quantization means for inverse quantization of a speech signal; External control signal means for providing a control signal for encoding and decoding; Macroblock packet detection means for calculating a packet area according to the position value of the X-axis of the macroblock inputted from the external control signal means and detecting packet information in a converted state compared with the packet area of the currently input macroblock; Prediction memory address generation means for generating an address of a macro block to be referred to by the packet information detected from said macroblock packet detection means; A prediction memory section for storing the inverse quantized DC / AC component to be referred to according to the address generated by the prediction memory address generating means and selecting already stored reference values; And obtaining and encoding a difference component between the quantization output information transmitted from the quantizer and the reference value stored in the prediction memory unit, and obtaining a composite of the inverse scanned information transmitted from the inverse scan processing unit and the reference value stored in the prediction memory unit. Predictive encoding / decoding means for decoding and transmitting to the quantizer.

4. Important uses of the invention

The present invention is used for image compression technology.

Description

Apparatus and method for encoding and decoding of intra block prediction

The present invention relates to an intra block prediction encoding and decoding apparatus and a method thereof, and more particularly, to a memory map for performing a reference in a single block form with a macroblock packet detector to adaptively encode both a DC component and an AC component. The present invention relates to an intra block prediction encoding and decoding apparatus for intra block encoding through a structure, and a method thereof.

In general, MPEG-2 differentially encodes only the DC component of the intra block, whereas MPEG-4, which is intended for low bit rate transmission, improves the intra block encoding efficiency by adaptively encoding both the DC component and the AC component. The main applications of the MPEG-4 are for real-time communication such as video telephony utilizing low bit rate and error tolerance, mobile communication multimedia devices such as mobile phones, and internet broadcasting.

Intra-block prediction encoding and decoding and processes used in the conventional MPEG-4 are mainly performed in software, which will be described in detail with reference to FIGS. 1 and 2.

1 is a configuration diagram of an embodiment for processing a conventional encoding and decoding by software.

As shown in FIG. 1, the encoding and decoding apparatus for processing in software includes a system processor 100, an internal data memory 110, a prediction encoder / decoder unit 120, a quantizer 150, and an inverse quantizer ( 130, a scan processor 140, and a reverse scan processor 150.

The system processor 100 controls encoding and decoding with reference to an inverse quantized macro block stored in the internal data memory 110. The quantizer 130 quantizes the input image information and provides the quantized information to the prediction encoder / decoder 120. The prediction encoder / decoder 120 encodes the received quantization information and encodes the same through the scan processor 140. The inverse scan processor 150 provides inversely scanned image information to the predictive encoder / decoder 120.

The predictive encoder / decoder 120 decodes the inversely scanned image information with reference to a macroblock stored in the internal data memory 110 and provides the decoded image information to the inverse quantizer 160.

Here, the DC / AC component, which is a reference value to be used for prediction, stores the inverse quantized macro block in the internal data memory 110 as it is. At this time, the block to be referred to requires at least one slice since the left, upper, and upper blocks are needed. Or you need to store and process data for two slices.

Hereinafter, an operation according to prediction and reconstruction will be described by configuring an address map of a macroblock to be referred to by referring to the 48 × 64 pixel image illustrated in FIG. 2.

FIG. 2 is a diagram illustrating the structure of an address for each block location to be stored in the internal data memory illustrated in FIG. 1.

As shown in FIG. 2, a basic macro block (hereinafter referred to as "MB") of an image and a block position in a macroblock unit are shown, and the macro block includes MB (0,0) and MB (0). , 1), MB (0,2), MB (1,0), MB (1,1), MB (1,2), MB (2,0), MB (2,1), MB (2, 2), MB (3,0), MB (3,1) and MB (3,2), where one line is MB (0,0), MB (0,1) and MB (0). , 2). And a collection of macro blocks in a line is a slice. In addition, the one macro block, for example, the MB (0,0) is 6 blocks (0), (1), (2), (3), (4) and (5) It consists of

Here, to perform prediction encoding and decoding on block (0) corresponding to MB (1,1), block (1) of MB (1,0), which is a left reference value, and MB (0), which is a reference value on the upper left side. Block (3) of, 0) and block (2) of MB (0,1), which are upper reference values, are required. However, if only data corresponding to one slice is stored, information on block (3) of the macro block (1, 0) is already stored and cannot be referred to at the upper left side, and U, corresponding to the color component, In order to store the information of blocks (4) and (5), which are blocks of V, extra memory is required, and thus, a memory address map cannot be efficiently constructed.

For example, if the image to be processed is CIF format (353 × 288), the number of macroblocks corresponding to one line is 22, so the prediction of the currently inputted macroblock without storing at least 23 macroblocks and There was a problem that the memory can not be efficiently configured in the end because it is difficult to restore.

Accordingly, the present invention has been proposed to solve the above-mentioned problems. When the address map of the macroblocks is an even line slice, the data of the block (0) of MB (even number, n) is (3). In the case of inserting the block No., and in the case of the slice of the odd line, the data of the block (3) of MB (odd, n) is stored in the block (0), and the data of the blocks of (4) and (5) The purpose of the present invention is to provide an intra block prediction encoding and decoding apparatus and method for storing the blocks at (6) and (7) to improve the processing speed according to encoding and decoding.

1 is a configuration diagram of an encoding and decoding apparatus implemented in conventional software.

FIG. 2 is a structural diagram of an address map for each block position to be stored in the internal data memory shown in FIG. 1; FIG.

3 is a diagram illustrating an embodiment of an intra block prediction encoding and decoding apparatus according to the present invention;

4 is a detailed block diagram of an embodiment of a macroblock packet detector shown in FIG. 3;

FIG. 5 is a structural diagram of an address map for each block position to be stored in a prediction memory unit according to the present invention; FIG.

FIG. 6 is a detailed block diagram of an embodiment of the predictive encoder / decoder shown in FIG. 3; FIG.

According to an aspect of the present invention, there is provided an apparatus for predictive encoding and decoding of an intra block, the apparatus comprising: quantization means for quantizing a speech signal; Inverse quantization means for inverse quantization of a speech signal; External control signal means for providing a control signal for encoding and decoding; Macroblock packet detection means for calculating a packet area according to the position value of the X-axis of the macroblock inputted from the external control signal means and detecting packet information in a converted state compared with the packet area of the currently input macroblock; Prediction memory address generating means for generating an address of a macro block to be referred to by the packet information detected from said macroblock packet detecting means; A prediction memory section for storing the inverse quantized DC / AC component to be referred to according to the address generated by the prediction memory address generating means and selecting already stored reference values; And obtaining and encoding a difference component between the quantization output information transmitted from the quantizer and the reference value stored in the prediction memory unit, and obtaining a composite of the inverse scanned information transmitted from the inverse scan processing unit and the reference value stored in the prediction memory unit. And predictive encoding / decoding means for decoding and transmitting the quantizer.

Meanwhile, the present invention is a method for predictive encoding and decoding of an intra block applied to an intra block predictive encoding and decoding apparatus, wherein the packet region is calculated according to a position value of an input macro block, A first step of detecting packet information in a converted state in comparison with the packet area; A second step of generating an address of a macro block to be referred to by the detected packet information; A third step of storing an inverse quantized DC / AC component as a reference value and selecting already stored reference values according to the generated address; And a fourth step of obtaining and encoding a difference component between the quantized output information and the reference value stored in the third step, and obtaining and decoding a composite of the inversely scanned information and the reference value stored in the third step. It features.

The objects, features and advantages described above will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating an embodiment of an intra block prediction encoder and a decoder according to the present invention.

As shown in FIG. 1, the configuration includes an external control signal unit 310, a macroblock packet detector 320, a prediction memory address generator 340, a prediction memory unit 350, and a prediction encoder / decoder unit 360. ), A quantizer 370, a scan processor 380, an inverse scan processor 390, and an inverse quantizer 400.

The external control signal unit 310 provides a read / write enable signal (read / write enable) to the prediction memory unit 350, and provides the macroblock packet detector 320 with the position values of the X and Y axes of the macroblock. It provides a quantization coefficient to the prediction encoder / decoder unit 360. Here, the quantization coefficients are different from each other in the encoding operation and the decoder operation.

The macroblock packet detection unit 320 calculates the number of packets according to the position values of the X and Y axes of the macroblock from the external control signal unit 310 to refer to the packet area of the currently input macroblock for prediction and restoration. It detects whether it is equal to the packet area of the macroblocks and provides the same to the prediction memory address generator 340.

The prediction memory address generator 340 generates an address of a block to be referred to by the packet information provided from the macroblock packet detector 320 and provides the address to the prediction memory unit 350. The prediction memory unit 350 stores the inverse quantized DC / AC component to be referred to according to the address generated by the prediction memory address generation unit 340, calculates already stored reference values, and predicts the selected left or upper value. The encoder / decoder unit 360 is provided.

Here, the prediction memory unit 350 stores the DC / AC component to be referred to in the macro block corresponding to one slice, the write address to store the data of the block to be referred to, and the prediction encoder / decoder 360 to refer to. A read address for reading data and a block to be referred to on the left or upper side are selected. The address format of the prediction memory unit 350 includes a macroblock number, a block number, and a DC / AC component of one slice as shown in Table 1.

MSB LSB

Number of macroblocks in one slice (5 bits) Number of blocks (3 bits) DC / AC component (4bit)

Here, since the number of one slice macroblock varies depending on the image size, the number of bits is variable.

The prediction encoder / decoder 360 receives the reference value IQEDOUT selected from the prediction memory unit 350 and divides the DC quantization value (DC_SCALER value) when the quantization value is DC. A prediction encoding operation is performed to obtain a difference component from an output QFIN of the quantizer 370 currently input.

The predictive encoder / decoder 360 receives a reference value IQEDOUT selected by the predictive memory 350 and divides the value by the value of the inverse quantizer 400, and then inputs the current scan of the inverse scan processor 390. A predictive decoding operation of obtaining a sum component with an output IZZ_OUT and outputting the sum component to the inverse quantizer 400 is performed.

4 is a detailed block diagram of an embodiment of the macroblock packet detector shown in FIG. 3.

As shown in FIG. 4, the macroblock packet detector 320 compares a packet input unit 321, a macroblock delay unit 322, a packet value storage unit 323, a reference value storage unit 325, and a packet conversion comparison. An output unit 327 is included.

The packet input unit 321 includes an adder, a cumulative register (RO), a storage register (R1), and a delay register (R2). The packet input unit 321 accumulates the packet signal by the adder and the accumulator register R0, and the accumulated signal. Is stored by the storage register R1, and the stored signal is delayed by the delay register R0.

The packet signal delayed by the delay register R2 of the packet input unit 321 is provided to the packet value storage unit 323, and the packet signal stored by the storage register R1 is stored in the reference value storage unit 325 and the packet. Respectively provided to the conversion comparison output section 327. The packet value storage unit 323 includes a macroblock position mux and a plurality of registers (REG0, REG1, .... REGn, where n is the number of macroblocks in one slice), and the packet input unit 321 The packet conversion value supplied from the data stored in each register (REG0, REG1, .... REGn) according to the X-axis position value provided from the macroblock delay unit 322, and the stored value is stored in the reference value storage unit 325. To provide.

The reference value storage unit 325 includes a packet connection block, a left reference register (PN_L), an upper left reference register (PN_LT), and an upper reference register (PN_T), which are currently input to the packet value storage unit 323. The converted value of the packet value is divided into the left, upper left and upper sides, respectively, and stored, and provided to the packet conversion comparison output unit 327.

The packet conversion comparison output unit 327 compares the packet conversion values input from the reference value storage unit 325 with the packet values from the packet input unit 321 currently input, and outputs the conversion status.

That is, the packet conversion comparison output unit 327 compares the left packet value stored in the left reference register PN_L with the current left packet value provided from the packet input unit 321, and outputs the difference value. The upper left packet value stored in the upper reference register PN_LT is compared with the current upper left packet value provided from the packet input unit 321, and the difference value is output, and the upper side stored in the upper reference register PN_T. And compares the packet value with the current upper packet value provided from the packet input unit 321 and outputs the difference value.

Here, the detection information of the packet region according to the difference value output by the above process is used to generate an address that stores the block of the currently input macroblock and the value of the block to be referred to, wherein the generated address is predicted. The address of the DC / AC component stored in the memory 350 is shown.

5 is a structural diagram of an address map for each block position to be stored in the prediction memory unit according to the present invention.

As illustrated in FIG. 5, when the slices are even and odd in the address for each block position to be stored in the prediction memory unit, the map is configured by changing and storing the positions of the macro blocks. That is, in case of an even line slice, block (0) of MB (even number n) is stored at block (3), and in case of odd line slice, block (3) of MB (odd number n) DC / AC components are stored in blocks (0), and blocks (4) and (5), which are color information, are stored in blocks (6) and (7).

6 is a diagram illustrating an embodiment of a prediction encoder / decoder unit according to the present invention.

As shown in FIG. 6, the configuration includes a distribution unit 362, a first code and decoder 366, and a second code and decoder 368.

The distribution unit 362 includes a rounding circuit, a divider, a DC scaler, a multiplexer, and a quantization LUT, and rounds a reference value IQEDOUT provided from the prediction memory unit 350 and the external control signal unit 310. Divide operation is performed by receiving the quantization coefficient provided by. Here, in the case of the prediction code and the decoding of the DC component, the division operation is performed through the DC scaler, and in the case of the AC component, the division operation is divided by the quantization coefficient value. The first code and decoder 366 includes a register and a multiplexer, and performs a subtraction operation by the adder and subtractor 364 on the quantization output QFIN provided from the quantizer 370 during an encoding operation. The inverse scan signal IZZ_OUT provided by the inverse scan processing unit 390 is added to the inverse quantizer 400 by the adder / subtractor 364 during the decoding operation.

The second code and decoder 368 includes a register, a multiplexer, and a clipping unit. The second code and decoder 368 is provided to the scan processor 380 encoded by the subtraction operation during the encoding operation. The inverse scan signal IZZ_OUT provided at 390 is added by the adder-subtracter 364 to the inverse quantizer 400.

The present invention described above is not limited to the stated embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the present invention has an effect of reducing the storage space of a memory for predicting a macroblock by efficiently constructing an address map through an adaptive intra prediction encoding and a decoder.

Claims (6)

An apparatus for predictive encoding and decoding of an intra block, Quantization means for quantizing a speech signal; Inverse quantization means for inverse quantization of a speech signal; External control signal means for providing a control signal for encoding and decoding; Macroblock packet detection means for calculating a packet area according to the position value of the X-axis of the macroblock inputted from the external control signal means and detecting packet information in a converted state compared with the packet area of the currently input macroblock; Prediction memory address generating means for generating an address of a macro block to be referred to by the packet information detected from said macroblock packet detecting means; A prediction memory section for storing the inverse quantized DC / AC component to be referred to according to the address generated by the prediction memory address generating means and selecting already stored reference values; And Obtains and encodes the difference between the quantization output information received from the quantizer and the reference value stored in the prediction memory unit, and obtains and decodes a composite of the inverse scanned information transmitted from the inverse scan processor and the reference value stored in the prediction memory unit. Predictive encoding / decoding means for transmission to the quantizer Intra block prediction encoding and decoding apparatus comprising a. The method of claim 1, wherein the macroblock packet detecting means comprises: A packet input unit for accumulating and storing the input packet value and delaying the stored packet value; A packet value storage unit for storing the packet value delayed from the packet input unit according to the position of the X-axis of the macro block; A reference value storage unit for storing a reference value of a packet value of a macroblock inputted from the packet value storage unit; And A packet conversion comparison output unit for comparing a reference value stored in the reference value storage unit with a packet value input from the packet input unit and outputting a conversion state thereof Intra block prediction encoding and decoding apparatus comprising a. The method of claim 1, wherein the prediction memory unit, And an address capable of storing and reading the data of the macro block to be referred to, the data to be referred to in a macro block corresponding to one slice, and including the address. The method of claim 3, wherein the address map of the macro blocks stored in the prediction memory unit, If the slice is an even line, the data of the block (0) of MB (even number or n) is inserted into the block position (3). If the slice is an odd line, the number (3) of MB (odd, n) is inserted. Intra block prediction encoding and storing data of a block in block (0), and data of blocks (4) and (5) are stored in blocks (6) and (7). Decryption device. A method for predictive encoding and decoding of an intra block applied to an intra block predictive encoding and decoding apparatus, A first step of calculating a packet area according to a position value of an input macro block, and detecting packet information in a converted state by comparison with the packet area of a currently input macro block; A second step of generating an address of a macro block to be referred to by the detected packet information; A third step of storing an inverse quantized DC / AC component as a reference value and selecting already stored reference values according to the generated address; And A fourth step of obtaining and decoding a difference component between the quantized output information and the reference value stored in the third step, and obtaining and decoding a composite of the inversely scanned information and the reference value stored in the third step Intra block prediction encoding and decoding method comprising a. The method of claim 5, wherein the first step, A fifth step of accumulating and storing the input packet value and delaying the stored packet value; A sixth step of storing the delayed packet value according to the position of the X axis of the macro block; A seventh step of storing a reference value of the packet value of the macro block; And An eighth step of comparing the stored reference value with the currently input packet value and outputting the conversion state; Intra block prediction encoding and decoding method comprising a.