KR100230350B1 - A semiconductor device and the manufacturing method - Google Patents

Abstract

The semiconductor device of the present invention is to insulate an impurity doped region formed in a surface region of a semiconductor substrate, a field insulating film defining at least one active region on the semiconductor substrate, a bit line formed over the field insulating film, and the bit line. A cell array region including a bit line insulating layer and a capacitor, a storage electrode formed on the bit line insulating layer and electrically connected to the impurity doped region, a dielectric layer formed on the storage electrode and a plate electrode formed on the dielectric layer The capacitor and the bit line insulating layer are formed to extend adjacent to the cell array region, and are formed to cover the periphery of the peripheral circuit region and the entire periphery of the peripheral circuit region compared to the surface of the cell array region to compensate for the step. Play adjacent to the peripheral circuit area A first insulating film covering the pattern portion of the electrode and the agent, over the first insulating film pattern and a planarized second insulating film formed above the cell array region. According to the present invention, the first insulating film pattern having a thickness sufficient to compensate for the step difference may be formed in the global step area to improve flatness.

Description

Semiconductor device and manufacturing method thereof

1 (a) and 1 (b) are process sequence cross-sectional views showing an example of the planarization process of the prior art,

2 shows one end face shape as another example of the prior art planarization process,

3 (a) to 3 (c) is a first embodiment of the planarization process according to the present invention,

4 (a) to 4 (c) is a second embodiment according to the present invention,

5 (a) to 5 (c) are Example 3 of the planarization process of this invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a flattened global step and a method of manufacturing the same when a distance between patterns having a large step is far apart.

Semiconductor devices, in particular dynamic random access memory (DRAM) devices, are arranged in a matrix form of cells composed of one transistor and one capacitor. and a cell array area for storing data, and a peripheral circuit area for storing or transmitting information in each cell driving the cell array.

Recently, the vertical integration between the cell array region and the peripheral circuit region is increasing due to the ultra-high integration of semiconductor devices. As a result, the cell capacitors are stacked in order to increase the cell capacitance capacity that can be accumulated as the cell area is reduced. A technique for forming or increasing a storage node of a cell capacitor has been developed and used. As the degree of integration of the semiconductor device increases, the step of the patterns formed in the cell array region is continuously increased. In addition, an efficient planarization method of the global step, in which the distance between the patterns having the large step distance is far apart, is a subsequent metal. It is important to prevent bad modes of the wiring process.

According to the monthly semiconductor world November 11, 1989, page 11, a planarization method using a process technology for reflowing BPSG (Borophospho Silicate Glass) film is introduced. It is shown.

First, referring to FIG. 1 (a), after the pattern structure 1 is formed on the underlying layer 100, the BPSG film 2 is deposited on the top, and then, in FIG. As shown in FIG. 1, the film is reflowed by heat treatment at a high temperature of 900 ° C. for 30 to 50 minutes to form a flat film surface having almost no step. In other words, the prior art shows that the flatness can be well maintained by the reflow technique of the BPSG film when the distance between the pattern structures is not far apart.

In addition, Korean Patent Publication No. 776 (Publication No. 91-15046) introduces a method of flattening a pattern step by performing the same technique as that of the conventional process described above, that is, performing a process of forming and reflowing a BPSG film twice. The cross-sectional shape by this method is shown in FIG.

However, as shown in FIG. 2, in the case where the gap between the pattern structures 21 with steps on the base layer 200 is a global step that is far apart, only the reflow technique of the BPSG film 22 is repeated. Not only does not improve step coverage, but also has a disadvantage in that it is difficult to obtain excellent flatness. Therefore, according to the related art, in the subsequent metal wiring forming process, a notching phenomenon or a disconnection phenomenon occurs in the metal wiring formed over the stepped portion, and thus the process yield and the electrical characteristics of the semiconductor device. Deteriorates.

Accordingly, an object of the present invention is to solve the above-described problems and to provide a semiconductor device having excellent flatness between global steps.

In addition, another object of the present invention is to provide a manufacturing method suitable for manufacturing the semiconductor device.

In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor substrate, an impurity doped region formed in a surface region of the semiconductor substrate, a field insulating film defining at least one active region on the semiconductor substrate, and the field insulating film. A cell array region including a bit line formed thereon, a bit line insulating layer and a capacitor for insulating the bit line, a storage electrode formed on the bit line insulating layer and electrically connected to the impurity doped region, and on the storage electrode The capacitor comprising a formed dielectric film and a plate electrode formed on the dielectric film, a peripheral circuit region adjacent to the cell array region and formed with an extended bit line insulating layer, and having a step difference compared to a surface of the cell array region, and the peripheral circuit region. The stage is formed while covering And a first insulating layer pattern covering a portion of the plate electrode adjacent to the peripheral circuit region and a second insulating layer formed on the first insulating layer pattern and on the cell array region and planarized.

The cell array region may be formed in a recess region of the semiconductor substrate.

In order to achieve the above object, the present invention provides an impurity doped region formed on a surface portion of a semiconductor substrate, a field insulating film defining an active region formed on the semiconductor substrate, a bit line formed over the field insulating film, and the bit. A bit line insulating film for insulating a line, a storage electrode, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, the capacitor being electrically connected to the impurity doped region and formed on the bit line insulating film. A method of manufacturing a semiconductor device comprising a cell array region and a peripheral circuit region formed at a periphery of the cell array region and formed with the bit line insulating film extending, wherein the peripheral circuit region is formed on the bit line insulating film of the peripheral circuit region. While covering most of Forming a first insulating layer pattern covering a portion of the plate electrode extending to the peripheral circuit region, forming a second insulating layer on the first insulating pattern and the plate electrode, and forming the second insulating layer Heat treating and reflowing to planarize the surface of the second insulating film.

The cell array region may be formed in a recess region of the semiconductor substrate.

According to the present invention, prior to the planarization process, an insulating film pattern having a thickness sufficient to compensate for the step difference is formed in the global step area, thereby eliminating the global step, thereby providing step coverage and flatness, which is a problem of the conventional planarization technology due to the global step. Can solve the problem.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

3 is a cross-sectional view of a process sequence of Embodiment 1 of the present invention. Referring to FIG. 3 (a) first of FIG. 3, a semiconductor substrate or a substrate having an n or p-type impurity doped region is provided. An electrode composed of a combination of an insulating film and a conductive layer spaced apart at an interval of x ₁ or x ₂ on a base layer 300 including a layer or an n- or p-type impurity doped region and an isolation layer In the case of a word line, a bit line, or a memory device, pattern structures 31, such as memory cells, are formed on the upper surface of the pattern structure 31 and the base layer 300. The first insulating film 32 is deposited.

In this case, the first insulating layer 32 may be formed of an insulating layer constituting the electrode pattern structure 31 and an insulating material having a large etching selectivity. For example, a BPSG layer, which is an insulating layer into which impurities are introduced, may be used. In this step, when the BPSG film is used, a high temperature reflow process may be added. Next, a photoresist is applied on the first insulating layer 32, and then x ₂ which is at least three times greater than the final BPSG film thickness t ₁ of the upper end of the pattern structure shown in FIG. 3 (c). The photoresist is patterned to form an appropriate photoresist pattern 33. At this time, the edge gap between the pattern structure 31 and the photoresist pattern 33 is appropriately varied according to the shape and size of the pattern structure 31 and the thickness of the final BPSG film 24 so that the photoresist pattern 33 Is formed. The base layer 300 may also be composed of a single layer or a combination layer such as the word line or the bit line, and may be coated with an insulating film.

Subsequently, referring to FIG. 3B, when the first insulating layer 32 is anisotropically or isotropically etched using the photoresist pattern 33, the first insulating layer pattern 32 compensates the pattern difference in the global step area. ') Is formed. Subsequently, a second insulating layer 34 is deposited on the upper surface of the pattern structure 31, the base layer 300, and the first insulating layer pattern 32 ′. At this time, the second insulating layer 34 is made of a material that can be reflowed at a high temperature. For example, the BPSG film is a typical case.

Next, referring to FIG. 3 (c), the upper front layer after the reblowing process of the second insulating film 34 at a high temperature of about 800 ° C. to 900 ° C. shows that desired good flatness is obtained. have.

Example 2

As the integration of DRAM devices increases, the reduction of the occupied area of each memory cell is required, and a stacked capacitor forming technology is used to secure a relative storage capacity of a cell capacitor. The present embodiment is performed as shown in FIG. 4, which is a cross-sectional view of a process sequence for flattening the stepped pattern structure of the DRAM device.

First, referring to FIG. 4A, a field insulating film 41 defining an active region is formed on a semiconductor substrate 400, and impurity doped regions 42 and 43 are formed in a surface region of the semiconductor substrate 400. For example, an impurity doped region of n or p type is formed. A bit line 44 is formed on the field insulating layer 41, and the bit line is insulated by the bit line insulating layer 61. In particular, as the density increases, the storage node 45 is increased in order to increase the cell capacitance value, so that the bit line 44 has a structure that comes under the storage node 45 so that the pattern structure increases as the density increases. It can be seen that the step becomes larger. In this figure, the capacitor dielectric layer 46 and the plate electrode 47 become an essential component of the stacked capacitor and have the same shape as in the figure.

Referring to FIG. 4 (b), the thickness of the first insulating film 48 at the top of the pattern structure can compensate to some extent the global step (t _{4 in} FIG. 4 (a)) (t ₄ ± (0 to 5000 kPa). It is deposited as)). At this time, if necessary, the first insulating film 48 may be reflowed by a heat treatment process. Then, a photoresist film is coated on the first insulating layer 48 to form a photoresist pattern 49 by photolithography to cover the peripheral portion B other than the cell array portion A. FIG. In this case, the photoresist pattern 49 may cover the cell array peripheral portion B over one end of the play electrode 47 of the cell capacitor extending to the peripheral portion B of the cell array. In this case, a first insulating film pattern (48 'in FIG. 4C) to be formed later is formed to overlap with a portion of the plate electrode 47.

Next, referring to FIG. 4C, the first insulating layer 48 is etched using the photoresist pattern 49 as an etching mask to overlap a portion of the plate electrode 47. After the insulating film pattern 48 'is formed, the second insulating film 40 is deposited to a thickness of about 3,000 kPa to 5000 kPa on the entire upper surface of the structure, and then subjected to a high temperature heat treatment reflow process to obtain good flatness as shown in the drawing. do.

Example 3

This embodiment relates to the DRAM device as in the second embodiment, but shows a planarization method of the DRAM device in which the cell array unit is recessed in order to further improve the flatness of the global step. The process sequence cross section is shown.

First, referring to FIG. 5A, a field insulating film 51 defining an active region is formed on a semiconductor substrate 500, and an impurity doped region 52 is formed in a surface region of the semiconductor substrate 400. For example, an n or p type impurity doped region is formed. A bit line 53 is formed on the field insulating layer 51, and the bit line 53 is insulated by the bit line insulating layer 63.

In particular, in the second embodiment, the semiconductor substrate 500 of the cell array unit a is recessed by a thickness of t ₃ , and then the bit line 53, the storage node 54, the dielectric film 55, and the plate node 56 are formed. The formed cell capacitors are sequentially formed to complete the cells.

Subsequently, as shown in FIG. 5 (b), the first insulating film 57 is deposited thinly by the recessed semiconductor substrate thickness t ₃ than the thickness of the insulating film 48 of Example 2 on the structure where the cell is completed. To form. If the recessed semiconductor substrate thickness t ₃ is greater than or equal to the thickness of the insulating film 48 of the second embodiment, deposition and patterning of the first insulating film 57 may be omitted. In this case, the first insulating layer 57 may be reflowed by high temperature heat treatment.

Next, a photosensitive film is coated on the first insulating layer 57 to form a photosensitive film pattern 58 by photolithography to cover the peripheral portion B other than the cell array portion A. FIG. In this case, the photoresist layer pattern 58 may cover the cell array peripheral portion B over one end of the plate electrode 56 of the cell capacitor extending to the peripheral portion B of the cell array. In this case, a first insulating film pattern (57 ′ in FIG. 5C) to be formed later is formed to overlap a portion of the plate electrode 56.

Next, referring to FIG. 5C, the first insulating layer 57 is etched using the photoresist pattern 58 as an etching mask to overlap a portion of the plate electrode 56. After the insulating film pattern 57 'is formed, the second insulating film 59 is deposited to a thickness of about 3,000 kPa to 5000 kPa on the entire upper surface of the structure, and then subjected to a high temperature heat treatment reflow process to obtain good flatness as shown in the drawing. You get In the drawings of the second and third embodiments, N ⁺ active region 52 becomes a source region of the transfer gate transistor.

Accordingly, the present invention solves the step coverage and the flatness, which is a conventional problem of the planarization technology due to the global step by forming an insulating film pattern having a thickness enough to compensate for the step in the global step area. Therefore, the process yield and the electrical characteristics of the semiconductor device can be greatly improved.

Claims (6)

An impurity doped region formed in a surface region of the semiconductor substrate; A field insulating film defining at least one active region on the semiconductor substrate; A cell array region including a bit line formed on the field insulating layer, a bit line insulating layer and a capacitor insulating the bit line; The capacitor including a storage electrode formed on the bit line insulating layer and electrically connected to the impurity doped region, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film; A peripheral circuit region adjacent to the cell array region and extending with a bit line insulating layer and having a step difference compared to a surface of the cell array region; A first insulating layer pattern formed covering the entire peripheral circuit area to compensate for the step and covering a portion of the plate electrode area adjacent to the peripheral circuit area; And a planarized second insulating layer formed on the first insulating layer pattern and on the cell array region at all times. The semiconductor device according to claim 1, wherein said cell array region is formed in a recess region of said semiconductor substrate. Semiconductor substrates; An impurity doped region formed in a surface region of the semiconductor substrate; A field insulating film defining at least one active region on the semiconductor substrate; A cell array region including a bit line formed over the field insulating layer, a bit line insulating layer for insulating the bit line, and a capacitor and formed in a recess region of the semiconductor substrate recessed relative to a peripheral circuit region; The capacitor including a storage electrode formed on the bit line insulating layer and electrically connected to the impurity doped region, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film; A peripheral circuit region adjacent to the cell array region and extending with a bit line insulating layer and having a step difference compared to a surface of the cell array region; A first insulating layer pattern formed to cover the part of the plate electrode region adjacent to the peripheral circuit region and formed to compensate for the step and cover the entire peripheral circuit region; And a planarized second insulating layer formed over the first insulating layer pattern and over the cell array region. An impurity doped region formed on a surface portion of the semiconductor substrate, a field insulating film defining an active region formed on the semiconductor substrate, a bit line formed over the field insulating film, a bit line insulating film for insulating the bit line, and a storage electrode And a cell array region including a dielectric layer formed on the storage electrode and a plate electrode formed on the dielectric layer, the cell array region including a capacitor electrically connected to the impurity doped region and formed on the bit line insulating layer, and a periphery of the cell array region. A method of manufacturing a semiconductor device, comprising: a peripheral circuit region formed on the semiconductor substrate, the peripheral circuit region formed by extending the bit line insulating film, wherein the peripheral circuit region is coated with most of the peripheral circuit region on the bit line insulating film of the peripheral circuit region. The plate extending into Forming a first insulating film pattern covering a portion of the electrode, forming a second insulating film on the first insulating film pattern and the plate electrode, and heat-reflowing the second insulating film to reflow the second insulating film. A manufacturing method of a semiconductor device comprising the step of flattening the surface. The method of manufacturing a semiconductor device according to claim 4, wherein said second insulating film is formed of a BPSG film. The method of claim 4, wherein the cell array region is formed in a recessed region of the semiconductor substrate.