KR100227833B1 - Wafer counter apparatus of ion implanter - Google Patents

Abstract

The present invention relates to a wafer counting device of an ion implantation facility in which the time of counting wafers in the ion implantation process is unified and improved to check the count abnormality.

The present invention relates to a wafer counting device of an ion implantation facility that controls operations of an ion implantation chamber and a load lock chamber in a process control unit, the method comprising: counting a cumulative amount of wafers in which processes installed in first and second end stations are performed; The count signals applied to the first and second counters are applied to the display unit provided in the operator panel for operating the process control unit to count the number of wafers at the same process point as the first and second counters, and the skip of the wafer is performed. It is configured to perform alarm operation when it occurs.

Therefore, according to the present invention, the management time of the wafer is unified, and the workability is improved, and the wafer skip is automatically sensed and the alarm operation is performed to maximize the control of the equipment and the process, thereby improving the yield.

Description

Wafer counting device of ion implantation equipment

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer counting apparatus of an ion implantation apparatus, and more particularly, to a wafer counting apparatus of an ion implantation apparatus which has been improved so that the time of counting a wafer in the ion implantation process can be checked and count abnormality can be checked.

As is well known, ion implantation refers to a technique for applying atomic ions into the target by applying energy that is large enough to penetrate the surface of the target, and implementing such a technique is an ion implantation facility.

In the semiconductor manufacturing process, the ion implantation apparatus can control the impurity concentration in the range of 10 ¹⁴ to 10 ¹⁸ atoms / cm 3, which is used because it has an advantage of easier concentration control than other impurity implantation techniques.

The ion implantation equipment described above may be divided into a vacuum device, an ion supply device, an ion extraction device, a scanning device, an accelerator device, and an ion implantation part, and each component should be supplied at various levels with a high voltage for the process. Ions are generated in the ion generating unit to which source gas is supplied using the supplied voltage, and extracted and accelerated ions are injected into the wafer.

In addition, the ion implantation equipment is usually composed of two end stations, and each end station is provided with a separate counter to display the cumulative number of wafers in which ion implantation is completed, and the operator operation unit load lock to perform a process. The number of picked up wafers in the chamber is configured to be displayed on the display unit.

Referring to FIG. 1, the process control unit 14 controlling the ion implantation chamber 10 and the load lock chamber 12 is buried in the counter 18 and the count 20 through the end station connection assembly 16. Of the wafer is configured to output a process signal according to the completion of ion implantation, and the operator operation unit 22 is configured to control the process control unit 14 for process control while the process control unit 14 is a load lock chamber. In step 12, when the wafer is picked up to perform the process, it is configured to apply the corresponding process signal to the display unit 24.

Here, each of the counters 18 and 20 shows the cumulative number of wafers in which ion implantation has been completed at the corresponding end station, and the display unit 24 of the operator operating unit 22 is the wafer peaked up in the load lock chamber 12. The quantity of the digital representation. Therefore, in the conventional wafer counting apparatus of the ion implantation facility, the check points of the quantities displayed on the counters 18 and 20 and the display unit 24 are different.

As described above, conventionally, since the number of wafers subjected to the ion implantation process is dually managed at different time points, inadequate operator judgment may be caused.

In the conventional ion implantation facility, when the number of wafers actually confirmed after the ion implantation of a predetermined number of wafers is completed and the number displayed on the counter are different from each other, whether ion implantation is completed for all wafers in which ion implantation was performed at the time. Had to be checked manually using measuring equipment. Therefore, time wasted accordingly, and work efficiency was also reduced.

In addition, although an alarm function for an error of various equipments generated during the process is provided to a conventional ion implantation equipment, an alarm function for skipping of a wafer or occurrence of a count abnormality is not provided. Therefore, an immediate process stop could not be performed, thus increasing the frequency of process anomalies.

In addition, various forms of unnecessary and inefficient work other than those described above are required, and there is a problem in that equipment is operated inefficiently.

SUMMARY OF THE INVENTION An object of the present invention is to provide a wafer counting device of an ion implantation apparatus for matching a wafer count time point and preventing an operator's judgment error and process abnormality related to the wafer count.

Another object of the present invention is to provide a wafer counting device of an ion implantation apparatus that can immediately check when a count error of a wafer occurs.

1 is a view showing a wafer counting device of a conventional ion implantation facility.

2 is a view showing an embodiment of a wafer counting device of an ion implantation apparatus according to the present invention.

3 is a detailed circuit diagram for driving the display unit of the embodiment according to the present invention.

※ Explanation of symbols for main parts of drawing

10: ion implantation chamber 12: road lock chamber

14, 26: process control unit 16, 28: end station connection assembly

18, 20: counter 22, 32: operator operation unit

24, 30: display unit 34, 36: up / down counter

38, 40: character generator 42, 44: 7-segment

46: quantity setting part 47: resistance pack

48 to 62, 78: NAND gate 64 to 76: OA gate

80: relay 82: buzzer

84: reset switch D1 to D5: diode

Q1 to Q3: transistors R1 to R5: resistors

In the wafer counting apparatus of the ion implantation apparatus according to the present invention for achieving the above object, ion implantation is performed on a wafer loaded in a carrier at the first and second end stations of the ion implantation chamber, and the wafer is loaded in a load lock chamber. In the wafer counting device of the ion implantation equipment for controlling the operation of the ion implantation chamber and the load lock chamber in the process control unit, counting the cumulative amount of wafers performed in the process installed in the first and second end station The count signal applied to the first and second counters is applied to the display unit provided in the operator panel for operating the process control unit, and is configured to count the quantity of wafers at the same process point as the first and second counters. .

The process point may be configured to be a time point at which ion implantation is completed for each wafer or a time point at which the wafer is picked up in the load lock chamber.

The count signal may be configured to be output through the first and second end station connection assemblies.

On the other hand, in the wafer counting apparatus of the ion implantation apparatus according to the present invention, the wafer loaded in the carrier of the load lock chamber is loaded into the ion implantation chamber and ion implanted, and the number of wafers is digitally displayed on the operator operation unit for managing the process. A wafer counting apparatus of an ion implantation apparatus comprising a display means, comprising: a quantity setting means in which a unit quantity of a wafer on which a process is performed is set, a quantity of wafers applied as a count signal from the display means and the quantity setting means Determination means for determining the normality and abnormality of the process with reference to the signal for the unit quantity and the alarm means for performing the alarm operation corresponding to the normality and abnormality with reference to the result determined by the determination means and the loading state of the carrier It is characterized by other features.

The quantity setting means may include a plurality of switching elements, and the switching signal of each switching element may be applied as the unit quantity signal as the determination signal.

And the discriminating means comprises: first logic combining means for NAND combining the number of wafers applied as a count signal by the display means and the signal for the unit quantity set by the quantity setting means, respectively, the first logic And a second logical combining means for OR-combining the NAND combined results in the combining means, and a third logical combining means for NAND combining the result of the second logical combining means and the loading state of the carrier. .

The alarm means may include switching means switched according to the output of the discriminating means, a relay switched in conjunction with the switching means, a normal alarm lamp connected to the first switching contact of the relay, and a second switching contact of the relay. It may be provided with an abnormal alarm that is connected.

The reset switch is further connected to the relay in parallel with the switching means, and a buzzer is further configured in parallel to the abnormal alarm.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

An embodiment according to the present invention is shown in FIG. 2, and in FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals and redundant descriptions of the components will be omitted.

The process control unit 26, which controls the ion implantation chamber 10 and the load lock chamber 12, receives the ionized wafer from the counters 18 and 20 and the display unit 30 through the end station connection assembly 28. When the injection is completed, it is configured to output a process signal corresponding thereto, and the operator operation unit 32 is configured to apply a process command to the process control unit 26 for process control. In addition, the display unit 30 installed in the operator operating unit 32 may be configured of a conventional seven-segment that is digital.

Therefore, the counters 18 and 20 and the display unit 30 receive the signal according to the received signal when the ion implantation of the buried wafer is completed, and performs the count operation and displays the quantity.

The embodiment according to the present invention has been described in that the process signal is applied to the counters 18 and 20 and the display unit 30 when the ion implantation is completed, so that the counting operation is performed. The process signal may be applied to the counters 18 and 20 and the display unit 30 when the wafer of the store is peaked up in the chamber 12 to perform a count operation.

Therefore, the number of wafers displayed in the ion implantation equipment is matched, and operator crosstalk can be prevented.

In addition, as shown in FIG. 2, a function of checking an error situation such as a wafer skip may be added to the display unit 30 installed in the operator manipulation unit 32 as shown in FIG. 3.

Referring to FIG. 3, the embodiment is configured such that a process signal applied from the process control unit 26 is applied to the photodiode D1 through an end station connection assembly 28, and a carrier signal is applied to the photodiode D2. It is. The process signal is a signal for completion of ion implantation to the buried wafer, and the carrier signal is a sensing signal applied to a low level when a carrier for loading a wafer is loaded and to a high level when no carrier is loaded.

The photodiode D1 and the phototransistor Q1 and the photodiode D2 and the phototransistor Q2 are photocouplers and are switched according to a process signal or a sensing signal.

In order to count the quantity of wafers, up / down counters 34 and 36 are configured.

In the up / down counter 34, the up terminal UP is configured such that a constant voltage Vcc of the same phase as the process signal is applied according to the switching of the phototransistor Q1, and the input terminals A, B, C and D are applied. ) And the down terminal DN are configured to apply a voltage applied to the grounded resistor R1 connected to the emitter of the phototransistor Q1.

In the up / down counter 36, the up terminal UP is configured such that the result of shifting the output of the up / down counter 34 is applied from the terminal CO, and the input terminals A, B, C and D) and the down terminal DN are configured to apply a voltage applied to the resistor R1.

The load terminal LOAD of the up / down counter 34 is configured to apply a constant voltage Vcc, and the clear terminals CLR of the up / down counters 34 and 36 are connected to each other.

The load terminal LOAD of the up / down counter 36 is configured such that the constant voltage Vcc applied to the collector of the phototransistor Q2 is inverted and applied to the phase of the carrier signal, and the emitter of the phototransistor Q2 is It is grounded through resistor R2.

Each of the output terminals A, B, C and D of the up / down counters 34 and 36 is connected to apply the count result to the character generators 38 and 40, respectively. 40 is configured to drive seven-segments 42 and 44, respectively.

Meanwhile, the quantity corresponding to one lot for ion implantation is set by the quantity setting unit 46, and the quantity setting unit 46 is composed of a plurality of dip switches, and each dip switch to which a constant voltage Vcc is applied. Is connected to the resistor pack 47 and is connected to the input terminal of the NAND gates 48 to 62 in parallel thereto.

As a result, the up / down counters 34 and 36 apply the count signals a1 to d1 and a2 to d2 from the respective output terminals QA to QD to the input terminals of the respective NAND gates 48 to 62, respectively. ) Is configured to apply setting signals S1 to S8 according to the switching state of each dip switch to the other input terminal of each NAND gate 48 to 62.

In addition, the NAND gate 48 and the NAND gate 50 are configured to apply an output signal to the input terminal of the OR gate 64. Similarly, the NAND gate 52, the NAND gate 54, and the NAND gate 56 are provided. ) And the NAND gate 58, and the NAND gate 60 and the NAND gate 62 are also configured to apply an output signal to the input terminals of the respective oA gates 66 to 70.

The oracle 64 and the oragate 66 are configured to apply an output signal to the input terminal of the oragate 72, and the oragate 68 and the oragate 70 are the input terminals of the oragate 74. It is configured to apply an output signal.

The oracle 72 and the oragate 74 are configured to apply an output signal to an input terminal of the oragate 76, and to output an output signal of the oragate 76 to an input terminal of the NAND gate 78. Consists of. The other input terminal of the NAND gate 78 is configured such that the constant voltage Vcc is switched by the transistor Q2 so that a predetermined level of voltage applied to the resistor R2 is applied.

The output of the NAND gate 78 is applied to the base of the transistor Q3 through the resistor R3, and the relay 80 and the reset switch 84 are connected in parallel to the collector side of the transistor Q3.

In addition, a diode D3 to which the constant voltage Vcc is applied is connected in parallel to the driving side of the relay 80, and the relay 80 is divided into a first switching part and a second switching part, and the first of the first switching part. The resistor R4 and the diode D4 to which the constant voltage Vcc is applied are connected to the contact point, and the resistor R5 and the diode D5 to which the constant voltage Vcc is applied are connected to the contact point, and the resistor R5 and the diode are connected to the second contact point. The buzzer 82 is connected in parallel with (D5). The common terminal of the first switching portion and the second switching portion is grounded, and a reset switch 84 is connected to one contact point of the second switching portion.

Accordingly, when the wafer is loaded on the carrier to perform ion implantation, the carrier loading is sensed so that a low level carrier signal is applied to the photodiode D2, and when the ion implantation of the buried wafer is completed, a process signal for the ion wafer is completed. It is applied to the photodiode D1 as a clock signal.

The photodiode D1 emits light as much as the duty of the clock signal, which is a process signal, the phototransistor Q1 is switched according to the light emission, the constant voltage Vcc is switched, and applied to the up / down counter 34. Down counter 34 and up / down counter 34 perform binary counts from (00000000) ₂ .

Each count result of the up / down counters 34 and 34 is applied to the character generators 38 and 40 by 4 bits, respectively, and the character generators 38 and 40 are transferred to the corresponding 7-segment 42. 44. A 7-bit signal is applied to display a predetermined number. Specifically, when the count signal of (00000100) ₂ is applied to the character generators 38 and 40, the character generator 38 displays '4' in the 7-segment 42, and the character generator 40 is Display '0' in 7-segment 44.

The count signals of the up / down counters 34 and 36 are applied to the NAND gates 48 to 62. The other input side of each NAND gate 48 to 62 has a logical '1' set in accordance with the value set in the quantity setting section 46. Thus, the NAND gates 48 to 62 vary in output in accordance with the signal applied from the up / down counters 34 and 36.

That is, when a high level logical '1' is applied to the NAND gates 48 to 62 from the up / down counters 34 and 36, a low level logical '0' is applied to each of the oragate 64 to 70. When a logical '0' is applied to the NAND gates 48 to 62 from the up / down counters 34 and 36, the logical '1' is applied to each of the oragates 64 to 70.

As described above, the signal applied to each of the orifices 64 to 70 is OR-combined, and the combined signal is again ora-combined at the oragates 74 to 76, and the combined result is NAND. Is applied to the gate 78.

Eventually, when the counts 34 and 36 output a count signal between (00000000) ₂ and (11111110) _{2 according} to the process signal, at least one of the NAND gates 48 to 62 outputs a logical '1' at which the high level is generated. Accordingly, a high level logical '1' is applied to the input side of the NAND gate 78 through the combination of the oragates 64 to 76. When the count signal is applied to the NAND gates 46 to 62 in the full count state of the up / down counts 34 and 36, that is, (11111111) ₂ , the output signals of the NAND gates 46 to 62 are applied. Since both are low level logical '0', a logical '0' is applied to the input side of the NAND gate 78 through the combination of the oragate 64 to 76.

Since the carrier is present while the count is being performed, the carrier signal is applied at a low level, and thus a low level, that is, a logical '0', is applied to the NAND gate 78 according to the turn-off of the transistor Q2. In contrast, when the count is not performed, the high level corresponding to the turn-on of the transistor Q2 is applied to the NAND gate 78, that is, a logical '1'.

As a result, when the process is completed, and the count is completed without skipping each wafer on which the process is performed, the NAND gate 78 outputs a high level signal by applying logic signals to '0', respectively. If the wafer is not counted or the wafer is skipped by a predetermined amount even when the process is completed, the NAND gate 78 outputs a low level signal by applying logic signals of '0' and '1'. do.

Therefore, upon completion of the normal process, the transistor Q3 is turned on by the high level output signal of the NAND gate 78 so that a connection is made to the first contact point of the first and second switching portions of the relay 80, and thus a diode. (D4) is emitted to indicate a steady state. However, since the transistor Q3 is turned off by the low level output signal of the NAND gate 78 during the process or during abnormal counting due to wafer skip, the connection is made to the second contact of the first and second switching parts. Therefore, the light emitting diode D5 emits light to indicate an abnormal state, and the buzzer 82 is operated.

The light emission of the light emitting diode D5 and the operation of the buzzer 82 can be released by the operation of the reset switch 84.

As a result, when a wafer skip occurs during the process, the ion implantation process for the predetermined quantity is completed in the facility itself, but the light emitting diode D5 maintains the light emitting state, so that the operator can easily check the abnormality of the wafer count.

Therefore, the operation of the count of the wafer is visually and audibly confirmed, the count of the wafer is collectively made based on a predetermined time point, and whether or not to perform the process in real time without checking whether the wafer is performed using the measuring equipment is unnecessary. It is possible to confirm the operation, and the alarm operation for the occurrence of skip or count abnormality of the wafer is performed to enable stable management of the equipment and to improve the yield.

Therefore, according to the present invention, the management time of the wafer is unified, and the workability is improved, and the wafer skip is automatically sensed and the alarm operation is performed to maximize the control of the equipment and the process, thereby improving the yield.

Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical scope of the present invention, and such modifications and modifications are within the scope of the appended claims.

Claims (10)

In the first and second end stations of the ion implantation chamber, ion implantation is performed on the wafer loaded in the carrier, the wafer is loaded from the load lock chamber, and the ion control chamber controls the operations of the ion implantation chamber and the load lock chamber. In the wafer counting device of the injection facility, The count signals applied to the first and second counters for counting the cumulative amount of wafers on which the processes installed in the first and second end stations are performed are applied to the display unit provided in the operator panel for operating the process control unit. A wafer counting device of an ion implantation system, characterized in that the number of wafers is counted at the same process point as the first and second counters. The method of claim 1, The process point is a wafer counting device of the ion implantation facility, characterized in that the ion implantation is completed for each wafer. The method of claim 1, The process time point is a wafer counting device of the ion implantation facility, characterized in that the wafer is picked up (Pick Up) to perform the process in the load lock chamber. The method of claim 1, And the count signal is configured to be output through the first and second end station connection assemblies. A wafer counting device of an ion implantation apparatus comprising a display means in which a wafer loaded in a carrier of a load lock chamber is loaded into an ion implantation chamber and ion implanted, and display means for digitally displaying the number of wafers on an operator operation unit for managing a process is provided. Quantity setting means in which a unit quantity of the wafer on which the process is performed is set; Discriminating means for determining the normality and abnormality of the process by referring to the wafer quantity applied as the count signal in the display means and the signal for the unit quantity set in the quantity setting means; And Alarm means for performing alarm operations corresponding to normal and abnormality with reference to the result determined by the determining means and the loading state of the carrier; Wafer counting device of the ion implantation equipment characterized in that it comprises a. The method of claim 5, And the quantity setting means comprises a plurality of switching elements, wherein the switching signal of each switching element is applied as the unit quantity signal as the determination signal. The method of claim 5, wherein the determining means, First logical combining means for NAND combining the number of wafers applied as a count signal by the display means and the signal for the unit quantity set by the quantity setting means, respectively; Second logical combining means for ORing each of the NAND combined results in the first logical combining means; And Third logical combining means for NAND combining a result of the second logical combining means with a loading state of the carrier; Wafer counting device of the ion implantation equipment characterized in that it comprises a. According to claim 5, The alarm means; Switching means switched in accordance with the output of the discriminating means; A relay which is switched in conjunction with the switching means; A normal alarm light connected to the first switching contact of the relay; And An abnormality alarm lamp connected to the second switching contact of the relay; Wafer counting device of the ion implantation equipment characterized in that it comprises a. The method of claim 8, And a reset switch connected to the relay in parallel with the switching means to reset the switching state. The method of claim 8, Wafer counting device of the ion implantation equipment, characterized in that the buzzer is further configured in parallel to the abnormal alarm.