KR100223722B1 - Motion detection apparatus - Google Patents

Abstract

[Purpose] The circuit scale in the apparatus for detecting the motion vector or the like is reduced.

[Configuration] The data A _K to D _K in the search range are supplied for every K cycles to the input terminals 11 of the circuit 1 provided in parallel with means for calculating the absolute absolute value, and the data from this circuit 1 is The addition means and the registers are supplied to the differential absolute value calculating circuit 2 provided in parallel, sequentially added for each cycle, and the addition data is compared in the comparison circuit 3.

Description

Motion detection device

1 is a conceptual diagram showing a configuration of an example of a motion detection apparatus according to the present invention.

2a and 2b are diagrams for explanation thereof.

3a and 3b are diagrams for explanation thereof.

4 is a configuration diagram of an example of the differential absolute value calculation circuit 1.

5 is a configuration diagram of an example of the differential absolute value calculation circuit 2.

6 is a configuration diagram of another example of the differential absolute value calculation circuit 1.

7 is a configuration diagram of another example of the differential absolute value calculation circuit 2.

8 is a configuration diagram of an example of an apparatus by time division multiplexing.

9 is a diagram for explaining the generalized case.

10 is a conceptual diagram showing a configuration of an example of a generalized motion detection device.

* Explanation of symbols for main parts of the drawings

1: differential absolute value calculating circuit 2: differential absolute value calculating circuit

3: comparison circuit 11: input terminal

31: output terminal

The present invention relates to, for example, a motion detection apparatus for high efficiency encoding of motion image data and used for detection of motion vectors.

For example, a high efficiency encoding of motion image data is used, and a motion detection device is used to detect motion vectors and the like. In such a motion detection apparatus, for example, when detecting by full search block matching, the pixel in the search range is b _ij , the pixel of the reference data block is a _ij , and the absolute difference value m _ij for each pixel is used.

[1]

m _ij = _{I J} | b _i + I _{j + J} -a _IJ |

Is calculated.

In this case, however, the relationship between b _{i + Ij + J} and a _IJ is complicated. For this reason, in the conventional apparatus, for example, all data b _{ij in the} search range is taken into a memory built into the LSI, and b _ij corresponding to a _IJ is read from the memory and calculated. Therefore, in the conventional apparatus, when LSI is formed, a memory must be provided inside, resulting in a large circuit scale.

The problem to be solved is that in the conventional apparatus, the circuit scale in the case of LSI becomes large.

A first means according to the present invention is to compare pixels b _ij in a search range configured as a predetermined decimal number and pixels a _{ij in} an existing data block configured as the number of pixels smaller than the predetermined decimal number by the arrangement state. And arithmetic means (1, 2) for calculating harmonics of the absolute difference values of the corresponding pixels in the search range of each pixel in the block for each corresponding state of the pixels taken within the search range. In the operation detection state in which the operation state is detected by the operation, each pixel within the search range is set in advance for the time inputted to the calculation means, and the pixels within the search range are input to the calculation means according to the time. And an operation for performing the operation with the pixel in the reference data block.

The second means according to the present invention, in the first means, corresponds to the pixel in the block even when the pixel b _{ij in} the search range and the corresponding state of the pixel a _ij of the reference data block are in a corresponding state. The third means according to the present invention is set so that the pixels within the search range all match the time inputted to the calculation means. In the second means, each pixel (b _ij) within the search range is used. ) And the reference data block a _ij are performed in the order of the time regardless of the corresponding state.

According to a fourth aspect of the present invention, in the first means, the existing data block a _ij is a pixel of the current field, and the pixel b _{ij in} the search range is a pixel before one field or more or after one field or more. Motion detection device, characterized in that.

The fifth means according to the present invention compares the pixels b _{ij in the} search range configured as the predetermined number of pixels and the pixels a _ij in the reference data block configured as the number of pixels smaller than the predetermined number of pixels by the arrangement state. And an input unit 11 for inputting pixels within the search range in a predetermined order, pixels within the search range, and corresponding pixels in the reference data block. A calculation circuit 1 for calculating the absolute difference value and detection means 2, 3 for detecting the operation state based on the calculation result, wherein the calculation circuit corresponds to the pixels taken by the block within the search range. For each state, the absolute difference value of each pixel in the block and the corresponding pixel in the search range is calculated, and the calculation is performed in the above order. An operation detecting device characterized in that the treatment is carried out so that in parallel with respect to each corresponding state.

A sixth means according to the present invention is the motion detection device, characterized in that in the fifth means, the detection means is (2) for calculating the harmonic of the absolute difference value output from the calculation circuit (1). .

A seventh means according to the present invention is characterized in that in the sixth means, the harmonic 2 for each of the corresponding states is compared to detect (3) the minimum value, thereby obtaining a motion vector. It is a detection device.

According to this, by calculating the pixels within the search range in a predetermined order, it is possible to disable the built-in memory and perform good motion detection with a simple configuration.

1 shows a conceptual diagram. As a specific example, full search block matching using a search range of 5x5 pixels and an existing data block of 3x3 pixels when the motion vector is to be obtained as a range of (+/- 1) x (+/- 1) pixels will be described. Of course, this can be generalized (search range exf pixels, reference data block gxp pixels).

In the figure, the pixel b _ij in the search range and the reference data block pixel a _ij are configured as shown in FIG. In this case, the upper left subscript of the search range is (00). Therefore, the difference absolute value screen of this circuit, if a motion vector _(ij) in the (m _ij) is

[Number 2]

9 types m _ij in total, i = 0-2 and j = 0-2 are calculated, and their magnitudes are compared, and the minimum value ( _ij ) is calculated.

Now, in the above description, the pixels in the search range of b _ij are named as A _K , B _K , C _K , and D _K , as shown in FIG. 3. As a result, the differential absolute circuit m _ij is

[Number 3]

It becomes

When this number (3) receives the order to add,

[Number 4]

It becomes

In this number (4), when the absolute value of the right side of each equation is set to 0 to 8 terms, the subscripts a _{ij to} D of each term correspond to the number of the term ranking. On the other hand, suppose that this subscript means that the data is input to the cycle. For example, by setting nine parallel calculation means for the difference absolute value [1 (input data)-a _ij ], The zero term value of the equation can be calculated, and then the first to eighth value can be calculated every 1 to 8 cycles.

That is, in the above conceptual diagram, 1 is the difference absolute value calculation circuit, for example, in which nine means for calculating the above absolute difference value are provided in parallel. In this circuit 1, four input terminals 11 are provided, and the data of A _{K to} D _K are supplied to the input terminal 11 at the K-th cycle, respectively. In addition, since the data of b _ij , D, 6, 7th C, D, 8th B, C, D in the 2.5th cycle is not used in the actual calculation as shown in Fig. 4, the data between them Is supplied with any damier data. As a result, in the circuit 1, nine values of each term are taken out for each cycle.

Nine pieces of data in this circuit 1 are supplied to the differential absolute value calculation circuit 2. In this circuit 2, nine addition means and nine registers (unit delay means) are provided in parallel. Nine zero term data supplied at the zeroth cycle are stored in nine registers. Nine ninth data stored in this register are added to nine ninth data supplied in the first cycle and stored in nine registers. Thereafter, the nine second to eighth data items supplied in the second to eighth cycles are sequentially added to the nine data stored in the register. Thereby, calculation which adds each term in each formula of the above-mentioned number (4) is performed, and difference absolute value (m _ij ) is calculated | required. The absolute absolute value m _ij obtained by this circuit 2 is supplied to the differential absolute value and the comparison circuit 3, and the smallest m _ij is obtained. And ( _ij ) is taken out to the output terminal 31 as an operation vector.

In this manner, according to the above-described apparatus, by inputting pixels within the search range in a predetermined order and performing calculations, it is possible to perform good operation detection with a simple configuration by making the internal memory unavailable.

The concrete circuit of the difference absolute value calculation circuit 1 and the difference absolute value calculation circuit 2 is demonstrated below. In other words, in the above description, the calculation of the nineth term K is performed simply on the Kth cycle.However, which calculation means is specifically assigned to the calculation of the number K term of the number four, in the nine calculation means provided in parallel. As a result, the circuit can be further simplified.

4 shows a specific example of the differential absolute value calculation circuit 1. In this figure, nine differential absolute calculation means U _{0 to} U ₂₂ are provided. These calculation means (U ₀ ~U ₂₂₎ to pixel (a ₀ ~a ₂₂₎ of an existing data block are respectively supplied. These calculation means with that (U ₀ ~U _22), the data of the A _K ~D _K at the input terminal 11 is selected by the selector (V ₀ ~V ₂₂₎ of each four-input is supplied. Here, the control signals W _{0 to} W ₂ and (X _{0 to} X ₂ ) are supplied to the selectors V _{0 to} V ₂₂ , respectively. When W and X are all at low level, A _K and W are high, X and low level, B _K and W are low and X is high level, and C _K , W and X are all high level. D _K is selected and these control signals W _{0 to} W ₂ and (X _{0 to} X ₂ ) are supplied as shown in Table 1 below in accordance with the cycle.

TABLE 1

L is low, H is high

This angle calculation means by U ₀ ~U ₂₂ with multifarious values including a00~a22 the number 4, respectively _(10-122) are taken in each cycle. Here, when the value of a _ij l t of the second cycle in l _{ij (t),} is 4 in the above-described

Number 5

It becomes

5 shows a specific example of the differential absolute value calculation circuit 2.

In the figure, nine addition means W _{0 to} W ₂₂ and nine registers X _{0 to} X ₂₂ are provided. The above-mentioned values l _0- l ₂₂ are supplied to these calculation means W _0- W ₂₂ , respectively. The outputs of the adding means W _{0 to} W ₂₂ are supplied to the registers X _{0 to} X ₂₂ . These registers X _{0 to} X ₂₂ are driven by a pulse equal to the data rate every cycle, and a clear pulse is input and reset every zero cycle. The output of these registers (X ₀ ~X ₂₂₎ via the one terminal of each selector on the second input (Y ₀ ~Y ₂₂₎ and connected so as to traverse in the longitudinal direction, the other terminal of the selector (Y ₀ ~Y ₂₂₎ It is connected so as to circulate in the transverse direction via.

In this circuit 2, the selectors Y _{0 to} Y ₂₂ are connected to one terminal at the 1st, 2nd, 4th, 5th, 7th and 8th cycles, and to the other terminal at the 0th, 3rd, 6th and cycles. Connection is made.

Thereby, the addition of each of the formulas of number 5 is performed, and the difference absolute value m _ij is stored in each register (X _{0 to} X ₂₂ ) at the end of the eighth cycle. In addition, the storage position of the differential absolute value m _ij is set to the point symmetrical position centering on X ₁₁ with respect to the subscripts of the registers X _{0 to} X ₂₂ . The difference absolute value m _ij stored in these registers X _{0 to} X ₂₂ is supplied to the comparison circuit 3 after the completion of eight cycles, the smallest m _ij is obtained, and the operation vector ( _ij) is obtained. ) Is calculated. In addition, since the specific example of the comparison circuit 3 is a well-known technique, description is abbreviate | omitted.

6 shows another specific example of the differential absolute value calculation circuit 1. In the figure, the pixels a _{0 to a 22} of the existing data blocks are circulatedly supplied to the nine difference absolute calculation means U _{0 to} U ₂₂ , respectively. That is nine register (Z ₀ ~Z ₂₂₎ is installed and the output of these registers (Z ₀ ~Z ₂₂₎ is supplied to each of the calculation means (U ₀ ~U _22), these registers (Z ₀ ~Z ₂₂₎ Is circulated in the lateral direction and connected. The pixel (a ₀ ~a ₂₂₎ are stored in respective registers (Z ₀ ~Z _22), those of the register (Z ₀ ~Z ₂₂₎ is supplied with a third clock of the data input light. This calculation means (U ₀ ~U ₂₂₎ by the pixel is (a ₀ ~a ₂₂₎ is fed by rotation every three time. A selector (V ₀ ~V ₂₂₎ a control signal (W ₀ ~W ₂₎ and supplied to the (X ₀ ~X ₂₎ is supplied, as shown in the following table 2 in accordance with the cycle.

TABLE 2

This angle calculation means by the (U ₀ ~U ₂₂₎ In paragraph containing a _ij00 ~a _ij22 of number 4, each value (h ₀ ~h ₂₂₎ are taken in each cycle.

Here, if the value of h _{ij at the} t cycle is h _ij (t),

The above-mentioned number (4)

[Jos 6]

It becomes

7 shows another specific example of the differential absolute value calculation circuit 2. In the figure, nine addition means W _{0 to} W ₂₂ and nine registers X _{0 to} X ₂₂ are provided. These calculation means (W ₀ ~W _22), there are respectively fed the value (h ₀ ~h ₂₂₎ described above. The outputs of the adding means W _{0 to} W ₂₂ are supplied to the registers X _{0 to} X ₂₂ , respectively. These registers X _{0 to} X ₂₂ are driven by pulses equal to the data rate for each cycle, and a clear pulse is input and reset every 0 cycles. In this circuit, the outputs of these registers X _{0 to} X ₂₂ are connected in the longitudinal direction. This way, each addition of a can (6) is carried out by, in the end of the eighth cycle, the difference absolute value Chemistry (m _ij) are stored in respective registers (X ₀ ~X _{22). Incidentally} , the storage positions of the absolute difference value m _ij are respectively located in the city.

The difference absolute value m _ij stored in these registers X _{0 to} X ₂₂ is supplied to the comparison circuit 3 after the end of 8 cyclesep, and the smallest m _ij is obtained to obtain ( _ij ) of the motion vector. Is calculated. In addition, since the specific example of the comparison circuit 3 is a well-known technique, description is abbreviate | omitted. In this manner, the absolute difference value calculation circuit 1 and the absolute difference value calculation circuit 2 can be realized.

With respect to the circuit described in the other specific examples described above, when the processing speed of each calculation means is sufficiently fast, the circuit can be further simplified by time division multiplexing. That is, in FIG. 8, time division processing of the absolute difference value calculating circuit 1 of FIG. 6 and the absolute absolute value calculating circuit 2 of FIG. 7 is carried out in three times. In this figure, the means for calculating the difference absolute value is provided so that nine registers Z _{0 to} Z ₂₂ , in which three of U _{0 to} U ₂ are provided, form three circulation loops in the transverse direction. The output of these registers (Z ₀ ~Z ₂₂₎ is selected as the three-input selector (S ₀ ~S ₂₎ is supplied to the calculation means (U ₀ ~U _2). The addition means is also provided with three of W _{0 to} W ₂ , and nine registers (X _{0 to} X ₂₂ ) are provided as slaves. As these circuits are driven by pulses three times the data rate, the same processing as described above is performed. In this way, the number of calculation means and addition means can be reduced.

In the above example, full search block matching using a four color gamut of 5 × 5 pixels and a reference data block of 3 × 3 pixels has been described. In one case, In this case, the motion vector can be obtained in the range of [± (e−q) / 2] × [± (f−p) / 2]. In this case, as shown in Fig. 9, the search range of the e x f pixels is divided for each g + q pixels, and processing is performed.

On the other hand, as shown in the conceptual diagram of FIG. 10, the difference absolute value calculation circuit 1 is provided with an input terminal 11 of (e / g) x (f / p), and the calculation circuit 1 has (e-g). Calculation means U of +1) x (f-p +1) difference absolute values is provided. For example, for each of the above-mentioned divisions, the pixels constituting them are named ah, ah, right ..., and at the 0th cycle, the pixel sub coordinates (n1g, n2p) n1 = 0, 1, 2, ... ., n ₂ = 0, 1, 2 ...] are input to the input terminal 11, and at the 1st cycle, the pixel 2 (coordinates (n ₁ g + 1, n ₂ p) n1 = 0, 1, 2 ..., n ₂ = 0, 1, 2 ...] are input to the input terminal 11, and at the second cycle, the pixel right [coordinate (n ₁ g +2, n ₂ p) n1 = 0, 1 , 2..., N ₂ = 0, 1, 2... Are input to the input terminal 11, and the sequential pixels Ah, 2, ...

(E-q +1) x (f-p + 1) outputs in this difference absolute value calculation circuit 1 are (e-q +1) x (f-p + 1) addition means W and Supplied to the differential absolute value calculating circuit 2 to be the register X, and the outputs of (e-q +1) x (f-p + 1) in the differential absolute value calculating circuit 2 are compared circuits. Supplied to (3), the smallest difference absolute value is obtained, and the motion vector is calculated.

Also in this circuit, the number of calculation means and addition means can be reduced by the time division multiplexing process as described above.

By having means for calculating the quadratic of the difference, instead of the means for calculating the absolute difference value U, it is possible to construct a full search block matching by the minimum of the difference sublimation.

According to the present invention, by inputting and calculating pixels within a search range in a predetermined order, it becomes possible to perform good motion detection with a simple configuration by disabling the internal memory.

Claims (7)

When a pixel in a search range configured as a predetermined number of pixels and a pixel in a reference data block configured as pixels smaller than the predetermined number of pixels are compared according to the arrangement state, for each corresponding state of the pixels handled by the block within the search range. And an operation means for calculating a harmonic of the difference absolute blood of each pixel in the block and the corresponding pixel in the search range, wherein the motion detection device detects an operation state by the harmonic. And setting the time input to the calculation means, and performing the calculation with the pixels in the pointing data block corresponding to the time sequentially. The method of claim 1, In any corresponding state of the pixel within the search range and the pixel of the reference data block, the setting is performed such that the pixel within the search range corresponding to the pixel in the block matches all the time inputted to the calculation means. An operation detection device. The method of claim 2, And the comparison operation between the respective pixels within the search range and the reference data block is performed in the order of the time, regardless of the corresponding state. The method of claim 1, And said reference data block is a pixel of a current field, and a pixel within said search range is a pixel before one field or more or after one field or more. The pixels in the search range and the pixels in the corresponding existing data block are compared by comparing the pixels in the search range configured as the predetermined number of pixels with the pixels in the existing data block configured as the number of pixels smaller than the predetermined number of pixels by the arrangement state. A calculation circuit for calculating the absolute difference value, and a detection means for detecting the operation state based on the calculation result, wherein the calculation furnace corresponds to each pixel in the block for each corresponding state of pixels taken by the block within the search range. And calculating an absolute difference value of the corresponding pixel within the search range, wherein the calculation is performed such that processing is performed in parallel with respect to each of the corresponding states according to the order. The method of claim 5, And the detecting means calculates a harmonic of the absolute difference value output from the calculating circuit. The method of claim 6, And detecting the minimum value by comparing the harmonics for the corresponding states, thereby obtaining a motion vector.