KR100221829B1 - Pattern data generating apparatus for stepping motor drive - Google Patents

Abstract

The present invention relates to a stepping motor drive pattern data generator for automatically generating and outputting pattern data for driving a stepping motor based on input control data, A second latch means for storing first reference data corresponding to a one-phase excitation mode of the step motor and second reference data corresponding to a two-phase excitation mode; A first latch circuit for latching the first or second reference data output from the second latch means, the least significant bit output being coupled to the first direction shift data input, the most significant bit output being coupled to the second direction shift data input, Shifting the loaded data based on rotation direction setting data output from the first latch means each time a signal is input Selecting means for selectively outputting the outputs of the first and second shift registers in accordance with first and second level selection signals, first and second shift registers for outputting shifted data, And a mode control means for selectively supplying a clock signal to the first or second shift register based on the excitation type data to be outputted and outputting a first or second level selection signal to the selection means .

Description

Pattern data generator for step motor drive

FIG. 1 is a block diagram showing a general step motor driving device. FIG.

FIGS. 2 and 3 are operational waveforms for explaining the operation of the device shown in FIG. 1;

FIG. 4 is a block diagram showing a step motor driving device according to a first aspect of the present invention; FIG.

5 shows the operation timing of the apparatus shown in FIG.

FIG. 6 and FIG. 7 are data formats showing an example of the format of data supplied from the microprocessor to the pattern data generator in FIG.

FIG. 8 is a circuit diagram showing a configuration of a pattern data generator in FIG. 4; FIG.

FIG. 9 is a block diagram showing the configuration of the mode control unit in FIG.

FIG. 10 is an operation timing diagram for explaining the operation of FIG. 9; FIG.

FIG. 11 is a block diagram showing a step motor driving apparatus according to a second aspect of the present invention; FIG.

12 is an operation timing diagram of the apparatus shown in Fig. 11; Fig.

FIG. 13 is a circuit diagram showing a configuration of a pattern data generating apparatus in FIG. 11; FIG.

* A brief description of the main parts of the drawing

3: motor driving unit 41: microprocessor

42: pattern data generator 81, 82: latch circuit

83, 84: Shift register 85: Mode control section

86: selector 91: first clock signal output section

92: second clock signal output section 93: selection signal output section

90: D flip flop 101: Microprocessor

102: pattern data generator 110: counter

SM: Step motor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stepping motor driving apparatus for driving and controlling a stepping motor. More particularly, the present invention relates to a stepping motor driving apparatus for automatically generating and outputting pattern data for driving a stepping motor, And a pattern data generator.

Generally, a step motor is a motor in which a rotor rotates at a constant rotation angle in accordance with the input of a pulse signal. Such a step motor controls precisely the amount of rotation of the motor based on the number of pulses supplied to the motor It is widely used in printers, electric typewriters or plotters requiring precise control.

FIG. 1 is a block diagram showing the configuration of a general step motor driving apparatus for driving the above-mentioned step motor.

In FIG. 1, reference numeral 1 denotes a microprocessor for outputting pattern data for driving and controlling a microprocessor. The microprocessor 1 controls whether the stepper motor SM is driven in a one-phase or two-phase mode, The predetermined pattern data is output according to whether the rotation is to be performed.

Reference numeral 2 denotes a latch circuit for latching the pattern data output from the microprocessor 1 and 3 denotes a motor driver for driving the stepper motor SM based on the data latched in the latch circuit 2 Where the motor drive unit 3 outputs a high or low level pulse signal to the stepper motor SM depending on whether each latch data of the latch circuit 2 is "1" or "0", for example.

Then, the step motor SM rotates in the forward or reverse direction by an amount corresponding to the number of pulses of the pulse signal output from the motor driving unit 3. [

That is, in the above configuration, the microprocessor 1 outputs the pattern data for driving the step motor SM, thereby driving the step motor SM in the predetermined drive mode.

The microprocessor 1 first drives the step motor SM in the forward rotation mode of one phase as shown in the following Table 1 and outputs the pattern data A , B, ) To be "1 " one by one to the latch circuit 2 in sequence.

The motor driving section 3 outputs data latched in the latch circuit 2 by the microprocessor 1, that is, the pattern data A, B, , The step motor SM is driven in the one-phase forward rotation mode by outputting the pulse signal as shown in Fig. 2 to the step motor SM.

At this time, when the step motor SM is driven in the reverse direction, the pattern data A, B, Quot; 1 "in the opposite direction to the forward rotation drive described above.

On the other hand, when the step motor SM is driven in the two-phase forward rotation mode, the microprocessor 1 sequentially latches the pattern data shown in the following Table 3 to the latch circuit 2,

The motor driving section 3 drives the step motor SM in the forward rotation mode of two phases by outputting the pulse signal shown in Fig. 3 to the step motor SM on the basis of the pattern data in the above Table 3. [

Also in this case, when the step motor SM is driven in the two-phase reverse rotation mode, pattern data is sequentially changed in the direction opposite to that of Table 3 as shown in Table 4 below.

"" "" "" "" "" "" ""

In Table 5, x denotes a Do not care bit.

FIG. 8 is a block diagram showing the configuration of the pattern data generator in FIG. 4, wherein reference numeral 81 denotes a latch circuit for latching data (DATA) input when the first control signal CSO is low level And 82 is a second latch circuit for latching and outputting data DATA to be inputted when the second control signal CS1 is at a low level.

Reference numerals 83 and 84 denote load signals ( (Bit 0 to bit 3) and the upper 4 bits (bits 4 to 7) of the latch data output from the second latch circuit 82 are loaded, respectively, and a mode The first and second shift registers 83 and 84 are first and second shift registers which output the data in parallel while shifting the loaded data in accordance with a clock signal (CLK) signal input from the control unit 85, The most significant bit output QA is coupled to the right shift data input terminal SR and the most significant bit output QD is coupled to the left shift data input terminal SL and also from the first latch circuit 81 The data loaded every time the clock signal CLK is input is shifted leftward or rightward based on data S0 and S1 for setting the rotational direction of the step motor SM.

That is, the first and second shift registers 83 and 84 are set so that the 2-bit data S0 and S1 applied from the first latch circuit 81, that is, the rotation direction setting data of the step motor SM, Quot ;, the loaded data is output while sequentially shifting the loaded data from QA to the direction of QD (right direction). When the rotational direction setting data is "1 ", the loaded data is shifted from QD ) And sequentially outputs the output. When the rightward shift is performed at this time, the output of the most significant bit QD is input to the right shift data input terminal SR and the output of the next least significant bit output terminal QA when the next clock signal CLK is input The output of the least significant bit QA is input to the left shift data input SL and the output of the next most significant bit output QD is input when the next clock signal CLK is input.

8, reference numeral 85 denotes a circuit for selectively outputting the first and second clock signals CLK1 and CLK2 according to a third bit (bit 2) signal output from the first latch circuit 81, A mode control unit for outputting the first or second level selection signal S to the selector 86 to be described later when the bit 2 signal output from the first latch circuit 81 is "1" That is, a single-mode or two-phase single mode excitation method, the first and second clock signals CLK1 are simultaneously output based on the input clock signal CLK, and the selector 86 outputs, for example, When the bit 2 signal output from the first latch circuit 81 is "0 ", that is, when the first latch circuit 81 outputs the first and second clock signals CLK1 and CLK2, CLK2 and the first and second level selection signals alternately.

FIG. 9 is a block diagram showing the configuration of the mode control unit 85. In FIG. 9, reference numeral 90 denotes a clock signal CLK operated in accordance with an externally applied clock signal CLK, Is a D flip flop coupled to the input terminal D, and AND1 and AND2 are the outputs of the D flip flop 90 (Q, ) And the clock signal (CLK) and outputs the resultant signal.

In the figure, reference numeral 91 denotes a first shift register 83 which processes the output of the first AND gate AND1 and the clock signal CLK according to a mode selection signal MODE, And 92 is a first clock signal output unit for outputting the signal CLK1 and 92 for processing the output of the second AND gate AND1 and the clock signal CLK in accordance with the mode selection signal MODE, A second clock signal output unit 93 for outputting a second clock signal CLK2 applied to the D flip flop 90 according to the mode selection signal MODE, And outputs a selection signal S for controlling the operation of the selector 86 to be described later.

Here, the third bit signal applied from the first latch circuit 81 is used as the mode selection signal MODE.

The first clock signal output unit 91 includes an inverter IV1 for inverting the mode selection signal MODE and an output of the first AND gate AND1, An AND gate AND4 for multiplying the output of the inverter IV2 by the clock signal CLK and an inverter IV2 for inverting the output of the inverter IV1; AND3) AND4 (OR1). When the mode selection signal MODE is "0 ", the output of the first AND gate AND1 is set to the mode And outputs the clock signal CLK as the first clock signal CLK1 when the selection signal MODE is "1 ".

The second clock signal output unit 92 includes an inverter IV3 for inverting the mode selection signal MODE and an output of the second AND gate AND2, An AND gate AND5 for inverting the output of the inverter IV3, an AND gate AND6 for ANDing the output of the inverter IV4 and the clock signal CLK, AND5 (AND6). When the mode selection signal MODE is "0 ", the output of the second AND gate AND2 is set to the mode And outputs the clock signal CLK as the second clock signal CLK2 when the selection signal MODE is "1 ".

The selection signal output unit 93 includes an inverter IV5 for inverting the mode selection signal MODE and an inverted output of the inverter IV5 and the D flip- An AND gate AND8 for inverting the output of the inverter IV5 and an AND gate 8 for ANDing the output of the inverter IV6 and the mode selection signal MODE, An OR gate OR3 for ORing the outputs of the AND gates AND7 and AND8 and an inverter IV7 for inverting the output of the OR gate OR3. Quot; 0 ", the inverted output of the D flip-flop 90 , And outputs a low-level selection signal when the mode selection signal MODE is "1 ".

That is, in the above configuration, when the clock signal CLK as shown in FIG. 10 (a) is inputted, the D flip-flop 90 outputs the output signals Q, (B) and (c) through the D flip-flop 90 and then outputs the signals (Q, Are logically multiplied with the clock signal CLK through the AND gates AND1 and AND2 and the clock signals as shown in FIG. 10 (d) and (e) are output from the AND gates AND1 and AND2.

The first and second clock signal output units 91 selectively output the outputs of the AND gates AND1 and AND2 and the input clock CLK according to an input mode selection signal MODE. That is, when the mode selection signal MODE is "0 ", the outputs of the inverters IV1 and IV3 become high level and the outputs of the inverters IV2 and IV4 become low level, The clock signals of FIGS. 10 (d) and 10 (e) are output via the AND gates AND3 and AND5, respectively. When the mode selection signal MODE is "1" And the outputs of the inverters IV1 and IV3 become low level, so that the clock signal CLK is outputted through the AND gates AND4 and AND6, respectively.

When the mode selection signal MODE is "0 ", the selection signal output unit 93 outputs the inverted output of the D flip-flop 90 as shown in FIG. 10 (f) ) Is inverted and outputted through the AND gate AND7 and the inverter IV7 and when the mode selection signal MODE is "1", the high level output of the AND gate AND8 is inverted by the inverter IV7 A low-level selection signal S is output.

Therefore, in the mode control unit 85, when the mode selection signal MODE applied from the first latch circuit 81 in FIG. 8 is "1", that is, in the single-mode or two-phase single- Level selection signal S while outputting the first and second clock signals CLK1 and CLK2 of the same type as in FIG. 10 (a), and when the mode selection signal MODE is "0" In the case of the 1-2 phase excitation method, the first and second clock signals CLK1 and CLK2 shown in FIGS. 10 (d) and 10 (e) are outputted and, as the selection signal S, A clock signal in which a high level and a low level are alternately generated is output.

In FIG. 8, reference numeral 86 denotes data of four bits each applied to the first input terminal A and the second input terminal B according to the selection signal S applied from the mode control unit 85, Which is input to the first input terminal A when the low level selection signal is applied from the mode control unit 85, to the motor driver 3 of the third stage, Bit data from the second shift register 84 that is input to the second input terminal B when a high-level selection signal is applied from the mode control unit 85, And outputs the data as pattern data.

Next, the operation of the apparatus having the above configuration will be described.

4, in the case where the microprocessor 41 drives the step motor SM in the one-phase excitation mode, the microcomputer 41 sets the first control signal CSO to the active low state Quot; 101x xxxx "through the data bus in the active low state of the second control signal and outputs" 1000 xxxx "in the active low state of the second control signal, And the clock signal CLK to drive the pattern data generator 42.

At this time, in the pattern data generator 42, "101x xxxx" is latched in the first latch circuit 81 at the low level of the first control signal CSO and at the low level of the second control signal CS1 "1000 xxxx" is latched in the second latch circuit 82.

Therefore, at this time, the first shift register 83 is supplied with the load signal ( &Quot; 1000 "is loaded in the active low state of the shift direction setting data, and" 10 "is inputted as the shift direction setting data.

In addition, in the mode control unit 85, the mode control unit 85 outputs a low-level selection signal to the selector 86 as the mode selection signal of "10" is input from the first latch circuit 81, The output of the first shift register 83 is set to the selectable state and the first and second clock signals CLK1 and CLK2 are output in accordance with the input clock signal CLK.

Therefore, in the above state, the first shift register 83 performs the shift operation in response to the clock signal CLK1 applied from the mode control unit 85, and outputs the shifted data through the output stages QA to QD The data output from the first shift register 83 through the selector 86 is input to the left shift data input terminal SL of the clock signal CLK and the output QD of the most significant bit is input to the left shift data input terminal SL again. As shown in Table 1 above, data "1" As pattern data that is sequentially shifted to the left side.

When the microprocessor 41 drives the step motor SM in the one-phase reverse rotation mode, the values of bit 0 and bit 1 of the data latched in the first latch circuit 81 are set to " 1 "and other data becomes the same as in the above-described one-phase forward rotation mode.

Therefore, in this case, the shift direction setting data applied to the first shift register 83 is changed so that the data shift direction of the first shift register 83 is performed from the output stage QD to the output stage QA side, The data output from the first shift register 83 through the selector 86 is input to the right shift data input terminal SR as data " 1 " The pattern data is sequentially shifted from the A side to the A side.

On the other hand, when the stepper motor SM is driven in the two-phase forward rotation mode, the microprocessor 41 outputs "101x xxxx" as the first data and "1100 xxxx" And supplies it to the data generating device 42.

In this case, the mode control unit 85 and the first shift register 83 operate in the same operation mode as the above-described one-phase forward rotation mode. At this time, the first shift register 83 outputs data of "1100" The data output from the first shift register 83 through the selector 86 is in the form of pattern data as shown in Table 3. [

When the step motor SM is driven in the two-phase reverse rotation mode, the microprocessor 41 supplies "011x xxxx" as the first data and "1100 xxxx" as the second data.

Therefore, in this case, the same data as in the above-described two-phase forward rotation mode is loaded into the first shift register 83 and the data shift direction thereof is set to be opposite to the forward rotation mode so that the data from the first shift register 83 to the selector 86 ) Is in the form of pattern data as shown in Table 4. < tb > < TABLE >

The second shift register 84 also performs the shift operation in accordance with the clock signal CLK2 applied from the mode control unit 85 in the one-phase or two-phase driving method described above. However, the second shift register 85 Is not selected for the selector 86, so that the operation of the stepper motor SM is not affected.

Next, when the stepper motor SM is driven in the forward rotation mode of 1-2 phase, the microprocessor 41 outputs "100x xxxx" as the first data and "1000 1100" as the second data as shown in Table 5 .

Therefore, in this case, the second data latched in the second latch circuit 82 is applied to the load signal Is input to the first shift register 83 and the second shift register 84 at the time of input of the shift register 83 and 84 and the first and second shift registers 83 and 84 are set to the shift direction setting Quot; 10 "as data. Therefore, the loaded data is shifted from the output stage QA to the output stage QD side and the shifted data is output in parallel through the output stages QA to QD.

Since the mode control unit 85 is applied with "0" as the mode selection data, the clock signal CLK applied from the microprocessor 41 as shown in FIGS. 10 (d) and 10 Generates the second clock signals CLK1 and CLK2 and supplies them to the first and second shift registers 83 and 84 and outputs the selection signal S as shown in FIG.

Therefore, as shown in the following Table 6, the one-phase normal rotation pattern data output from the first shift register 83 and the two-phase normal rotation pattern data output from the second shift register 84 are input to the selector The step motor SM is driven in the positive rotation mode of the 1-2 phase.

When the stepper motor SM is driven in the reverse rotation mode of 1-2 phases, as shown in Table 5, the microprocessor 41 supplies 010x xxxx as the first data and 1000 1100 as the second data.

Therefore, in this case, only the rotational phase direction setting data supplied to the first and second shift registers 83 and 84 are different from the above-mentioned 1-2 phase normal rotational mode and therefore, The mode control is executed in the 1-2 phase forward rotation mode and the mode.

In the first and second shift registers 83 and 84, the same data as in the 1-2-phase forward rotation mode is loaded. In this case, the first and second shift registers 83 and 84 1, the shifted data is outputted in parallel through the output stages QA to QD while shifting the data from the output stage QD to the output stage QA side.

Table 7 below shows pattern data output from the selector 86 in the 1-2 phase reverse rotation mode.

When the drive of the step motor SM is to be stopped in each of the above operation mode states, the microprocessor 41 is executed by blocking the clock signal CLK supplied to the pattern data generator 42. [

Therefore, in the above-described embodiment, the microprocessor 41 does not generate and output pattern data all the time according to the driving method of the step motor SM, but generates pattern data based on predetermined data only according to the driving method Since the apparatus 42 is programmed, the burden on the microprocessor 41 due to the driving of the stepper motor SM can be greatly reduced.

On the other hand, in the above embodiment, the drive amount or drive time of the stepping motor SM depends on the output of the clock signal CLK from the microprocessor 41. That is, when the microprocessor 41 drives the stepper motor SM by a predetermined amount, the microprocessor 41 counts the number of pulses of the clock signal CLK supplied to the pattern data generator 42 The driving amount of the step motor SM is controlled by a method of interrupting the output of the clock signal CLK when the number of counted pulses becomes a predetermined value.

Therefore, in the above embodiment, the driving amount of the stepping motor SM must be continuously checked while counting the number of output pulses of the clock signal CLK of the microprocessor 41. This is because the software load of the microprocessor 41 .

FIG. 11 is a block diagram showing a pattern data generating apparatus for driving a step motor according to another embodiment of the present invention. In this embodiment, the pattern data generating apparatus includes a step motor And when the step motor is properly driven, the microprocessor outputs the interrupt signal. In FIG. 11, the same reference numerals are assigned to the same components as those in FIG. 4, and a detailed description thereof will be omitted.

11, reference numeral 101 denotes a microprocessor for controlling the driving of the stepping motor SM, and 102 generates pattern data for driving the stepping motor SM under the control of the microprocessor 101 And outputs the pattern data.

12, the microprocessor 101 outputs the first to third data in the active low state of the first to third control signals CSO to CS2, The data generating apparatus 102 is programmed.

At this time, the first and second data are set to the drive mode data for selecting the rotational direction and the excitation mode of the step motor SM in the same manner as described in FIG. 4, The drive amount data for setting the drive amount is set.

Next, the microprocessor 101, as in the embodiment of FIG. 4, And the clock signal CLK to drive the pattern data generator 102.

Then, from the pattern data generator 102, an interrupt signal ( The operation of the step motor is stopped by stopping the output of the clock signal CLK.

FIG. 13 is a diagram showing the configuration of the above-described pattern data generator 102. In FIG. 13, a counter 110 is additionally provided for the configuration shown in FIG.

The counter 110 sets the third data DATA, that is, the drive amount data of the stepper motor SM from the microprocessor 101 in the low level state of the third control signal CS2, and then outputs the clock signal CLK, The corresponding data value is down-counted. When the count value becomes "0 ", the low-level interrupt signal ( ).

Therefore, in the above embodiment, when the microprocessor 101 programs the pattern data generator 102, after inputting another data value to the drive amount of the stepper motor SM, the pattern data generator 102 The output interrupt signal ( The output of the clock signal CLK is stopped, so that the burden on the software of the microprocessor 101 is further reduced.

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the technical spirit of the present invention.

For example, in the embodiment shown in FIGS. 4 and 8, the microprocessor 41 is configured to set the second data to an appropriate value according to the excitation method of the stepping motor SM, but in this case, 1000 " is constantly supplied to the first shift register 83 and the second shift register 84 by constantly supplying "1000 1100" The output of the first shift register 81 is selected by the shift register S and the output of the second shift register 84 is selected in the case of the two-phase excitation method. In the case of the 1-2- The same result can be obtained even if the mode control unit 85 is configured so that the first and second shift registers 83 and 84 and the selector 86 are operated alternately.

As described above, according to the present invention, it is possible to realize a pattern data generator for stepping motor drive that can greatly reduce the software burden of the microprocessor in driving the stepper motor.

Claims (3)

First latch means for latching data for setting the line direction and excitation mode of the step motor, first latch means for latching the first reference data corresponding to the one-phase excitation mode of the step motor and the second reference data corresponding to the two- A second latch means for storing the first or second reference data output from the second latch means in accordance with a load signal and for connecting the least significant bit output thereof to the first direction shift data input stage, First and second shifts, which are coupled to a second direction shift data input and output the shifted data while shifting the loaded data based on rotation direction setting data output from the first latch means each time a clock signal is input, Selection means for selectively outputting the outputs of the first and second shift registers in accordance with a register, first and second level selection signals, A counter means for counting the clock signal and outputting an interrupt signal of a predetermined level when the count value is equal to the drive amount data, And a mode control means for selectively supplying a clock signal to the first or second shift register based on the excitation type data output from the first or second shift register and outputting a first or second level selection signal to the selection means And outputs the pattern data to the step motor. 2. The step motor driving pattern data generator according to claim 1, wherein when the step motor is operated in a single-phase or two-phase single mode, the reference data is loaded in the first shift register in accordance with the mode. 2. The shift register according to claim 1, wherein the reference data for driving the step motor in the 1-phase mode is loaded in the first shift register, and the reference data for driving the step motor in the 2-phase mode is loaded in the second shift register Wherein the step motor driving pattern data generating device comprises: