KR100219060B1 - Mask rom having word line inactivated when sense amplifier is disabled - Google Patents

Abstract

According to the present invention, in a mask ROM, a word line control of a sense amplifier for reducing power consumption and preventing malfunction of a sense amplifier by turning off a word line after a predetermined time has elapsed after data of a selected cell is sensed. It is about a circuit.

To this end, the present invention comprises a sense enable delay signal generator and a word line control signal generator, which makes the word line control signal WL-CON high level at the time when the address transition detection signal ATD is generated. The word line control signal WL-CON is low level when the sense enable delay signal SEDD is generated when the sense enable signal SE of the sense amplifier is turned off. So that the word line is in the disabled state.

Description

Mask ROM with Word Line Disabled When Sense Amplifier Is Disabled

1 is a block diagram of a mask ROM having a general NAND string.

2 is a detailed block diagram of a typical cross coupled sense amplifier.

3 is a waveform diagram of each control signal in a conventional mask ROM.

4 is a waveform diagram of each control signal in the mask ROM according to the present invention.

5 is a partial block diagram of a mask rom according to the present invention.

6 is a detailed circuit diagram of the low predecoder of FIG.

7 is a word line control signal generation circuit diagram according to the present invention.

* Explanation of symbols for the main parts of the drawings

50: sense enable delay signal generator 60: word line control signal generator

The present invention relates to a mask ROM, and more particularly, to a mask ROM in which a word line is deactivated at a time when a sense amplifier is disabled in order to reduce power consumption and stabilize the operation of the device.

FIG. 1 is a block diagram of a mask ROM having a general NAND string, FIG. 2 is a detailed block diagram of a general cross coupled sense amplifier, and FIG. 3 is a waveform diagram of each control signal of a conventional mask ROM.

A mask ROM having a general NAND string is composed of a memory cell array unit 1, a Y-decoder 2, and a sense amplifier 3 as shown in FIG. 1 for reading data stored in a cell. The memory cell array unit 1 includes a dummy cell string 11 consisting of 32 NAND strings and 16 NAND strings having a predetermined voltage, and a bit cell string l2 that can be selectively read according to the type of cell. .

The operation of a general mask ROM having such a configuration will be described with reference to FIGS. 1, 2, and 3 as follows.

In general, the sense amplifier detects the voltage difference between a dummy line and a bit line to read data stored in a cell. In order to operate the sense amplifier 3, a reference voltage is required, and the data value of the cell is read at a high level or a low level based on the reference voltage. For this purpose, the dummy line is always turned on so that a constant current flows, so that the dummy line has a constant voltage and is used as an input of the sense amplifier 3, and the bit line has a low level in the word line of the selected cell and the remaining word lines It has a high level (low active).

That is, in FIG. 1, the voltage passing through the Y-decoder 2 from the 32 NAND string cell 11 of the memory cell array unit 1 passes through the n-channel MOSFET N88 of the sense amplifier 3. It is input to the input terminal of 32) and this voltage is used as the reference voltage. In addition, in the 16 NAND string cell 12 of the memory cell array unit 1, one of the string line SL0 and the string line SL1 becomes a high level and the other becomes a low level to select one of the two strings, and the word line WL0. One word line selected from WL15 becomes a low level and an unselected word line becomes a high level, so that a path to the ground terminal Vss is turned on / off according to the characteristics of the cell.

Meanwhile, as shown in FIG. 1, some of the MOSFETs N57, N58, N65, N72, N73, which constitute the dummy cell string 11 and the bit cell string 12 of the memory cell array unit 1, N83) is a depletion transistor, and the rest are enhancement transistors. When the selected cell is a depletion transistor, the bit line has a lower voltage than the dummy line, so the sensing output SAOUT of the sense amplifier is at a low level. When the selected cell is an enhancement transistor, the dummy line is dummy. Having a higher voltage than the line, the sense output of the sense amplifier is at a high level.

Referring to FIG. 3, the word line driving of the conventional mask ROM is described in detail. An address transition signal ATD is generated by detecting the transition of the address signal ADD, and the string line SL and the word line WL are responded to in response to the address transition signal ATD. It is activated or deactivated. The string line is activated as a high level signal, and the word line is activated as a low level signal. However, referring to FIG. 3, conventionally, the bit line signal is input to the sense amplifier by the selected cell and continues to be activated even after the driving of the sense amplifier of the sense amplifier is completed. There is a problem that power is consumed through the selected cell until the conversion time.

The present invention to solve the above problems in the mask ROM. It is an object of the present invention to provide a mask ROM for turning off the word line after a predetermined time has elapsed since the data of the selected cell is detected to reduce power consumption and prevent malfunction of the cell.

In order to achieve the above object, the present invention provides a word for generating a word line control signal for deactivating a selected word line at a time when a sense amplifier is disabled in response to a sense enable signal and an address transition detection signal in a mask ROM. Line control signal generating means; A low predecoder driving in response to a plurality of address signals and the word line control signal; And a low decoder for activating or deactivating Word Raan in response to the output of the low predecoder.

Preferably, the low predecoder includes a NAND gate that receives and outputs the plurality of address signals and the word line control signal, and deactivates the selected word line when the word line control signal has a low level. do.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a waveform diagram of each control signal in the mask ROM according to the present invention, FIG. 5 is a partial block diagram of the mask ROM according to the present invention, FIG. 6 is a detailed circuit diagram of the low predecoder of FIG. Is a word line control signal generation circuit diagram according to the present invention.

First, referring to FIGS. 5 and 6, the mask ROM according to the present invention inputs the word line control signal WL-CON to the low predecoder 72 which receives an address from the low address buffer 71, thereby providing a low decoder ( The word line signal, which is an output of 73, is controlled, whereby the word line selected by the word line control signal WL-CON is inactivated in the word line of the mask ROM according to the present invention (see Fig. 4). The word line control signal WL-CON is generated under the control of the sense enable delay signal SEDD generated by delaying the enable signal SE and the address transition detection signal ATD.

Referring to FIG. 7, the word line control signal generator according to the present invention includes a sense enable delay signal generator 50 and a word line control signal generator 60.

The sense enable delay signal generating unit 50 generates a sense enable delay signal SEDD when the sense enable signal SE is turned off by inputting the enable signal SE to the sense in controlling the operation of the sense amplifier. A delay unit 51 for delaying the sense enable signal SE for controlling the operation of the sense amplifier, a negative gate 52 for negating and logically combining the output of the delay unit 51 and the sense enable signal SE; An inverter 53 for inverting the output of the NOA gate 52, an inverter 54 for inverting the sense enable signal SE, a NAND gate 55 for negative logic multiplying the outputs of the two inverters 53 and 54, And an inverter 56 which inverts the output of the NAND gate 55 and outputs a sense enable delay signal SEDD.

The word line control signal generator 60 receives an address transition detection signal (ATD) input from the outside and a sense enable delay signal SEDD further output from the sense enable delay signal generator 50. It becomes a high level when the address transition detection signal ATD is activated as an input and becomes a low level when the sense enable delay signal SEDD is activated to generate the word line control signal WL-CON for controlling the word line. By using the address transition detection signal (ATD: Address Transition Detection Signal) input from the outside as a single input, the sense enable output output from the NOA gate 61 and the sense enable delay signal generator 50 Noah gate 62 and negative gate 61 for negatively combining the delay signal SEDD and the output of the noah gate 61 and outputting them with the type force of the noah gate 61, and the noah gate 61. By inverting the output consists of beodeo (63) for outputting a word line control signal (WL-CON).

The operation of the word line control signal generator according to the present invention configured as described above will be described.

The word line control signal generator according to the present invention shown in FIG. 7 is for controlling the word line WL and the string line SL which are the gate lines of the transistors of the bit string cells 12 of the mask ROM shown in FIG. will be.

The sense enable delay signal SE is input to the sense enable delay signal generator 50 and is generated when the sense enable signal SE is deactivated as shown in FIG. 4 to become a high level. Output to SEDD. That is, the sense enable signal SE is negatively logically inverted through the inverter 53 after being delayed by the delay unit 50 and historyed at the noar gate 52, and then inverted through the inverter 53. Inverted through the sense enable signal SE and the NAND gate 55 inverted through the inverted through the inverter 56 is outputted as the sense enable delay signal SEDD.

In addition, the address transition detection signal ATD and the sense enable delay signal SEDD are input to the word line control signal generation unit 60 and become high at the time when the address transition detection signal ATD comes in as shown in FIG. When the enable delay signal SEDD is turned on, the word line control signal WL is set to the low level so that the word line and the string line are in the active state at the high level, and the word line and the string line are in the inactive state at the low level. Generate -CON In other words, the sense enable delay signal SEDD is negated and logically mixed with the output of the noble gate 61 at the noble gate 62, and negatively sequentially mixed with the address transition detection signal ATD at the noble gate 61 and then inverted by the inverter 63. Outputted by the line control signal WL-CON.

The word line control signal WL-CON generated as described above is input to the low predecoder to control the word line. The input low address is buffered in the low address buffer 71 and then precoded in the low precoder 72. At this time, the low precoder 72 is enabled and disabled by the word line control signal WL-CON. That is, the low precoder 72 has an inverter for inverting the outputs of the NAND gate 81 and the NAND gate 81 to which a plurality of address signals and word line control signals WL-CON are input as shown in FIG. 82, and an inverter 84 that inverts the output of the inverter 82. When the word line J signal WL-CON is at a high level, the output of the low precoder 72 is made high by the address signal output. Since the low-decoder 73 may activate the string line SL and the word line WL, and the word line control signal WL-CON is at a low level, the output of the low precoder 72 may have a low value. Therefore, the low decoder 73 is disabled so that the string line SL and the word line WL are inactivated.

Therefore, as shown in FIG. 4, when the address transition detection signal ATD is generated, the word line control signal WL-CON is set to high level so that the word line is in the enabled state, and the sense enable signal SE of the sense amplifier is When the sense enable delay signal SEDD generated at the time of turning off, the word line control signal WL-CON is made low so that the word line is in an inactive state.

As a result, the mask ROM of the present invention stabilizes the operation of the cell by putting all of the word lines in the -activated state after the sensing operation of the sense amplifier and then operating only the selected word lines for the cells selected after the address conversion. In addition, power consumption is reduced by preventing leakage current caused by unnecessary word line activation.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (3)

11. A mask ROM comprising: word line control signal generation means for generating a word line control signal for deactivating a selected word line at a time when a sense amplifier is disabled in response to a sense enable signal and an address transition detection signal; A low predecoder driving in response to a plurality of address signals and the word line control signal; And a low decoder to enable or disable a word line in response to an output of the low predecoder. 2. The method of claim 1, wherein the low predecoder comprises a NAND gate that receives and outputs the plurality of address signals and the word line control signal to deactivate the selected word line when the word line control signal has a low level. Mask rom, characterized in that. 2. The apparatus of claim 1, wherein the word line control signal generating means comprises: a delay unit for delaying a sense enable signal; A first noacetate that negates and logically outputs the delay unit and the sense enable signal; A first inverter for inverting output of the first NOR gate; A second inverter for inverting the sense enable signal; A NAND gate that negatively multiplies the outputs of the first and second inverters; A third inverter for inverting the output of the NAND gate; A second NOR gate configured to perform negative logic sum on the address transition detection signal as one input; A third NOR gate outputting the output signal of the third inverter and the output of the second NOR gate by a negative force and outputting the type force of the second NOR gate; And a fourth inverter outputting the word line control signal by inverting the output of the second NOR gate.