KR100215904B1 - Manufacturing method of silicon sensor - Google Patents
Manufacturing method of silicon sensor Download PDFInfo
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- KR100215904B1 KR100215904B1 KR1019950004697A KR19950004697A KR100215904B1 KR 100215904 B1 KR100215904 B1 KR 100215904B1 KR 1019950004697 A KR1019950004697 A KR 1019950004697A KR 19950004697 A KR19950004697 A KR 19950004697A KR 100215904 B1 KR100215904 B1 KR 100215904B1
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- diffusion region
- epitaxial layer
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 31
- 239000010703 silicon Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 13
- 229910021426 porous silicon Inorganic materials 0.000 claims abstract description 13
- 238000000206 photolithography Methods 0.000 claims abstract description 10
- 238000006243 chemical reaction Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims description 8
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 6
- 239000007864 aqueous solution Substances 0.000 claims description 3
- 230000007246 mechanism Effects 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N hydrofluoric acid Substances F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 7
- 230000001133 acceleration Effects 0.000 description 5
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000003487 electrochemical reaction Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
- G01L9/0041—Transmitting or indicating the displacement of flexible diaphragms
- G01L9/0042—Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Analytical Chemistry (AREA)
- Ceramic Engineering (AREA)
- Pressure Sensors (AREA)
Abstract
본 발명은 실리콘을 이용한 각종센서 제조에 관한 것으로, 특히 HF 양극반응을 통하여 다이어프램 및 각종기구물의 휨에 대한 지지대를 갖도록 함으로써 소자의 파손을 마고 면적을 줄이는데 적당하도록 한 실리콘센서 제조방법에 관한 것이다.The present invention relates to the manufacture of various sensors using silicon, and more particularly, to a silicon sensor manufacturing method that is suitable for reducing the area of damage to the device by having a support for the deflection of the diaphragm and various mechanisms through the HF anodic reaction.
상기와 같은 본 발명은 불순물 확산영역이 형성된 기판상에 n형 에피택셜층과 절연막을 차례로 형성하는 공정, 상기 절연막을 사진식각 방법으로 불순물 확산영역상의 일부가 제거되도록 패 터닝하고, 이를 마스크로 이용하여 n형 에피택셜층을 선택적으로 식각하는 공정, 상기 선택적으로 식각된 n형 에피택셜층에 의해 노출된 불순물 확산영역을 HF 양극 반응하여 다공질 실리콘으로 형성하는 공정, 상기 다공질 실리콘을 식각하여 하부의 기판이 지지대 역할을 하는 다이어프램 그리고 기판과 다이어프램 사이의 캐비티를 형성하는공정, 상기 다이어프램 모서리 부분에 압 저항을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.In the present invention as described above, a process of sequentially forming an n-type epitaxial layer and an insulating film on a substrate on which an impurity diffusion region is formed, and patterning the insulating film to remove a part of the impurity diffusion region by a photolithography method, and use the mask as a mask. Selectively etching the n-type epitaxial layer, forming a porous silicon by HF anodic reaction of the impurity diffusion region exposed by the selectively etched n-type epitaxial layer, and etching the porous silicon And a step of forming a cavity between the substrate and the diaphragm serving as a support, and a step of forming a piezoresistor at the edge portion of the diaphragm.
Description
제 1 도는 일반적인 실리콘센서를 이용한 기구의 단면도1 is a cross-sectional view of a device using a general silicon sensor
제 2 도는 종래의 실리콘센서 레이아웃도2 is a layout diagram of a conventional silicon sensor
제 3 도는 제 2 도의 A-A'선상의 종래 실리콘센서 제조방법을 도시한 공정단면도3 is a process sectional view showing a conventional silicon sensor manufacturing method along the line AA ′ of FIG. 2.
제 4 도는 제 2 도의 B-B'선상의 종래 실리콘센서 제조방법을 도시한 공정단면도4 is a process cross-sectional view showing a conventional silicon sensor manufacturing method along the line B-B 'of FIG.
제 5 도는 본 발명의 실리콘센서 레이아웃도5 is a layout view of a silicon sensor of the present invention.
제 6 도는 제 5 도의 A-A'선상의 본 발명 실리콘센서 제조방법을 도시한 공정단면도6 is a cross-sectional view showing a method of manufacturing the silicon sensor of the present invention along the line AA ′ of FIG. 5.
제 7 도는 제 5 도의 B-B'선상의 본 발명 실리콘센서 제조방법을 도시한 공정단면도7 is a process cross-sectional view showing a method of manufacturing the silicon sensor of the present invention along the line B-B 'of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 기판 22 : 불순물 확산영역21 substrate 22 impurity diffusion region
22a : 다공질 실리콘 23 : n형 에피텍셜층22a: porous silicon 23: n-type epitaxial layer
23a : 다이어프램 24 : 절연막23a: diaphragm 24: insulating film
25 : 다공질 실리콘의 식각된 영역 26 : 압저항25 etched region of porous silicon 26 piezoresistive
본 발명은 실리콘(Silicon : Si)을 이용한 각종 센서제조에 관한 것으로, 특히 HF 양극반응을 통하여 다이어프램(Diaphragm) 및 각종기구물 등의 휨에 대한 지지대를 갖도록 함으로써 소자의 파손을 막고, 면적을 줄이는데 적당하도록 한 실리콘센서(Silicon Senser) 제조방법에 관한 것이다.The present invention relates to the manufacture of various sensors using silicon (Si), and in particular, by having a support for bending of diaphragms (Diaphragm) and various apparatuses through HF anodic reaction, it is suitable for preventing damage to the device and reducing the area. The present invention relates to a method for manufacturing a silicon sensor.
일반적으로, 실리콘을 이용한 가속도, 압력 또는 진동센서 제조시 실리콘 뒷면을 식각하여 다이어프램 구조를 형성한 다음, 다이어프램의 모서리 부분에 압저항을 형성한다.In general, when manufacturing an acceleration, pressure or vibration sensor using silicon to form a diaphragm structure by etching the back side of the silicon, and then forming a piezoresistor on the corner portion of the diaphragm.
따라서 가속도, 압력, 진동 등에 대한 다이어프램의 응력이 저항값을 변화시키게 되고, 이 저항값 변화를 계산하여 실제 가해진 가속도, 압력, 진동 등을 측정할 수 있다.Therefore, the stress of the diaphragm with respect to acceleration, pressure, vibration, etc. changes the resistance value, and the change in the resistance value can be calculated to measure the actual applied acceleration, pressure, vibration, and the like.
제 1 도는 일반적인 실리콘센서를 이용한 기구단면도를 나타낸 것이다.1 is a cross-sectional view of a device using a general silicon sensor.
이하, 종래의 레이아웃도 및 제조방법은 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, the conventional layout and manufacturing method will be described with reference to the accompanying drawings.
제 2 도는 종래의 실리콘센서 레이아웃도, 제 3 도는 제 2 도의 A-A' 선상, 제 4 도는 제 2 도의 B-B'선상의 종래 실리콘센서 제조방법을 도시한 단면도를 나타낸 것이다.FIG. 2 is a layout diagram of a conventional silicon sensor, and FIG. 3 is a cross-sectional view showing a conventional silicon sensor manufacturing method on the line A-A 'of FIG. 2 and on the line B-B' of FIG.
먼저 제 3 도 (a) 및 제 4 도 (a)에서와 같이 P형 반도체 기판(1)상에 n형실리콘(n-type silicon)을 에피텍시 성장시켜(epitaxy) 에피택셜층(2)을 형성하고, 상기 기판 뒷면의 두꺼운 실리콘을 소정의 두께로 폴리싱(polishing)하여 깍아낸다.First, the epitaxial layer 2 is epitaxially grown by n-type silicon on the P-type semiconductor substrate 1 as shown in FIGS. 3A and 4A. The thick silicon on the back side of the substrate is polished to a predetermined thickness and scraped off.
이어서, 에피텍셜 성장된 기판상면과 폴리싱된 기판 뒷면에 산화공정(Oxidation)을 실시하여 산화막(3)을 형성한다.Subsequently, an oxidation process is performed on the epitaxially grown substrate upper surface and the polished substrate rear surface to form an oxide film 3.
그 다음 제 3 도 (b) 및 제 4 도 (b)에서와 같이 상기 기판 뒷면에 형성된 산화막(3)상에 감광막(P/R)을 도포하여 사진식각(Photolithography) 방법으로 소정의 식각부분을 정의(define)하고 제 3 도 (c) 및 제 4 도 (c)에서와 같이 노출된 산화막을 습식식각 한 후 기판을 식각한다.Then, as shown in FIGS. 3B and 4B, a photoresist film P / R is coated on the oxide film 3 formed on the back side of the substrate, and a predetermined etching portion is removed by a photolithography method. The substrate is etched after defining and wet etching the exposed oxide film as in FIGS. 3 (c) and 4 (c).
이때 기판의 식각방법은 P형 반도체 기판의 두꺼운 실리콘을 식각해야 하므로 KOH 수용액을 사용하여 습식식각하면 등방성 식각을 하게 된다.At this time, the etching method of the substrate is to etch the thick silicon of the P-type semiconductor substrate, so that the wet etching using a KOH aqueous solution is isotropic etching.
그래서 전기화학(electrochemical)반응을 이용하여 식각하면 P형 반도체기판(1)층만 식각해내고 n형 에피실리콘(n-type epitaxial Silicon : 이하 n-epi라 지칭함)층(2)은 식각되지 않은 자동정지 반응이 일어난다.Therefore, when etching using an electrochemical reaction, only the P-type semiconductor substrate (1) layer is etched and the n-type epitaxial silicon (n-epi) layer (2) is not etched. A stop reaction occurs.
이어서 식각되지 않은 P형 반도체 기판(1)상에 있는 n-epi 영역에 사진식각 방법으로 캐비티(cavity)영역(4)을 정의(define)하여 n-epi층을 식각한다.Subsequently, the cavity region 4 is defined in the n-epi region on the non-etched P-type semiconductor substrate 1 by photolithography to etch the n-epi layer.
이때 캐비티(cavity)영역은 n-epi 다이어프램(2)이 좌우로 움직일 수 있도록 하는 빈공간이 되고, 상기 제 4 도 (d)에 도시된 바와 같이 n-epi 다이어프램(2)은 캐비티(cavity)(4) 사이에 놓여 있다.At this time, the cavity area is an empty space for the n-epi diaphragm 2 to move left and right, and as shown in FIG. 4 (d), the n-epi diaphragm 2 is a cavity (4) lies between.
여기서 제 3 도 (d)상에는 캐비티(cavity)영역이 도시되지 않는다.Here, the cavity area is not shown on FIG. 3 (d).
그 다음 제 3 도 (e)에서와 같이 n-epi 다이어프램 모서리(n-epi Diaphram Edge)부분에 압저항이 형성될 영역의 옥사이드를 디파인하여 사진식각 방법으로 식각한 다음, 상기 디파인된 옥사이드에 의해 노출된 n-epi 다이어프램 모서리 부분에 불순물(P)을 확산하여 압저항(5)영역을 형성한다.Next, as shown in FIG. 3 (e), the oxide of the region where piezoresistive resistance is to be formed at the n-epi diaphram edge is etched and etched by a photolithography method, followed by the fine oxide. Impurities P are diffused on the exposed n-epi diaphragm edge to form a piezoresistor 5 region.
이어서 제 3 도 (f)에서와 같이 상기 남아 있는 옥사이드를 모두 제거하고, 상기 압저항을 신호로 받아들이는 외부회로를 플레너(planar) 기술을 이용하여 만들면 가속도, 압력, 진동 등의 센서로서 동작할 수 있는 실리콘센서가 완성된다.Subsequently, as shown in FIG. 3 (f), when the remaining oxide is removed and an external circuit that receives the piezoresistor as a signal is made using a planar technique, it may operate as a sensor such as acceleration, pressure, and vibration. Silicon sensor can be completed.
이때 아주 큰 압력이 가해지면 제 3 도 (g)에서와 같이 다이어프램의 아랫쪽 휨에 대한 지지대가 없기 때문에 다이어프램 자체가 파괴되어 버리는 상태가 발생한다.At this time, when a very large pressure is applied, the diaphragm itself is destroyed because there is no support for the lower deflection of the diaphragm as shown in FIG. 3 (g).
상기와 같은 종래의 기술은 다음과 같은 문제점이 있었다.The prior art as described above has the following problems.
첫째, P형 반도체 기판의 뒷면 식가후 다시 앞면에서 사진식각 방법을 진행해야 하므로 뒷면과 앞면의 양면정렬(align)이 필요로 하며 이에 따른 정합오차가 크게 발생한다.First, after etching the back side of the P-type semiconductor substrate, the photolithography method must be performed from the front side, so that both sides of the back side and the front side need to be aligned, and a matching error occurs largely.
둘째, 상기와 같이 형성된 다이어프램은 상하방향으로 P형 반도체 기판의 두께만큼 떠 있는 구조가 되어 다이어프램의 아랫쪽 휨에 대한 지지대가 없는 상태가 되기 때문에 아주 큰 힘이 가해질 경우 다이어프램 자체가 파괴되어 버리는 상태가 발생한다.Second, the diaphragm formed as described above has a structure floating in the vertical direction by the thickness of the P-type semiconductor substrate, and thus there is no support for the lower bending of the diaphragm. Therefore, the diaphragm itself is destroyed when a very large force is applied. Occurs.
본 발명은 상기에 상술한 문제점을 해결하기 위해 안출된 것으로 HF 양극반응을 통하여 다이어프램 및 각종 기구물 등의 힘에 대한 지지대를 갖도록 함으로써 소자의 파손을 막고 면적을 줄이는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems described above, and has an object to prevent damage to the device and to reduce the area by having a support for the force of the diaphragm and various mechanisms through the HF anode reaction.
상기 목적을 달성하기 위한 본 발명의 실리콘 센서 제조 방법은 불순물 확산영역이 형성된 기판상에 n형 에피택셜층과 절연막을 차례로 형성하는 공정, 상기 절연막을 사진식각 방법으로 불순물 확산영역상의 일부가 제거되도록 패 터닝하고 이를 마스크로 이용하여 n형 에피택셜층을 선택적으로 식각하는공정, 상기 선택적으로 식각된 n형 에피택셜층에 의해 노출된 불순물 확산영역을 HF 양극 반응하여 다공질 실리콘으로 형성하는 공정, 상기 다공질 실리콘을 식각하여 하부의 기판이 지지대 역할을 하는 다이어프램 그리고 기판과 다이어프램 사이의 캐비티를 형성하는 공정, 상기 다이어프램 모서리 부분에 압저항을 형성하는 공정을 포함하여 이루어짐을 그 특징으로 한다.The silicon sensor manufacturing method of the present invention for achieving the above object is a step of sequentially forming an n-type epitaxial layer and an insulating film on the substrate on which the impurity diffusion region is formed, so that a part of the impurity diffusion region is removed by the photolithography method. Patterning and selectively etching an n-type epitaxial layer using the mask, forming a porous silicon by HF anodic reaction of an impurity diffusion region exposed by the selectively etched n-type epitaxial layer, and And forming a cavity between the substrate and the diaphragm by etching the porous silicon to form a cavity between the substrate and the diaphragm, and forming a piezoresistive resistor at the edge portion of the diaphragm.
이하, 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, with reference to the accompanying drawings in detail as follows.
제 5 도는 본 발명의 실리콘센서 레이아웃도이고, 제 6 도는 제 5 도의 A-A'선상, 제 7 도 B-B'선상의 실리콘센서 제조방법을 도시한 단면도를 나타낸 것이다.5 is a layout diagram of the silicon sensor of the present invention, and FIG. 6 is a cross-sectional view illustrating a method of manufacturing a silicon sensor on line A-A 'and FIG. 7B-B' on FIG.
먼저 제 6 도 (a) 및 제 7 도 (a)에서와 같이 n형 반도체 기판(21)내에 소자영역이 형성될 부분을 정의하여 불순물 n층(22)을 확산시킨 후 에피택셜 공정으로 상기 전면에 n형 에피택셜층(23)을 형성한다.First, as shown in FIGS. 6A and 7A, a portion in which an element region is to be formed in the n-type semiconductor substrate 21 is defined to diffuse the impurity n layer 22 and then the front surface is subjected to an epitaxial process. The n-type epitaxial layer 23 is formed in this.
이어서 제 6 도 (b) 및 제 7 도 (b)에서와 같이 상기 전면에 마스크층으로써 질화막(Si3N4)(24)을 증착하고, 상기 질화막(24)을 사진식각 방법을 통하여 캐비티(cavity)와 다이어프램 영역이 형성될 부분인불순물 n+확산층(22)을 노출시키기 위하여 먼저 질화막(24)을 포트리소그래피 공정으로 선택적으로 식각하여 패터닝한다.Subsequently, as illustrated in FIGS. 6B and 7B, a nitride layer (Si 3 N 4 ) 24 is deposited on the entire surface as a mask layer, and the nitride layer 24 is deposited using a photolithography method. The nitride film 24 is selectively etched and patterned by a photolithography process in order to expose the impurity n + diffusion layer 22, which is a portion where the cavity and the diaphragm region are to be formed.
이어서 상기 패터닝된 질화막(24)을 마스크로 이용하여 n형 에피택셜층(23)을 선택적으로 식각한다.Subsequently, the n-type epitaxial layer 23 is selectively etched using the patterned nitride layer 24 as a mask.
이때 불순물 n+확산층 상의 질화막과 n형 에피택셜층을 모두 식각하는 것이 아니라 불순물 n+확산층의 중간부분에 아일랜드 형태의 질화막과 n-epi 패턴(제 6 도(b)에는 도시되지 않음)을 남겨둔다.In this case (not shown in Figure 6 (b)) impurity n +, rather than etching all the nitride film and the n-type epitaxial layer on the diffusion impurity n + island form of a nitride film and the n-epi pattern in the middle portion of the diffused layer leaves a .
상기 남아 있는 n형 에피택셜층 패턴은 실리콘 다이어프램(23a)이 되는 부분이다.The remaining n-type epitaxial layer pattern is a portion of the silicon diaphragm 23a.
그 다음 제 6 도 (c) 및 제 7 도 (c)에서와 같이 불산(HF)용액속에서 상기기판을 양극반응(anodization)시켜 상기 불순물 n+확산층의 확산깊이 만큼의 다공질 실리콘(PSL : Porous Silion Layer)(22a)을 형성한다.Next, as shown in FIGS. 6 (c) and 7 (c), the substrate is anodized in a hydrofluoric acid (HF) solution, and porous silicon (PSL: Porous) is formed to have a diffusion depth of the impurity n + diffusion layer. Silion Layer (22a) is formed.
이때, 다공질 실리콘의 제조방법은 실리콘 기판내에 도핑된 불순물 n+확산층(22)을 고순도 HF 용액속에 넣고, 백금전극을 음극으로, 실리콘 기판을 양극으로 하여 전류를 흘리면 반응조건에 따라서 불순물 n+확산층 깊이만큼 수십에서 수백 Å 크기의 미세기공이 형성된다.At this time, in the method of manufacturing porous silicon, when the impurity n + diffusion layer 22 doped in the silicon substrate is placed in a high purity HF solution, and a platinum electrode is used as the cathode and the silicon substrate is used as an anode, the current is impurity n + diffusion layer depending on the reaction conditions. As many as tens to hundreds of microns of pores are formed.
이어서 상기와 같이 불순물 n+확산영역내 형성된 다공질 실리콘(22a)을 5% NaOH 수용액에 담그면 상기 다공질 실리콘만 식각되어 제 6 도 (d) 및 제 7 도 (d)에서와 같이 다이어프램(23a) 구조(제 7 도 (d)에는 도시되지 않음)가 형성된다.Subsequently, when the porous silicon 22a formed in the impurity n + diffusion region is immersed in a 5% NaOH aqueous solution as described above, only the porous silicon is etched to form a diaphragm 23a as shown in FIGS. 6 (d) and 7 (d). (Not shown in FIG. 7 (d)) is formed.
이때, 상기와 같이 형성된 다이어프램(23a) 구조는 상하방향의 휨에 대해서 불순물 n+층의 확산깊이 만큼의 변위만을 할 수 있으므로 외부의 압력에 대해 n형 기판층이 상하휨에 대한 지지대 역할을 해주게 되어 다이어프램 자체가 파괴되는 현상을 막을 수 있다.At this time, since the diaphragm 23a structure formed as described above can only displace as much as the depth of diffusion of the impurity n + layer with respect to the vertical warpage, the n-type substrate layer acts as a support for the vertical warpage against external pressure. This can prevent the diaphragm itself from being destroyed.
이어서 제 6 도 (e) 및 제 7 도 (e)에서와 같이 n-epi 다이어프램 모서리 부분에 압저항이 형성될 영역의 상기 남아 있는 질화막(24)을 디파인하여 사진식각 방법으로 식각한 다음, 상기 디파인된 질화막에 의해 노출된 n-epi 다이어프램(23a) 모서리 부분에 불순물(p)을 확산하여 압저항(26)영역을 형성한다.Subsequently, as shown in FIGS. 6E and 7E, the remaining nitride film 24 of the region where piezoresistance is to be formed at the corner of the n-epi diaphragm is deeply etched and etched by a photolithography method. An impurity p is diffused to the edge portion of the n-epi diaphragm 23a exposed by the fine nitride film to form a piezoresistive 26 region.
여기서 제 7 도 (e)상에는 압저항영역이 도시되지 않는다.Here, the piezoresistive region is not shown on FIG. 7 (e).
이어서 제 6 도 (f) 및 제 7 도 (f)에서와 같이 상기 남아 있는 질화막(24)을 모두 제거하고, 상기 압저항(26)을 신호로 받아들이는 외부회로를 플레너(planar) 기술을 이용하여 만들면 가속도, 압력, 진동 등의 센서로서 동작할 수 있는 실리콘센서가 완성된다.Next, as shown in FIGS. 6 (f) and 7 (f), all the remaining nitride film 24 is removed, and an external circuit that receives the piezoresistor 26 as a signal using a planar technique. In this way, the silicon sensor can be operated as a sensor such as acceleration, pressure and vibration.
이와 같이 본 발명은 다음과 같은 효과가 있다.As such, the present invention has the following effects.
첫째, 기판의 양면 어라인이 필요없게 되므로 그에 따른 정합오차를 개선할 수 있어서 소자를 집적화 할 수 있다.First, since the two-sided alignment of the substrate is not necessary, the matching error can be improved and the device can be integrated.
둘째, 외부의 큰 힘에 대해 아랫쪽의 지지대가 있고, 그폭(상하휨의 정도)은 불순물 n+층의 확산깊이에 따라 적절히 조절할 수 있는 구조가 되므로 다이어 프램의 손상을 막을 수 있다.Second, there is a lower support for the large external force, and its width (degree of vertical warpage) is a structure that can be properly adjusted according to the depth of diffusion of the impurity n + layer can prevent the diaphragm damage.
Claims (4)
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| KR1019950004697A KR100215904B1 (en) | 1995-03-08 | 1995-03-08 | Manufacturing method of silicon sensor |
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