KR100214840B1 - Method for forming polysilicon layer of semiconductor device - Google Patents
Method for forming polysilicon layer of semiconductor device Download PDFInfo
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- KR100214840B1 KR100214840B1 KR1019950054384A KR19950054384A KR100214840B1 KR 100214840 B1 KR100214840 B1 KR 100214840B1 KR 1019950054384 A KR1019950054384 A KR 1019950054384A KR 19950054384 A KR19950054384 A KR 19950054384A KR 100214840 B1 KR100214840 B1 KR 100214840B1
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- Prior art keywords
- polysilicon
- grain size
- semiconductor device
- temperature
- polysilicon film
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000002245 particle Substances 0.000 abstract description 7
- 230000008021 deposition Effects 0.000 abstract description 5
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 abstract description 4
- 229920006395 saturated elastomer Polymers 0.000 abstract description 3
- 229910001873 dinitrogen Inorganic materials 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 101100520660 Drosophila melanogaster Poc1 gene Proteins 0.000 abstract 1
- 101100520662 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) PBA1 gene Proteins 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
고집적 반도체 소자 제조 방법.Highly integrated semiconductor device manufacturing method.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
반도체 소자 제조 공정에 필수적으로 폴리실리콘막 형성 공정시, 종래에는 예를 들어 약 625℃ 부근의 온도에서 LPCVD 방식을 이용하여 0.3um 정도의 거의 균일한 그레인 사이즈를 갖는 폴리실리콘을 증착하는 공정을 이용해 왔는데, 이와 같이 약 625℃ 이상의 온도에서는 증착 속도가 비교적 빠르므로 파티클 발생 가능성이 높고, 또한 거의 균일한 그레인 사이즈를 가지므로 후속 공정인 옥시염화인(POC13) 도핑 공정시 하부 산화막과의 접촉면에서 인 이온이 포화상태로 되는 현상이 발생할 가능성이 많다는 등의 문제점이 있었음.In the process of forming a polysilicon film, which is essentially a semiconductor device manufacturing process, conventionally, a process of depositing polysilicon having a nearly uniform grain size of about 0.3 μm using an LPCVD method at a temperature around 625 ° C. Since the deposition rate is relatively fast at a temperature of about 625 ° C. or more, the particles are more likely to be generated and have a nearly uniform grain size. Therefore, the phosphorus oxychloride (POC1 3 ) doping process is performed at the contact surface with the lower oxide film. There were problems such as the possibility of occurrence of phosphorus ion becoming saturated.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
비교적 낮은 온도에서 비교적 느린 증착 속도로 비교적 작은 그레인 사이즈를 가진 폴리실리콘을 증착한 다음, 고온의 질소 가스 분위기에서 표면을 열처리 하므로써, 파티클 발생을 억제하고 저항 조절이 용이한 폴리실리콘막을 형성하는 방법을 제공하고자 함.By depositing polysilicon having a relatively small grain size at a relatively low deposition rate at a relatively low temperature, and then heat-treating the surface in a high temperature nitrogen gas atmosphere, it is possible to form a polysilicon film that suppresses particle generation and easily adjusts resistance. To provide.
4. 발명의 중요한 용도4. Important uses of the invention
고집적 반도체 소자, 특히 DRAM 제조에 이용됨.Used in manufacturing highly integrated semiconductor devices, especially DRAM.
Description
제1a도 내지 1b도는 본 발명의 폴리실리콘막 형성 방법에 따른 제조 공정도.1a to 1b is a manufacturing process chart according to the polysilicon film forming method of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 산화막1 semiconductor substrate 2 oxide film
3 : 폴리실리콘막3: polysilicon film
본 발명은 일반적으로 반도체 소자 제조 방법에 관한 것으로서, 특히 파티클 발생을 억제하고 저항 조절이 용이한 폴리실리콘막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a polysilicon film that suppresses particle generation and easily adjusts resistance.
반도체 소자 제조 공정에는 필수적으로 폴리실리콘막 형성 공정이 수반되게 되는데, 종래에는 예를 들어 약 625℃ 부근의 온도에서 저압 화학 기상 증착법(LPCVD)을 이용하여 약 0.3um 정도의 거의 균일한 그레인 사이즈를 갖는 폴리실리콘을 증착하는 공정을 이용해 왔는데, 이와 같이 약 625℃ 이상의 온도에서는 증착 속도가 비교적 빠르므로 파티클 발생 가능성이 높고, 또한 거의 균일한 그레인 사이즈를 가지므로 후속 공정인 옥시염화인(POCl3) 도핑 공정시 하부 산화막과의 접촉면에서 인 이온이 포화상태로 되는 현상이 발생할 가능성이 많다는 등의 문제점이 있었다.The semiconductor device manufacturing process is essentially accompanied by a polysilicon film forming process, which is conventionally, for example, by using a low pressure chemical vapor deposition (LPCVD) at a temperature of about 625 ℃ almost uniform grain size of about 0.3um Since the deposition process of polysilicon has been used, since the deposition rate is relatively fast at a temperature of about 625 ° C. or higher, there is a high possibility of particle generation, and since it has a nearly uniform grain size, phosphorus oxychloride (POCl 3 ), which is a subsequent process, is used. In the doping process, there was a problem in that a phenomenon in which phosphorus ions become saturated at the contact surface with the lower oxide film is more likely to occur.
따라서 전술한 문제점을 해결하기 위해 안출된 본 발명은 비교적 낮은 온도에서 비교적 느린 증착 속도로 비교적 작은 그레인 사이즈를 가진 폴리실리콘을 증착한 다음, 고온의 질소 가스 분위기에서 표면을 열처리 하므로써, 파티클 발생을 억제하고 저항 조절이 용이한 폴리실리콘막을 형성하는 방법을 제공하는 것을 목적으로 한다.Therefore, the present invention devised to solve the above problems is to deposit polysilicon having a relatively small grain size at a relatively slow deposition rate at a relatively low temperature, and then suppress particle generation by heat-treating the surface in a high temperature nitrogen gas atmosphere. And it is an object to provide a method of forming a polysilicon film easy to control the resistance.
본 발명에 따른 반도체 소자의 폴리실리콘막 형성 방법은, 반도체 기판상에 산화막이 형성된 구조상에 저압 화학 기상 증착법으로 소정의 온도에서 폴리실리콘을 증착하는 단계와, 상기 폴리실리콘 표면 부위에서의 그레인 사이즈와 상기 산화막과의 접촉부위에서의 그레인 사이즈가 다르게 형성되도록 소정의 온도에서 상기 폴리실리막을 열처리한 다음, 도핑을 실시하는 단계를 포함하는 것을 특징으로 한다.The polysilicon film forming method of a semiconductor device according to the present invention comprises the steps of depositing polysilicon at a predetermined temperature by a low pressure chemical vapor deposition method on a structure in which an oxide film is formed on a semiconductor substrate, and the grain size at the surface portion of the polysilicon And heat-treating the polysilicon film at a predetermined temperature such that the grain size at the contact portion with the oxide film is formed differently, and then doping is performed.
이제 본 발명의 한 실시예에 대하여 첨부도면을 참조하여 상세하게 설명되게 된다. 먼저 제1a도에 도시된 바와 같이, 반도체 기판(1)상에 얇은 산화막(2)을 형성하고, 그 위에 LPCVD 방식으로 약 590℃ 내지 약 610℃의 온도 범위에서 약 0.03um 내지 0.3um의 그레인 사이즈를 갖는 폴리실리콘막(3)을 증착한다. 이때, 기존의 약 625℃ 부근의 온도에서의 증착 속도 보다 낮은 반응 속도로 폴리실리콘막이 형성되므로 파티클 발생 가능성이 줄어들게 된다. 다음에는 제1b도에 도시된 바와 같이, 질소(N2) 분위기에서 약 900℃의 고온으로 폴리실리콘막(3)을 열처리 한다. 이때, 산화막(2) 표면과의 접촉 부위(3A)의 그레인 사이즈는 약 0.03um 내지 0.3um 크기로 거의 변화가 발생하지 않게 되지만, 폴리실리콘막(3)의 표면 부위(3B)의 그레인 사이즈는 약 0.3um 내지 1um 정도의 크기로 변하도록 제어할 수 있다. 다음에 POCl3도핑을 실시하게 되면, 도펀트의 확산 속도는 그레인 사이즈에 비례하므로 도핑 공정 동안 전술한 그레인 사이즈의 차이에 의해 초기에는 빠르게 도핑이 진행되고 점차 그레인 사이즈가 작아지므로 도핑속도가 늦어지게되므로 도핑 농도의 제어가 용이하게 되므로 산화막(2)과의 접촉면에서 도펀트가 포화상태가 되는 것을 방지할 수 있다.One embodiment of the present invention will now be described in detail with reference to the accompanying drawings. First, as shown in FIG. 1A, a thin oxide film 2 is formed on the semiconductor substrate 1, and thereon, grains of about 0.03 um to 0.3 um are formed thereon in a temperature range of about 590 deg. C to about 610 deg. A polysilicon film 3 having a size is deposited. At this time, since the polysilicon film is formed at a reaction rate lower than the deposition rate at a temperature of about 625 ° C., the possibility of particle generation is reduced. Next, as illustrated in FIG. 1B, the polysilicon film 3 is heat-treated at a high temperature of about 900 ° C. in a nitrogen (N 2 ) atmosphere. At this time, the grain size of the contact portion 3A with the surface of the oxide film 2 is about 0.03 um to 0.3 um, so that almost no change occurs, but the grain size of the surface portion 3B of the polysilicon film 3 is It can be controlled to change the size of about 0.3um to 1um. The next time the POCl 3 doping is carried out, the dopant diffusion rate is proportional to the grain size, and thus the doping rate is slowed down early due to the difference in grain size during the doping process. Since the doping concentration can be easily controlled, it is possible to prevent the dopant from becoming saturated at the contact surface with the oxide film 2.
고집적 반도체 소자 제조시, 전술한 바와 같은 본 발명에 따라 폴리실리콘막을 형성하므로써, 파티클 발생 가능성을 줄이고, 도핑 농도 조절에 의한 저항의 조절이 용이해지며, 하부층과의 접촉면에서의 도펀트의 포화를 방지할 수 있으므로 후속 공정인 식각 공정에서 과도 식각을 방지할 수 있다는 효과가 있다.When manufacturing a highly integrated semiconductor device, by forming the polysilicon film according to the present invention as described above, it is possible to reduce the possibility of particle generation, to easily control the resistance by adjusting the doping concentration, and to prevent the saturation of the dopant on the contact surface with the underlying layer Since it is possible to prevent the excessive etching in the subsequent etching process.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950054384A KR100214840B1 (en) | 1995-12-22 | 1995-12-22 | Method for forming polysilicon layer of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950054384A KR100214840B1 (en) | 1995-12-22 | 1995-12-22 | Method for forming polysilicon layer of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR970051990A KR970051990A (en) | 1997-07-29 |
| KR100214840B1 true KR100214840B1 (en) | 1999-08-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950054384A KR100214840B1 (en) | 1995-12-22 | 1995-12-22 | Method for forming polysilicon layer of semiconductor device |
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| KR100543655B1 (en) | 2003-06-30 | 2006-01-20 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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| KR970051990A (en) | 1997-07-29 |
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