KR100214264B1 - Method of forming gate oxide film - Google Patents
Method of forming gate oxide film Download PDFInfo
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- KR100214264B1 KR100214264B1 KR1019950050487A KR19950050487A KR100214264B1 KR 100214264 B1 KR100214264 B1 KR 100214264B1 KR 1019950050487 A KR1019950050487 A KR 1019950050487A KR 19950050487 A KR19950050487 A KR 19950050487A KR 100214264 B1 KR100214264 B1 KR 100214264B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02249—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by combined oxidation and nitridation performed simultaneously
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
Abstract
본 발명은 반도체소자의 게이트 산화막 형성방법에 관한 것으로, 산화막 양쪽 계면의 경도가 크면서 산화막 벌크의 신뢰도가 높은 게이트 산화막을 제조하기 위하여 실리콘 기판 표면에 N2O에 의해 제1질화 산화막을 형성하고, 수 % NH₃를 N2O 분위기속으로 흘려 보내어 상기 제1질화 산화막과 실리콘 기판의 계면에 제2질화 산화막을 형성하고, N2O에 의한 어닐 공정을 실시하여 상기 실리콘 기판과 산화막의 계면에 제3질화 산화막을 형성함으로써 게이트 산화막 내의 결함을 줄여주고 질소에 의한 새로운 전자 트랩 센터를 없애 소자의 신뢰성 및 수율을 향상시킬 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate oxide film of a semiconductor device, wherein a first nitride oxide film is formed on a surface of a silicon substrate by N 2 O to produce a gate oxide film having high hardness at both interfaces of the oxide film and high reliability of an oxide bulk. And several% NH3 are flowed into the N 2 O atmosphere to form a second nitride oxide film at the interface between the first nitride oxide film and the silicon substrate, and annealing with N 2 O is performed to the interface between the silicon substrate and the oxide film. By forming the third nitride oxide film, it is possible to reduce defects in the gate oxide film and to eliminate new electron trap centers by nitrogen, thereby improving the reliability and yield of the device.
Description
제1도 내지 제3도는 본 발명의 실시예에 의해 게이트 산화막을 형성하는 단계를 도시한 단면도.1 to 3 are cross-sectional views showing steps of forming a gate oxide film according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 제1질화 산화막1 silicon substrate 2 first nitride oxide film
3 : 제2질화 산화막 4 : 제3질화 산화막3: second nitride oxide film 4: third nitride oxide film
본 발명은 반도체소자의 게이트 산화막 형성방법에 관한 것으로, 특히 산화막 양쪽 계면의 경도가 크면서 벌크의 신뢰도가 높은 게이트 산화막이나 터널 산화막을 요구하는 초고집적 DRAM 소자 또는 플래쉬(Flash)EEPROM에 적용할 수 있는 게이트 산화막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate oxide film of a semiconductor device. In particular, the present invention can be applied to an ultra-high density DRAM device or a flashEEPROM that requires a gate oxide film or a tunnel oxide film having high bulk reliability and high hardness at both interfaces of the oxide film. The present invention relates to a gate oxide film forming method.
N2O를 이용한 질화(mitridation) 방법은 산화막 성장속도가 느려서 열적버짓(thermal budget)이 크고, Si/SiO2계면쪽만 질화되어 폴리게이트 인젝트(Poly gate injection)에 대해서 신뢰성을 증가시키지 못하고, 수 % NH3/N2O분위기에서 성장한 질화산화막은 산화막 성장속도가 빠른 대신 양쪽 계면이 빽빽하게 질화(heavily nitridation) 되지 못하는 단점이 있다.The nitriding method using N 2 O has a high thermal budget due to the slow growth rate of the oxide film, and only a Si / SiO 2 interface is nitrided to increase the reliability of poly gate injection. For example, nitride oxide films grown in a few% NH 3 / N 2 O atmospheres have a disadvantage in that both surfaces are not nitridated at the same time as the oxide film growth rate is high.
따라서, 본 발명은 상기한 문제점을 극복하기 위하여 산화막 전체를 질화시켜서 산화막의 계면 및 벌크의 결함들을 없애주기 위해서 먼저 N2O에 의한 위쪽 산화막의 계면 질화와 즉시 인시튜(in-situ) 로 NH₃ 밸브를 열어서 수%의 NH3가 N2O에 혼합되도록 하여 수 % NH3/ N2O 분위기를 만들어 빠른 성장률을 얻고 벌크를 질화시킨다음, 다시 NH₃ 밸브를 달아서 아래쪽 산화막의 계면을 질화 시킴과 동시에 잔류해 있을 NHｘ를 열처리하여 없애주는 게이트 산화막 형성방법을 제공하는데 그 목적이 있다.Accordingly, the invention is NH₃ by interfacial nitride and immediately in-situ (in-situ) at the top of the oxide film due to the N 2 O first, by nitriding the whole oxide order to eliminate the interface and defects in the bulk of the oxide film in order to overcome the above problems was getting a number% of NH 3 by opening the valve can be mixed% NH 3 / N 2 O atmosphere is created and rapid growth in the N 2 O nitride bulk, and then re-strapping NH₃ valve and Sikkim nitride to the lower oxide interface At the same time, an object of the present invention is to provide a method for forming a gate oxide film by removing a residual NH 없애 by heat treatment.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체소자의 게이트 산화막 형성방법은 게이트 산화막 형성방법에 있어서, 실리콘 기판 표면에 N2O에 의해 제1질화 산화막을 형성하는 단계와, NH3를 N2O분위기속으로 흘려 보내어 상기 제1질화 산화막과 실리콘 기판의 계면에 제2질화 산화막을 형성하는 단계와, N2O 분위기에서 어닐 공정을 실시하는 상기 실리콘 가판과 제2질화 산화막의 계면에 제3질화 산화막을 형성하는 단계로 이루어지는 것을 제1특징으로 한다.In the gate oxide film forming method of the semiconductor device according to the present invention for achieving the above object, in the gate oxide film forming method, forming a first nitride oxide film by N 2 O on the surface of the silicon substrate, NH 3 N 2 Forming a second nitride oxide film at an interface between the first nitride oxide film and the silicon substrate by flowing into an O atmosphere, and performing a third annealing process at an interface between the silicon substrate and the second nitride oxide film to be annealed in an N 2 O atmosphere. It is a 1st characteristic which consists of forming a nitride oxide film.
상기한 목적을 달성하기 위해 본 발명에 따른 게이트 산화막 형성방법은, 게이트 산화막 형성방법에 있어서, 실리콘 기판 표면에 N2O에 의해 제1질화 산화막을 형성하는 단계와, NH3를 N2O 분위기속으로 흘려 보내어 제2질화 산화막을 형성하는 단계와, N2O 분위기에서 어닐 공정을 실시하여 제3질화 산화막을 형성하는 단계와, 실리콘 기판 표면 N2O에 의해 제4질화 산화막을 형성하는 단계와, NH₃를 N2분위기속으로 흘려 보내어 제5질화 산화막을 형성하는 단계와, N2O 분위기에서 어닐 공정을 실시하여 제6질화 산화막을 형성하는 단계를 포함하는 것을 제2특징으로 한다.In order to achieve the above object, the method for forming a gate oxide film according to the present invention includes the steps of: forming a first nitride oxide film by N 2 O on a surface of a silicon substrate in a gate oxide film formation method, and NH 3 in an N 2 O atmosphere. Forming a second nitride oxide film by flowing into the substrate, performing an annealing process in an N 2 O atmosphere, and forming a third nitride oxide film, and forming a fourth nitride oxide film by the silicon substrate surface N 2 O. And forming a fifth nitride oxide film by flowing NH 3 into the N 2 atmosphere and performing an annealing process in the N 2 O atmosphere to form a sixth nitride oxide film.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제1도 내지 제3도는 본 발명의 실시예에 의해 게이트 산화막을 형성하는 단계를 도시한 단면도이다.1 to 3 are cross-sectional views showing steps of forming a gate oxide film according to an embodiment of the present invention.
제1도는 실리콘기판(1) 상부에 N2O에 의해 제1질화 산화막(2)을 형성한 단면도이다. 이때 계면을 빽빽하게 질화시키기 위해서 상압이나 상압에 가까운100∼900 Torr에서 진행시키고, 충분한 제1질화 산화막(2)이 형성되도록 10Å정도 이상 성장시켜야 한다.FIG. 1 is a cross-sectional view in which the first nitride oxide film 2 is formed of N 2 O on the silicon substrate 1. At this time, in order to nitrate the interface densely, it should be proceeded at 100 to 900 Torr, which is close to normal pressure or normal pressure, and grown to about 10 GPa or more so that sufficient first nitride oxide film 2 is formed.
제2도는 압력을 수십 Torr정도로 내린 다음, 1∼9% NH₃를 N2O 분위기 속으로 흘러 보내어 상기 제1질화 산화막(2)과 실리콘 기판(1)의 계면에 제2질화 산화막(3)을 형성한 것이다. 이때, 압력을 10 ∼90 Torr 로 낮춘 이유는 NH3와 N2O의 폭발적인 반응에 대한 안전 때문이다. 이러한 반응을 거쳐 생성물로서 H2O와 NHx 생기는데, H2O는 산화막의 성장률을 빨리하여 앞서 형성된 제1질화 산화막(2)의 질소가 다른 부분으로 확산되는 것을 방지하고 그 자리에 있도록 만든다. 또한 NHx에 의해 새로 형성되고 있는 산화막 전체를 질화시킨다. 이 산화막에는 질소가 많이 함유되고 있지 않아야 된다. 산화막 벌크에 질소가 많이 함유되어 있으면 새로운 전자 트랩 센터(electron trapceneter)가 되기 때문이다. 따라서 H2O에 의한 빠른 성장률 때문에 질소의 함량이 크게 떨어지게 된다.FIG. 2 shows a pressure drop of several tens of torr and then flows 1-9% NH3 into an N 2 O atmosphere to form a second nitride oxide film 3 at the interface between the first nitride oxide film 2 and the silicon substrate 1. It is formed. At this time, the pressure was lowered to 10 to 90 Torr because of the safety against the explosive reaction of NH 3 and N 2 O. H 2 O and is kind NHx as a product after this reaction, H 2 O is prevented by the fast growth rate of the oxide of nitrogen in the first nitride oxide film (2) formed previously from spreading to other parts and made to be in its place. In addition, the whole of the oxide film newly formed by NHx is nitrided. This oxide film should not contain much nitrogen. This is because a large amount of nitrogen in the oxide film becomes a new electron trap center. Therefore, the nitrogen content is greatly reduced because of the rapid growth rate by H 2 O.
제3도는 NHx의 수소는 후속 N2O 어닐(anneal)에 의해 없어질 뿐만 아니라, 이 N2O어닐에 의해 Si/SiO₂계면쪽이 빽빽하에 질화되어 제3질화 산화막(4)이 형성되는데, 이를 위해 다시 압력을 상압에 가까운 압력으로 올릴 필요가 있다.In FIG. 3, not only hydrogen of NHx is removed by a subsequent N 2 O anneal, but the N 2 O anneal is densely nitrided on the Si / SiO 2 interface to form a third nitride oxide film 4. To this end, it is necessary to raise the pressure to a pressure close to normal pressure.
본 발명의 다른 실시예는 상기한 본 발명의 공정을 반복적으로 실시하는 것이다.Another embodiment of the invention is to repeatedly carry out the process of the invention described above.
이와 같은 공정에 의해 양쪽 계면이 빽빽하게 질화 되고 산화막 벌크가 가볍게 질화 되면서 성장률이 빠른 질화산화막을 얻을 수 있다.Through this process, both interfaces are densely nitrided and the oxide film bulk is lightly nitrided to obtain a nitride oxide film having a high growth rate.
이상에서 설명한 바와 같이 본 발명에 따른 게이트 산화막 형성방법은, 본 발명에 의해 성장된 새로운 질화산화막은 그 성장속도가 빨라 열적 버짓을 줄일 수 있고, 양쪽 계면이 질화되어, 기판쪽 전자 인젝션 뿐만 아니라, 게이트 전극 쪽 전자 인젝션에 대해서도 경도(hardeness)가 증가하여 소자의 신뢰성을 크게 증가시키고, 산화막 벌크를 적당히 질화시켜 산화막내의 결함을 줄여주고 질소에 의한 새로운 전자 트랩 센터를 없애 소자의 신뢰성 및 수율을 크게 향상시킬 수 있다.As described above, in the method for forming a gate oxide film according to the present invention, the new nitride oxide film grown by the present invention has a rapid growth rate, which can reduce thermal budget, and both interfaces are nitrided, so that not only the electron injection on the substrate side, The hardness of the gate electrode increases, which greatly increases the reliability of the device, moderately oxidizes the oxide bulk, reduces defects in the oxide film, and eliminates new electron trap centers by nitrogen, which greatly increases the reliability and yield of the device. Can be improved.
Claims (5)
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| KR100455737B1 (en) * | 1998-12-30 | 2005-04-19 | 주식회사 하이닉스반도체 | Gate oxide film formation method of semiconductor device |
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