KR100213873B1 - Apparatus and method for trick mode in dvcr - Google Patents

Abstract

The present invention relates to an apparatus and method for implementing a trick mode of a digital VTR, and by setting an efficient track format for implementing a track mode in a digital VTR system, the trick mode can be easily implemented by phase locking using an opposing head. It is an object of the present invention to provide an apparatus and method for implementing a trick mode of a digital video home system.

According to an apparatus and method for implementing a trick mode of a digital VTR according to the present invention, an opposite type is set by setting a track format for repeatedly recording trick data in a trick data area on a track having the same phase as many times as the trick speed. The trick mode can be easily implemented by phase locking using a head. In particular, since it is possible to easily change the track format for the trick mode, it is possible to implement a trick mode of various double speeds, which may be easily applied to an actual digital VTR system.

Description

Apparatus and method for implementing the trick mode of a digital video tape recorder.

The present invention is an apparatus and method for implementing a trick mode of a digital video tape recorder (hereinafter referred to as a digital VTR), and more particularly, in a digital VTR, an efficient method for a trick mode. An apparatus and method for implementing a trick mode of a digital VTR that can easily implement a trick mode by phase locking using an opposing head by setting a track format.

In recent years, as the demand and demand for digital data storage technology have soared, standardization work is actively underway to establish the digital VTR standard, which is one of the digital image storage devices that can generate a wide range of economic benefits and technical ripple effects. .

Related standards include SD VTR (Standard Definition VTR) and JVC (Japan Victor Company) of Japan, which are proposed for companies such as Phillips, Sony, Thomson, Matsushita, etc. Is the specification of the Digital VHC Video Home System Video Tape Recorder (VTR), which is being pursued by

The SD VTR has a processing speed of 25 Mbps (Mega bit per second), the head drum has 9000 revolutions per minute (rpm), the head drum has a diameter of 6 mm, and the digital VHS VTR has a processing speed of 14.10 Mbps, and the head drum The rotational speed per minute is 1800 times, and the diameter of the head drum is 4 mm. A general digital VTR system is described with reference to FIG. 1 as follows.

As shown in FIG. 1, a general digital VTR system receives data and adds additional information to the input data to protect the input data from errors, and stores the input data and the additional information on the tape 50. As shown in FIG. An encoder 1 which modulates in an easy-to-follow form, and reads the data recorded on the tape 50 by the encoder 1 to refer to the additional information, which can occur during storage and playback. Decoder (2) for recovering the original data from the various errors that are present, wherein the encoder (1) is input from the data input unit 10 for receiving data and errors that may occur during storage and playback In order to protect the digital data, a channel coder 20 for adding a channel code to the input data and an output of the channel coder 20 are received. It consists of a data modulator 40 for modulating the signal into a form easy to store on the tape 50, the decoder 2 is to read and demodulate the data recorded on the tape 50 A data decoder 60, a channel decoder 70 for detecting a channel code from the demodulated data, and then removing the channel code from the read data, and the channel decoder And a data output unit 80 for receiving data from 70 and outputting the data.

The channel encoder 20 is a shuffler 21 which converts a burst error into a random error as removing the burstness of the input data received from the data input unit 10. And an error correction coder 30 which receives an output of the shuffling unit 21 and adds an error correction code to the input data, wherein the error correction coder 30 receives a concatenation error. An outer code error correction coder 31 for generating an outer code through error correction encoding to add to the shuffled input data, and outputting data in order of data before being shuffled; It consists of an internal code error correction coder 32 which receives the output of the external code error correction coder 31 and generates an inner code for removing the scattering error and adds it to the data.

In addition, the channel decoder 70 is the inverse of the channel coder 20, corrects an error using the internal code of the read data input from the demodulator 60, and then internally reads the read data. An internal call error correction decoding unit 71 for removing a call; an inverse shuffling unit 72 for receiving the output of the internal call error correction decoding unit 71; and shuffling the shuffled data; and a reverse shuffling unit. And an external code error correction decoding unit 73 for correcting an error using the external code after receiving the output of 72 and removing the external code from the read data.

The operation of the general digital VTR system will be described in detail with reference to FIG.

First, when data is received through the data input unit 10 and provided to the shuffling unit 21, the shuffling unit 21 improves the recovery capability of the consolidation error by removing the coherence of the data.

In brief with respect to the errors of the digital system in relation to the shuffling unit 21, the errors of the digital system include sporadic errors occurring randomly and burst errors occurring continuously and intensively at a specific location. There is).

In a digital storage device, large-scale collection errors are likely to occur due to contamination of the recording / reproducing head and optical pickup, tape defects, and scratching of the disk. For this reason, countermeasures against aggregation errors are very important in digital systems such as digital audio tape recorders (DAT), digital VTRs, and compact disks (CDs).

There are various methods for countermeasure of aggregation error, but interleave is most commonly used. Interleaving is a method of distributing word arrays of consecutive digital data according to a predetermined rule, and scrambled and recording them so that bits that existed close to each other are not adjacent to each other. When data is recorded in such an interleaved manner, it is possible to disperse intensive and continuous error occurring in a continuous manner, thereby greatly improving the error detection and correction capability of the system.

In a rotary-head digital audio tape recorder (R-DAT) or digital VTR that uses a helical scan method, the amount of information that can be recorded depends on the mechanical mechanism (such as the number of revolutions of the head drum and the diameter of the recording head). As a result, the block interleave method of distributing and writing data in units of blocks is adopted. This is a method of interleaving data by making a sample signal in block units and sequentially writing them in a memory, and then controlling the sequencer out of order.

As a result, the data is evenly distributed over several recording heads and recorded on the tape, so that in the R-DAT, even if a large collection error occurs, error detection and correction is very easy.

Interleaving is referred to as shuffling in digital VTR systems. The two terms are synonymous in terms of error detection and correction. Signal processing by interleaving and shuffling is not limited to recording formats of tapes such as digital VTRs and R-DATs, but is equally applied to almost all digital systems such as CDs and digital broadcasts.

As described above, the shuffling portion 20 of the digital VTR prevents the entire track from being corrupted by eliminating cohesion, and it is generally common to shuffle data in units of 6 tracks.

In this way, the shuffling unit 20 provides randomicity to data to maximize error detection and correction characteristics of the error correction code unit 30 at the rear end.

On the other hand, the external code error correction coder 30 generates and adds an error correction code for correcting a concatenation error and a scattering error through Reed Solomon coding (RS coding).

Accordingly, the outer code error correction coder 31 reads data in a shuffling sequence defined by the shuffling unit 21 and corrects a concatenation error in data shuffled through Reed Solomon coding. After adding a call, data is output in the same order as the output order of the shuffling unit 21, and the inner code error correction coder 32 outputs the outer code error correction coder 32 through Reed Solomon coding. An internal code for correcting a scattering error is added to the received data and applied to the data modulator 40.

Reed-Solomon coding is an error-correcting coding technique that simultaneously corrects the concatenation and scattering errors proposed by IS Reed and G. Solomon in 1960. It is a code and scheme in which the binary BCH (Bose, Chaudhuri, Hocquenghen) code proposed by Hochquenghen is expanded to a non-binary BCH code.

Here, BCH encoding is a coding method in which a Hamming code, which is a single correction code, is expanded into a multiple error correction code that can correct several scattered errors.

For a detailed description of the above shuffling technique and Reed Solomon coding, refer to Peter Sweeny's book, Error Control Coding An Introduction, published by Prentice Hall. .

Subsequently, the data modulator 40 receives the channel-coded output data and modulates the data in a form that is easy to record on the tape 50.

The operation of the decoder 2 is in the reverse order of the encoder 1. After the demodulation of the signal that has been modulated through the data demodulator 60, the scattering that may occur during storage and playback using the channel decoder 70 is performed. Correct errors and association errors.

That is, the data demodulator 60 reads and demodulates the data recorded in the data 50, and the internal code error correcting decoder 71 receives the read data from the data demodulator 60 to receive the internal code. After correcting the concatenation error by using the internal data, the internal code is removed from the read data and provided to the reverse shuffling unit 72. The output of the internal code error correction decoding unit 72 of the reverse shuffling unit 72 is received. After performing inverse shuffling to solve the data in the original arrangement, the outer code error correcting decoding unit 73 receives the output of the inverse shuffling unit 72 and corrects the scattering error using the outer code. When an external code is removed from the read data and applied to the data output unit 80, the data output unit 80 outputs data through a display device, an acoustic device, a transmission device, or the like.

Meanwhile, Moving Picture Experts Group-2 (MPEG-2), a video standard established by the Video Standardization Expert Group under the International Standard Organization (ISO), has been developed by HDTV (High Definition TV) and satellite broadcasting. As the possibility of being adopted as a standard of video codec for video is relatively high, the interest of research in the development of storage format for storing data bitstream according to MPEG-2 format It is concentrated.

Taking advantage of the above facts, technologies for storing data bit strings according to MPEG-2 format in digital VTRs are being developed day by day. In general, such digital VTR storage techniques are digital data bit strings in MPEG-2 format. After receiving the digital data bitstream and performing error correction encoding, the digital data to which the error correction code is added is modulated and recorded on the tape, and during reproduction, the digital data recorded on the tape is demodulated and stored through error correction decoding. It is common to recover error data that may occur during overplay and to output the data in a bit stream.

However, in order to store MPEG-2 format data in a conventional general digital VTR system, it is necessary to change the conventional track format to a track format that can accommodate the MPEG-2 standard.

In particular, in order to support a trick mode, which is a type of fast seek mode supported by MPEG-2, in a digital VTR system, data is divided into a normal data region and a trick data region on a track of a tape. As recording is required, the setting of a track format that can accommodate the trick mode is a problem to be prioritized first.

Accordingly, an object of the present invention is to solve such a problem, and by setting an efficient track format for implementing a track mode in a digital VTR system, a trick mode can be easily implemented by phase locking using an opposing head. An apparatus and method for implementing a trick mode of a digital video home system may be provided.

1 is a block diagram illustrating a digital video tape recorder system.

2 is a block diagram showing an apparatus for implementing a trick mode of a digital video tape recorder according to the present invention.

3 is an exemplary diagram showing a track structure of a digital VHS VTR tape.

4 is an exemplary diagram showing a sync block of a track of a digital VHS VTR tape.

5 is an exemplary diagram showing an ECC block of a track of a digital VHS VTR tape.

FIG. 6 is an exemplary diagram illustrating a track format supporting 9x dedicated trick mode according to an embodiment of the present invention. FIG.

7 is a flowchart showing a method for implementing a trick mode of a digital video tape recorder according to the present invention.

* Explanation of symbols for main parts of the drawings

100: data array unit 110: data separation unit

120: region setting unit 130: data rearrangement unit

140: multiplexer 200: data combination unit

210: demultiplexer 220: data reproducing unit

S300: data array step S310: data separation step

S320: Area setting step S330: Trick data rearrangement step

S340: Multiplexing Step S400: Channel Coding Step

S410: shuffling step S420: outer code error correction encoding step

S430: Inner code error correction encoding step

S440: Data Modulation Step S500: Channel Decoding Step

S510: Data demodulation step S520: Inner code error correction decoding step

S540: deshuffling step S550: outer code error correction decoding step

S600: Data Combination Step S610: Demultiplexing Step

S620: data playback step

An apparatus and method for implementing a trick mode of a digital VTR according to the present invention for achieving the object of the present invention as described above repeatedly records trick data in the trick data area on a track having the same phase as many times as the trick speed. By setting a track format, the trick mode can be easily implemented by phase locking using an opposing head.

Hereinafter, a preferred embodiment of an apparatus for implementing a trick mode of a digital VTR according to the present invention will be described with reference to FIG. 2.

As shown in FIG. 2, the conventional method of implementing the trick mode of the digital VTR according to the present invention is a conventional digital VTR system composed of an encoder 1 and a decoder 2 that perform channel encoding and channel decoding, respectively. After extracting the normal data and the trick data from the input data, the normal data area and the trick data area are set on the track of the tape, and the trick data is assigned to the speed of the track data area on the track having the same pace. A data arranging unit 100 for arranging data to be repeatedly recorded as many times is included between the data input unit 10 and the channel coder 30 of the encoder 1, and by phase locking using an opposing head. The channel decoder 70 provides a data combination unit 200 for selectively combining the read normal data and trick data according to an operation mode and outputting the combined data. It is configured to include between the output section 70.

Here, the data arranging unit 100 may include a data separating unit 110 that separates normal data and trick data from input data, a normal data area in which normal data is to be recorded by receiving an output of the data separating unit 110. An area setting unit 120 for setting a trick data area in which trick data is to be recorded, and allowing normal data to be recorded in the normal data area, and having the same phase in the trick data area along the horizontal direction by the number of times of trick speed The trick data rearranging unit 130 rearranges the data so that the trick data is repeatedly recorded, and the output of the trick data rearranging unit 130 is received, and normal data is provided to the shuffling unit 21. A multiplexer 140 is provided to the inner code error correcting coder 32.

On the other hand, the data combination unit 200 receives the output of the outer code error correction decoding unit 73 in the normal mode, and inputs the output of the inner code error correction decoding unit 71 in the trick mode. The demultiplexer 210 receives the demultiplexer and the data reproducing unit 220 receives the output of the demultiplexer 210 and combines and reproduces the data according to an operation mode.

Hereinafter, the operation of the preferred embodiment of the present invention configured as described above will be described in detail.

Prior to explaining the operation of the preferred embodiment of the present invention, the description of the above-described trick mode is briefly described, and the trick mode is an operation mode that is also supported in MPEG-1, and an operation mode that is further enhanced in MPEG-2. One of them is an operation mode that supports fast and slow play, reverse play, and the like.

In the following description, the same reference numerals are given to parts overlapping with the conventional general digital VTR system described above, and the description thereof will be replaced with the above description.

First, when data is applied from the data input unit 10, the data separator 110 separates normal data and trick data from the input data.

In particular, the trick data is a sequence header, sequence extension, extension and user data, group of picture header, intra picture in MPEG-2 normal data. Only picture header, picture coding extension, and picture data of a picture are extracted and used as a trick bit sequence, and a unidirectional predictive picture (P-picture) and a bidirectional predictive picture are obtained. Data related to (Bidirectional predictive picture; B-picture) is not used as trick data.

Therefore, most of the trick data consists of data related to an intra picture (I-picture) included in the normal data.

For a detailed description of the above MPEG-2, reference is made to 13818-2 of ISO / IEC JTC1 / SC29 / WG11 Coding of Moving Pictures and Associated Audio, which is an MPEG-2 video standard.

Meanwhile, the area setting unit 120 receives the output of the data separating unit 110 and sets a normal data area in which normal data is to be recorded and a trick data area in which trick data is to be recorded on a track of the tape 50. The trick data rearranging unit 130 rearranges the data such that the normal data is recorded in the normal data area, and the trick data is repeatedly recorded in the trick data area by the number of times the trick speed in the horizontal direction. .

3 is an exemplary diagram showing a track structure of a digital VHS VTR data. The track refers to a unit area in the tape read by the head drum when the head drum is rotated once, and includes an integer number of sync blocks (SB), each sink block as shown in FIG. Similarly, it has a total block length of 112 bytes consisting of 2 bytes of sync, 3 bytes of identification, 99 bytes of data, and 8 bytes of parity.

Data relating to normal data and trick data is recorded in a main area composed of 336 sync blocks configured as described above, which occupy most recording areas on a track, and information relating to time and address in a sub area. The pre code and post amble areas enclosed in the front and back while the sub code containing the sub code are recorded, are sections for fastening a phase locked loop (PLL). It prevents distortion and supports accurate recording in the sub area.

In addition, the IBG (Inter Block Gap) provides a clearance gap (gab) so that an adjacent signal is not deleted even if a positional shift occurs during recording.

On the other hand, 112 sync blocks are combined to form an Error Correction Code (ECC) block, and each track has three ECC blocks, so that each track has a total of 336 sync blocks (that is, one track = 3 x 112 SB).

The ECC block is composed of 102 data sink blocks and 10 outer code error correction parity (ie, outer code) sync blocks, as shown in FIG. 5, each sink block having 8 bytes of internal code. (inner error correction parity).

The trick data rearranging unit 130 allocates 12 trick block areas for each ECC block, so that the trick data area exists in one track so that three trick data areas exist per track. Rearrange the data so that three sync blocks (i.e., 3 x 12 SBs) are allocated to the trick data area.

In the case of the digital VHS VTR system, the head drum rotates 30 times per second as the head drum rotates 1,800 times per minute. With an opposing head, the positive and negative tracks Since different data is recorded, it is possible to read the trick data of 72 sync blocks each time the head drum is rotated.

FIG. 6 is an exemplary diagram illustrating a track format supporting 9x speed trick mode according to an embodiment of the present invention.

The trick format used in the present invention is phase locking under the assumption that the opposite header and the 9x speed mode in which the polarities of the positive (+) and the negative (-) are located opposite to each other are used as shown in FIG. 6 as an example. To implement the trick mode.

As shown in Fig. 6, each of 18 tracks, such as i to (i + 17), (i + 18) to (i + 35), etc., becomes a basic track unit for reproducing trick data by pacing locking. Of the 18 tracks, nine tracks such as i, i + 2, i + 4, i + 6, i + 8, i + 10, i + 12, i + 14, i + 16, etc. have positive polarity. Nine tracks of i + 1, i + 3, i + 5, i + 7, i + 9, i + 11, i + 13, i + 15 and i + 17 have a negative polarity.

Each of the 12 sync blocks SB in three areas SBj to SBj + 11, SBk to SBk + 11, and SB1 to SB1 + 11 is a trick data area, and the rest are normal data areas SBO to SBj-. 1, SBj + 12 to SBk-1, SBk + 12 to SB1, and SB1 + 12 to SB335). Of the three trick data areas, SBj to SBj + 11 are designated as the first trick data area, SBk to SBk + 11 are designated as the second trick data area, and SB1 to SB1 + 11 are designated as the third trick data area. Different trick data is recorded in each area. Nine tracks with positive polarity and nine tracks with negative polarity in the three trick data areas are the same data. Therefore, the configuration of the track format as described above means that the same trick data is repeatedly recorded in the horizontal direction in the specific trick data area of the same polarity along the tape length direction. The remaining part in the main area except for the above-described trick data area represents a normal data area.

6, i + 2 tracks in the second trick data area, i + 4 tracks in the second trick data area, and i + 6 tracks in the third trick data area are shown in FIG. The negative head of the opposing head reads i + 11 tracks in the first trick data area, i + 13 tracks in the second trick data area, and i + 15 tracks in the third trick data area. It is shown. The amount of trick data for each track is 72 sink blocks (12 SB x 3 x 2 = 72 SB).

As described above, in order to implement the 9x search mode, half of the 18 tracks may be read in accordance with the polarity after repeating the same data of nine polarities and nine identical data of the negative polarity in the horizontal direction while using the opposite head.

In order to realize the 18x search mode, 18 tracks should be polarized based on 36 tracks, and the remaining 18 will have negative polarity. Can be implemented.

The multiplexer 140 receives the output of the trick data rearranger 130, provides normal data to the shuffling unit 21, and provides trick data to the internal code error correction coder 32.

Subsequently, the demultiplexer 210 receives the output of the outer code error correction decoder 73 in the normal mode, and inputs the output of the inner code error correction decoder 71 in the trick mode. Receiving demultiplexing is performed, and the data reproducing unit 220 receives the output of the demultiplexing unit 210 and selectively switches the data according to an operation mode to combine the data and output the same in the same format as the originally input MPEG2 input bit string.

Since the trick data does not perform shuffling and outer code error correction coding at the encoder 1, the decoder 2 does not perform reverse shuffling and outer code error correction decoding, because the trick data is an outer code error. It is difficult to process the sync block for corrective encoding and decoding processing. As the trick data is constructed using only the data related to the intra picture, even if an error occurs in the trick data, it affects only one frame and affects another frame. Because it does not give.

In particular, in the case of the fast search, the characteristics of the human's single angle that the degree of error is hardly recognized by the human eye are considered.

On the other hand, in the above preferred embodiment, the shuffling unit 21 shuffles the result data output from the inner code error correcting code unit 75, but the shuffling unit 76 replaces the outer code error correcting code unit 74. ) And the inner code error correction code unit 75, the result data output from the outer code error correction code unit 74 can be shuffled, and the inner error correction code can be added to the result data shuffled. The position of the reverse shuffling portion 82 is determined according to the position of the shuffling portion 76 at the time of data encoding.

In the first embodiment, the inverse shuffling unit 82 performs inverse shuffling on the bit stream of the data demodulated by the demodulation unit 81, but the inverse shuffling unit 82 replaces the inverse internal code error correcting code unit ( 84) and the reverse outer code error correcting code part 85 to reverse shuffle the result data output from the reverse internal code error correcting code part 84, and to reverse reverse shuffle the result data. Can be entered at 85.

Hereinafter, a preferred embodiment of the method for implementing the trick mode of the digital VTR according to the present invention will be described with reference to FIG. 7.

According to the present invention, a method of implementing a trick mode of digital VR is, as shown in FIG. 7, in a digital VTR system composed of an encoder 1 and a decoder 2 that perform channel encoding and channel decoding, respectively. After separating the normal data and the trick data from the video data, the area where the normal data and the trick data are recorded on the track of the tape is set, and the trick data is repeatedly repeated as many times as the trick speed in the trick data area on the track having the same phase. A data array step (S300) for recording, a channel encoding step (S400) for performing channel encoding on the normal data and the trick data, and recording on a storage means (here, a tape); and using an opposite head from the storage means. Channel decoding stage for performing channel decoding on the read data having read the data by phase locking Consists of (S500) and, selectively, the data combination step (S600) for selecting, combining and outputting the normal data and the trick-mode data in accordance with the operation from the read data.

Here, the data arrangement step (S300) is a data separation step (S310) for separating the normal data and trick data from the input data using the data separation unit 110, and receives the output of the data separation unit 110 An area setting step (S320) of setting a normal data area in which normal data is to be recorded and a trick data area in which trick data is to be recorded, and allowing the normal data to be recorded in the data area by using the data rearranging unit 130, the trick In the data area, a trick data rearranging step (S330) for rearranging data such that the trick data is repeatedly recorded in the horizontal direction at the position having the same phase so that the trick data is repeatedly recorded, and the output of the trick data rearranging unit 130 The normal data is input to the shuffling unit 21, and the trick data is provided to the internal code error correction coder 32. It consists of the neutralization step (S340).

The channel encoding step (S400) includes a shuffling step (S410) of converting a concatenation error into a scattering error by removing the coherence of the input data by using the sherring unit 21, and an outer code error correcting code unit 31. In step S420, an outer code is generated through error correction encoding to remove the concatenation error, and added to the shuffled input data, and then the data is output in the data order before being shuffled. And an internal code error correcting encoding step of receiving an output of the external code error correcting code part 31 and generating and adding an internal code to remove the scattering error using the internal code error correcting code part 32. (S430) and a data modulation step (S440) for modulating the output of the internal code error correction coder 32 and recording it in the storage means.

Further, the channel decoding step (S500) includes a data demodulation step (S510) for demodulating the read data read from the storage means, and correcting an error using the internal code of the demodulated read data, and then from the read data. After performing the inner code error correction decoding step (S520) and the inner code error correction decoding step (S520) to remove the inner code, and in the trick mode, the output of the inner code error correction decoding unit 71 is received. After the error is corrected using a reverse shuffling step (S540) of reverse shuffling the shuffled data and an external code that receives the output of the reverse shuffling unit 72 and removes the external code, the external data is read from the read data. External call error correction decoding step (S550) for removing the call.

On the other hand, the data combining step (S200) receives the output of the outer code error correction decoder 73 in the normal mode using the demultiplexer 210, and corrects the inner code error in the trick mode. A demultiplexing step (S610) of receiving an output of the decoding unit 71 and a data reproducing step (S620) of receiving and outputting the output of the demultiplexing unit 210 to combine and reproduce data according to an operation mode.

Hereinafter, an embodiment of a method of implementing the trick mode of the digital VTR according to the present invention will be described with reference to FIG.

In encoding, first, when data is input, in the data separating step S310, the normal data and the trick data are separated from the input data using the data separating unit 110, and in the region setting step S320, the data is separated. After receiving the output of the unit 110 and setting the normal data area in which the normal data is to be recorded and the trick data area in which the trick data is to be recorded, in the trick data rearrangement step S330, the data rearranger 130 is used. In the normal data area, normal data is recorded, and in the trick data area, the data is rearranged so that the trick data is repeatedly recorded as many times as the number of tricks in the horizontal direction at the position having the same phase. In the multiplexing step (S340), Receives the output of the trick data rearrangement unit 130 and provides the normal data to the shuffling unit 21, the trick day Is provided to the internal code error correction coder 32. Thereafter, after channel decoding is performed, data is recorded in the storage means.

In decoding, after reading data from the storage means and performing channel decoding, in the demultiplexing step (S610), the outer code error correction decoding unit 73 in the normal mode using the demultiplexer 210. In the case of the trick mode, the output of the internal code error correction decoding unit 71 is received.

Accordingly, in the data reproducing step (S620), the output of the demultiplexer 210 is input and combined and reproduced according to an operation mode.

As described in detail above, according to the apparatus and method for implementing the trick mode of the digital VTR according to the present invention, the trick data is repeatedly recorded in the trick data area on the track having the same phase as many times as the trick speed. By setting the track format, the trick mode can be easily implemented by phase locking using an opposing head.

In particular, since it is possible to easily change the track format for the trick mode, it is possible to implement a trick mode of various double speeds, which may be easily applied to an actual digital VTR system.

Claims (14)

A digital video tape recorder comprising an encoder including channel encoding means and a decoder including channel decoding means, wherein trick data is specified in a trick data area on a track having the same phase by extracting normal data and trick data from input data. A data arranging unit for arranging data to be repeatedly recorded as many times as the speed, and including the normal data and the trick data read from the tape by phase locking using an opposing head according to an operation mode. And a data combination unit for selectively combining and outputting the data combination unit, the data arranging unit separating the normal data and the trick data from the input data; An area setting unit for setting a track format to include a normal data area in which the normal data is to be recorded and a trick data area in which the trick data is to be recorded; Trick data for rearranging data such that normal data is recorded in the normal data area, and the trick data is repeatedly recorded in the trick data area at a position having the same phase so as to repeatedly record the trick data in the longitudinal direction of the tape. Apparatus for implementing a trick mode of a digital video tape recorder comprising a rearrangement unit. The method of claim 1, wherein the area setting unit allocates a predetermined sync block to the trick data area for each phase of each error correction code (ECC) block in the track format of the video home system. And allocating an area such that the same trick data is repeatedly recorded at the same phase position by the specific number of times of trick tricking in the tape length direction. 3. The apparatus of claim 2, wherein the predetermined sync block is a 12 sync block, and the phase positions are alternately spaced apart from each other. 3. The apparatus of claim 2, wherein the specific trick speed is 9 times speed. 2. The apparatus of claim 1, wherein the normal data consists of an MPEG-2 bit string, and the trick data consists of an intra picture of the normal data. The channel coding unit of claim 1, wherein the channel encoding means comprises: a shuffling unit for scattering error of a concatenation error as the consolidation of the input data is removed, and an outer code is generated and shuffled through error correction coding to remove the concatenation error. The external code error correction coder for outputting data in order of data before being shuffled, and an internal code for eliminating sporadic errors by receiving the output of the external code error correction coder. An internal code error correcting code part to be added, and a data modulating part for modulating the output of the internal code error correcting code part into a form that is easy to record on a tape, wherein the channel decoding means comprises a phase using an opposing head from the tape. A demodulator for demodulating the read data read by locking and the internal code of the read data. An error correction decoding unit for removing an internal code from the read data after the error correction, an inverse shuffling unit for receiving the output of the internal code error correction decoding unit and shuffling the shuffled data, and an inverse shuffling And an external call error correction decoding unit for correcting an error using the external code after receiving a negative output, and removing the external code from read data. The apparatus of claim 6, wherein the data arranging unit further includes a multiplexing unit which receives the output of the trick data rearrangement unit, provides the normal data to the shuffling unit, and provides the trick data to the inner code error correcting code unit. And a trick mode of a digital video tape recorder. 7. The method of claim 6, wherein the data combiner performs demultiplexing to receive the output of the outer code error correcting decoder in normal mode and to receive the output of the inner code error correcting decoder in trick mode. And a multiplexer and a data reproducing unit which receives the output of the demultiplexer and combines and reproduces the data according to an operation mode of the digital video tape recorder. A digital video tape recorder comprising an encoder including channel encoding means and a decoder including channel decoding means, wherein the normal data and the trick data are separated from the input data into normal data and trick data, and then on the track of the tape. A data arranging step of setting an area to be recorded and repeatedly recording the same trick data in a trick data area on a track having the same phase by a specific number of trick speeds; and performing channel coding on the normal data and the trick data to tape A channel encoding step of recording, a channel decoding step of reading data by phase locking using an opposing head from the tape and performing channel decoding on the read data, and selectively outputting the normal data from the read data according to an operation mode. Data and remind And a data combining step of selecting and combining the trick data and outputting the data, wherein the data arranging step comprises: a data separating step of separating the data separating the normal data and the trick data from the input data; An area setting step of setting a normal data area and a trick data area in which the normal data is to be recorded, and allowing the normal data to be recorded in the normal data area, and performing trick trick in a horizontal direction at a position having the same phase in the trick data area. And rearranging the data such that the same trick data is repeatedly recorded the same number of times. 10. The method of claim 9, wherein the channel encoding step comprises: a shuffling step of converting a concatenation error into a scattering error as removing the coherence of data; and generating and shuffling an outer code through error correction encoding to remove the concatenation error. An external code error correction encoding step of outputting data in order of data before being shuffled after adding to the input data; and an internal code error for generating and adding an internal code for removing a scattering error to the external code added data. And a correction encoding step and a data modulation step of recording on the tape. 10. The method of claim 9, wherein the channel decoding step includes a data demodulation step of demodulating the read data read from the tape, and correcting an error using the internal code of the demodulated read data, and then inserting the data from the read data. An inner shuffle error correction decoding step of removing a call; an inverse shuffling step of reverse shuffling read data from which the inner code has been removed in a trick mode after performing the inner code error correction decoding step; And an external call error correction decoding step of correcting an error by using the outer code after receiving the ringed data, and then removing the outer code. 12. The method of claim 10, wherein the data arranging unit receives an output of the trick data rearrangement unit so that the normal data performs the shuffling step, and the data further comprises a multiplexing step of performing an inner code error correction encoding step. A method of implementing a trick mode of a digital video tape recorder, comprising: The demultiplexing method of claim 11, wherein the data combining step comprises: receiving decoded data in which the outer code is removed in a normal mode and receiving decoded data in which the inner code is removed in a trick mode; And a data reproduction step of combining and reproducing the data according to the operation mode after performing the operation of the trick mode of the digital video tape recorder. 10. The method of claim 9, wherein the area setting step comprises assigning a predetermined sync block to the trick data area for each phase of each error correction code (ECC) block in a track format of a video home system. And allocating an area such that the same trick data is repeatedly recorded at the same phase position by the specific number of times of the trick trick in the tape length direction.