KR100210646B1 - Apparatus and method of detecting motion using content addressable memory - Google Patents

Abstract

1. TECHNICAL FIELD The invention described in the claims pertains to a motion detection apparatus for moving pictures using associative memory for performing a parallel search operation.

2. A technical problem to be solved by the present invention is to provide a motion detection apparatus capable of detecting motion of moving images at high speed by using an associative memory capable of comparing high-speed parallel search by comparing content information instead of stored position information.

3. Summary of Solution of the Invention: In response to the input of the write control signal, the image data of the window area is recorded in a predetermined cell therein, and the image data of the window area stored in the cell and the currently input image data are matched by a match signal. Compare and output the match signal simultaneously with associative memory cell arrays generating a match result signal and image data input within a preset scanning area to an associative memory cell array in which window data is stored in the associative memory cell array. And a motion determination unit for recording data of the recording area in the recording area in the scanning area into another associative memory cell array, and adding a weight according to the condition of the image data to the output match result signal to detect and determine a motion vector. .

4. Significant use of the invention: Used in moving picture motion detection devices.

Description

Motion Detection Device Using Associative Memory and Its Method

1 is a block diagram showing a conventional motion detection apparatus.

FIG. 2 is a diagram for explaining the relationship between video block divisions for detecting motion of moving images by a conventional technique.

3 is a diagram showing the structure of an associative memory cell according to an embodiment of the present invention.

4 is a block diagram of an associative memory according to an embodiment of the present invention.

5 is a block diagram showing the configuration of a motion detection apparatus for moving pictures according to an embodiment of the present invention.

6A to 6G are views for explaining a process of detecting motion in the motion detection apparatus of the moving picture shown in FIG.

7 is a flowchart of an operation process of the video motion detection apparatus of FIG.

* Explanation of symbols for main parts of the drawings

12: memory 14: motion detector

16: filter (frame) 20: bit storage

22: read / write controller 24: data / mask register

26: address selector and decoder 28: associative memory cell array

28A: Associative Memory Cell Array A 28B: Associative Memory Cell Array B

30: sense amplifier 32: response saver

34: MRR 36: address encoder

38: output register 40: processor

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a motion detection apparatus for moving images, and more particularly, to a motion image detection apparatus and method using a associative memory (CAM) for parallel search operation.

In general, a digital image processing system such as a moving image processing apparatus such as a digital television, a digital video camera, and the like is essentially provided with a motion detector for detecting a motion of a moving image for correction of an image signal and compression of image data. For example, video cameras are becoming thin and short due to consumer's desire. As a result, the camera shake is essentially generated when the subject is photographed. In order to compensate for image blur due to such a hand shake, it is necessary to detect a motion coefficient, that is, a motion vector. Also, as is well known for compressing a large amount of image data into a small amount of image data, the detection of a motion vector is essentially used.

The conventional moving picture motion detection method uses a dynamic random access memory capable of storing a picture of a field or a frame to determine a difference between an image signal of all the current and the current or the previous frame and the current frame. The method of detecting and detecting motion is used. Such a conventional technique is as shown in FIG.

1 is a block diagram showing a conventional motion detection apparatus. The configuration of the memory 12 outputs a delayed video data DVD by feeding or frame-delaying the currently input video data VD (Video Data), and comparing the video data VD with the delayed video data DVD by comparing the two. It consists of a motion detector 14 for detecting the motion vector MV. Here, the memory 12 is a dynamic random access memory having a storage capacity in a unit of a frame or frame.

FIG. 2 is a diagram for explaining the relationship between video block divisions for detecting a motion of a moving image by a conventional technique. In the figure, reference numeral 16 is an image in a unit of a frame or frame, and A, B, C, D, E, etc. are an image region obtained by dividing an image of a layer or a frame into a plurality of unit blocks.

First, the operation of the conventional motion device configured as shown in FIG. 1 will be described with reference to FIG.

The image data VD is input to the input terminals of the memory 12 and the motion detector 14, which constitute the motion detection device of FIG. The memory 12 has a capacity for storing an image of a feed or frame, and delays and outputs the input image data VD in a feed or frame unit. Therefore, the data output from the memory 12 becomes a feed or frame delayed image data DVD, which is immediately input to another input terminal of the motion detector 14.

The motion detector 14 compares the video data DVD delayed by the memory 12 with the video data VD currently input, that is, the video signal of the current or frame and the video signal of the previous or frame. Outputs At this time, as noted in the comparison, a difference between pixels versus pixels with the current screen is accumulated and detected based on the entire screen. For example, when the image data VD of the current screen is moved in the vertical and horizontal directions to obtain a cumulative value with the previous screen, in the case of a still image, since the correlation between the previous screen and the current screen is correlated with each other, the data is almost the same. Have. However, in the case of moving images, when the motion of the screen occurs as much as (X, Y) on the X, Y coordinates, the current screen is moved by (X, Y) to obtain the cumulative value of the pixel difference from the previous screen. Is the minimum. As can be seen from the above, the amount of (X, Y) movement at which the cumulative value is minimum becomes the motion vector MV.

As compared with the video data DVD of the previous screen and the video data VD of the current screen as described above, since the amount of data to be compared is too large, it takes considerable time to detect the motion vector MV. As shown in FIG. 2, image data of one screen is divided into several regions (A, B, C, D, and E of FIG. 2) to detect motion for each region, and then the weight according to the state of the screen is determined. The final motion vector MV is detected. Here, the weight according to the state of the screen means conditions relating to whether there are many high frequency components or whether the image is dark or bright.

However, the conventional technique having the configuration as shown in FIG. 1 has a problem that it cannot operate at high speed by detecting a motion vector MV using a dynamic random access memory. When data is searched using the dynamic random access memory as described above, since data must be accessed and searched sequentially by address, it takes much time to output image data of the divided region as shown in FIG.

In addition, in the prior art, since motion vector is obtained for each area by dividing the image data of the feed or frame into multiple data in order to detect the motion, the motion detection is often incorrect according to the state of the image data. Is generated. For example, motion detection becomes difficult when an area such as the sky or the sea having no high-frequency component on a screen, or a moving object such as a car that runs at high speed in the center of the screen passes. In other words, it is very difficult to determine the real motion in each of the divided regions as shown in FIG. When the screen is corrected as the motion vector detection information in which the motion vector is incorrectly detected due to the above-described cause, a serious phenomenon occurs in which the entire screen is moved. In order to solve such a problem, conventionally, a complicated algorithm and a dedicated microprocessor for detecting an accurate motion are used.

As described above, when random data is searched by storing image data using a dynamic random access memory in a conventional manner and searching and comparing the data using the stored image data, data is sequentially ordered according to an address. Searching data is very slow because it needs to be searched. In other words, each unit of information is processed sequentially, which causes a great amount of time to perform the search and comparison of data. Therefore, there is a problem that cannot support the fast data search speed required in a wide range of fields, such as information storage and modification of the high-speed conversion database, tracking of image data such as radar images.

Accordingly, an object of the present invention is to provide a motion detection apparatus and method capable of detecting motion of an image at high speed by using an associative memory capable of searching in parallel by comparing content information instead of stored location information. Is in.

Another object of the present invention is to provide an associative memory which can compare information of previously input data with information of currently input data at high speed and output the comparison information.

Another object of the present invention is to provide an associative memory cell structure having a structure capable of comparing information of stored contents at high speed.

The present invention for achieving the above object is a register controller for converting and outputting in parallel the serial image data input from the outside by the input of the shift output control signal, and the data output from the register controller by the write signal First and second associative memory cells which are stored in an associative memory cell connected to an active word line and which generate a match result signal by comparing the data stored in internal bit storage with the output data from the register controller in response to match control; An address controller that decodes an input external address, selects the first and second associative memory cell arrays, and activates a word line corresponding to the address; and outputs from one of the first and second associative memory cells Output level to save the match result signal to the internal storage area And the shift output control signal in response to the input of the image data in the set scanning area and output a match signal, and generate the write signal and the external address by data input of the recording area in the scanning area. And a motion determination unit for detecting a motion vector by giving a weight according to the condition of the image data to the match result signal stored in the output register.

The above objects and features of the present invention and other objects and features will become more apparent from the detailed description of the embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a view showing the structure of an associative memory cell according to the present invention. The associative memory cell stores write data lines for inputting the first and second write data W ₁ (1) and W ₁ (0) and the first and second write data C ₁ (1) and C ₁ (0). A bit storage 20 having input data lines respectively input, a set and reset node, and one node connected to the first and second write data lines, and at the same time on the word line (address) A1. Data write gates G1 and G2 which connect another node and set / reset the bit storage 20 in response to activation of the two input nodes, and each of the two input nodes is a set / restore of the bit storage 20. Connected to a set output node and the first and second input data lines, respectively, and an output node is commonly connected to each of the set / reset outputs of the bit storage 20 and the first and second input data lines, respectively. which is input first and second input data C _{1 (1),} compare the signals C ₁ (0) Match signal M1 match gates G6, G7 and for generating, and in response to the activation of the word line A1 is composed of data bits stored in the bit storage 20 to output the gate G5 to the inverting output.

In the configuration shown in FIG. 3, the bit storage 20 is configured by connecting two NAND gates G3 and G4 in the form of an RS flip-flop, and all other gates are formed of NAND gates. The output B1 of the NAND gate G5 is an output when reading recorded data, which is precharged to the level of the power supply voltage by the pull-up resistor R1 connected at one side to the power supply voltage VDD. In addition, the output M1 of the match gates G6 and G7 is the first and second write data W ₁ (1), W ₁ (0) and the first and second input data C ₁ (1) and C ₁ (0). Is activated when matching with the signal occurs, and the signal M1 is precharged to the level of the power supply voltage VDD by the resistor R2.

Operation of the associative memory cell configured as shown in FIG. 3 is largely performed in three modes. That is, a matching operation of outputting a matching result signal by comparing a write operation of storing data in the bit storage 20, a read operation of reading the stored data, and data newly input to the data stored in the bit storage 20. Can be divided into actions. The write, lead and matching operations as described above are the basic operations of the associative memory and will be described using the memory cell shown in FIG.

First, an operation process of writing data to the bit storage 20 will be described. As described above, in the bit storage 20, two NAND gates G3 and G4 are connected in the form of an R-S flip-flop.

The NAND gates G3 and G4 input data W ₁ (1) and W ₁ (0) input to the first and second write data lines to one node and input address information A1 to the other node. It is set or reset by the outputs of G1 and G2 to store the state.

The output of NAND gate G3 in bit storage 20 represents the value of the stored data bit.

The value of the NAND gate G3 is the information of the data W ₁ (1), W ₁ (0) of the first and second write data lines, and the information of the word line having address information A1 is W ₁ (1) = 0, W _It is set to logic 1 by the output of NAND gate G1 when it has a value of ₁ (0) = 1, A1 = 1.

If the information on the first and second write data W ₁ (1) and W ₁ (0) and the word information A1 is input to the first and second write data lines, respectively, W ₁ (1). When the value of = 1, W ₁ (0) = 0, A1 = 1, the output of the NAND gate G3 is reset to logic 0 by the output of the NAND gate G2. In order not to change the value of the addressed word and bit as described above, it is possible to mask by setting the information of the first and second write data W ₁ (1) and W ₁ (0) to all zeros. For example, when the information of the first and second write data W ₁ (1) and W ₁ (0) is set to 0, the data write gates G1 and G2 set / reset the bit storage 20. The outputs are all transitioned to 1 so that the output of the bit storage 20 always retains its stored state.

The operation of reading data stored in the bit storage 20 by the above process is initiated by activating the address line A1, which is a word line, to a logic high state. When the address information A1 is activated high, an output NAND gate G5 having an input connected to the word line A1 and an output node of the bit storage 20 is enabled and stored in the NAND gate G3 in the bit storage 20. The value of the bit is inverted and output to the bit line B1. At this time, the output of the bit line B1 is supplied to a sense amplifier (not shown).

On the other hand, the associative memory cell array configured as shown in FIG. 3 performs a matching operation in which the data stored in the bit storage 20 and the first and second input data C ₁ (1) and C ₁ (0) are compared in high speed in parallel. do. The matching operation is performed in parallel by writing the first and second input data C ₁ (1) and C ₁ (0) to logic 0 and 1 or 1 and 0. For example, the value of data stored in the bit storage 20 is 1, and the values of the first and second input data C ₁ (1) and C ₁ (0) are C ₁ (1) = 0 and C, respectively. _{When 1} (0) = 1, the outputs of the matchgates NAND gates G6 and G7 are all output high. As described above, when the outputs of the media gates G6 and G7 are all 1, the level of the match line M1 is kept high. At this time, although not shown in detail in the configuration of the present invention, the above-described matching operation is the output of the plurality of bit storage 20 located in the word direction and the first and second input data C ₁ (1), C ₁ (0 ) Is compared in parallel so that any one of the bits has a mismatch state, the output of matchline M1 is discharged to a level of zero. To mask the matchline M1, the level of the first and second input data C ₁ (1) and C ₁ (0) may be set to zero.

As described above, the associative memory cell according to the present invention can obtain a result by performing high-speed parallel search of content information stored in a plurality of bit storages and content information of currently input data instead of location information of stored data. It can be seen. As described above, the associative memory cell of the present invention which performs the matching operation by independently searching the stored data and the newly input data in parallel with the write and read operation of the data independently can be very useful for detecting the motion of moving images. Can be. This will be more clearly understood by the following description.

4 is a block diagram of the associative memory according to the present invention. In FIG. 4, the operation mode control circuit 22 selects an operation mode of the associative memory in response to input of a control signal input from the outside, for example, a read, write, and match signal. Has the function to set. The data / mask register 24 connected to the output of the operation mode control circuit writes data input from the outside in response to the set operation mode into an internal register and outputs the mask corresponding to the set operation mode. Mask the data of the corresponding bits in response to the input of the signal. Reference numeral 28 is an associative memory cell array composed of a plurality of associative memory cells as described in FIG. The address selector and decoder 26 decodes the address and the encoded address from the outside to activate the corresponding word line in the associative memory cell array 28. The sense amplifier 30 senses and amplifies the voltage difference between the bit line and the bit line of the associative memory cell array 28 to output data. The sense amplifier 30 is generally used to improve lead operation. The input offset voltage is designed to reduce the sensitivity of the sense amplifier and to reduce the adverse effects as much as possible because it may cause a decrease in operation speed and a malfunction. The response store 32 has a function of storing and outputting a match signal output from the match line Mi (where i is a natural number) of the associative memory cell array 28. Multiple response resolvers (hereinafter referred to as MRRs) connected to the output of the response store 32 sequentially operate when a plurality of match signals output from the response store 32 are simultaneously activated by a matching operation. The matched signal is processed and output so that the matched words can be encoded according to the priority. The address encoder 36 has a function of encoding and outputting an address of the corresponding word line when the matched word lines are input through the MRR 34 as a result of the execution of the matching operation. The output of the address encoder 36 may be output directly to the outside or may be fed back to the input of the address selector and decoder 26 as shown in FIG.

5 is a block diagram showing the configuration of a moving picture motion detection apparatus according to the present invention. The moving picture motion detection apparatus includes a write / match controller 22 generating a write and match operation control signal in response to input of a write signal and a match signal, and serial image data VD input from the outside by input of a shift output control signal. Is composed of a plurality of associative memory cells and converts the output data from the register controller 25 into active words according to the write control of the write / match controller 22. First and second associative memories, which are stored in associative memory cells connected to a line, and which generate a matching signal according to a matching operation between data stored in internal bit storage and data stored in the register controller 25 in response to a match control; Cell arrays (hereinafter referred to as CAM-A and CAM-B) 28A and 28B, and decoded external addresses to decode the two CAM-As (28A). And an address controller 26 for selecting at least one CAM among the CAM-B 28B and activating a word line corresponding to the address, and output from the CAM-A 28A and CAM-B 28B. An output register 38 for storing a match signal in an internal storage area, and counting the video data VD to generate a shift output control signal when the video data VD is in a preset scanning area, and simultaneously output and scan a match signal. A motion for detecting the motion vector MV by generating a write signal and an external address by data input as a recording area in the area and adding a weight according to the condition of the image data to the match result signal stored in the output register 38. The determination unit 40 is configured.

6A to 6G are views for explaining a process of detecting motion of a moving picture using an associative memory according to the present invention. FIG. 6A shows window data AB of the previous field for searching for motion information compared with data of the whole image data FS, the scanning area BB for detecting the motion of a moving image among the whole image data FS, and the scanning area BB. The size of the window data is 5 × 5 as shown in FIG. 6B.

FIG. 6C shows the scanning area BB, which shows that the scanning area BB is set to a size of 9x9 to detect a state of moving from the window data AB to two positions M (± X, ± Y) up, down, left, and right. FIG. 6E shows the data stored in the output register 38 as a data table as a result of comparing (matching) the data AB of the window area shown in FIG. 6B with the data BB of the scanning area shown in FIG. 6C.

FIG. 7 shows an operation flowchart of the circuit and the controller 40 shown in FIG.

Hereinafter, the motion detection operation relation of a moving image according to the present invention will be described in detail with reference to FIGS. 5, 6a to 6g and 7.

As is well known, the video data constitutes one frame representing one image in the even field and the odd field. The motion of a moving image can be detected based on one frame and can also be detected in units of fields. When detecting a motion based on the field, the even field and the odd field are interlaced with each other in the vertical direction. It should be noted that the following description of the present invention does not specifically limit it.

The CAM-A 28A and CAM-B 28B shown in FIG. 5 are mutually exclusive. For example, when the image data of the previous field or the previous frame is stored in the CAM-A 28A, the image data of the current field or the current frame is stored in the CAM-B 28B under the control of the write / match controller 22. Stored.

In the present specification, a field image will be described as an example. Initially, it is assumed that data recorded in the CAM-A 28A is stored in a size of 5x5 as shown in FIG. FIG. 6B shows the image data AB of a part of the entire image data FS shown in FIG. 6A, which means the previous field image data recorded to detect motion of a moving image.

When the serial image data VD of the current field to be scanned is input to the register controller 24 and the motion determining unit 40 shown in FIG. 5 in step 71 of FIG. 7, the motion determining unit 40 is inputted. The serial image data VD is counted to find out in step 73 whether the current image data is data located within a preset scanning area. In other words, it is to search whether the data is located in the scanning area BB set in advance in order to detect the motion of the moving image among the entire image data FS in FIG. 6A.

If the image data VD input by the above search is located in the scanning area, the motion determination unit 40 supplies the shift output control signal to the register controller unit 24 in step 74. Then, the motion determination unit 40 searches for the record area in step 75. For example, it is searched whether the image data VD of the current field input in the scanning area BB is the data in the data area of the hatched portion in FIG. 6C. At this time, the data of the recording area in the scanning area BB is as follows.

b33, b34, b35, b36, b37

b43, b44, b45, b46, b47

b53, b54, b55, b56, b57

b63, b64, b65, b66, b67

b73, b74, b75, b76, b77

At this time, the register controller 24 converts the image data VD currently input in parallel in units of a window block in response to the input of the output control signal and supplies it as comparison data in the CAM-A 28A. That is, when the image data is inputted from b11 of FIG. 6C, the register control unit 24 receives the 5-bit data b11, b12, b13, b14, and b15 having the horizontal size of the window block 5x5 of FIG. 6a. When data is input, it is converted into parallel data and supplied as comparison data in the CAM-A 28A. The parallel data output from the register controller 24 includes a plurality of first and second input data lines C _i (1) and C _i (0) located in the associative memory cells having the configuration shown in FIG. Is a natural water).

On the other hand, if it is determined that the motion determination unit 40 is not the search result recording area in step 75, the motion determination unit 40 supplies the match signal to the write / match controller unit 22 in step 77 to supply the cells in the CAM-A 28A. The data in the window area of the previous field stored in < RTI ID = 0.0 > is < / RTI > By this operation, the data a11, a12, a13, a14, a15 stored in the cells in the form of FIG. 6b from the CAM-A 28A having the configuration as shown in FIG. 2 and the data output from the register controller 24 b11, b12, b13, b14, and b15 are compared so that the matching result signal C (0, 0), where C is a logical value, has logical 1 when the two data values are the same, and 0 and 0 are coordinate values. Is output. The matching result signal C (0, 0) output as described above is stored in the output register 38 as shown in FIG.

The motion determiner 40 that has performed step 77 of FIG. 7 searches for the end of the scanning area BB in step 78. For example, it is detected whether matching to the data b98 of the last region of the scanning region BB as shown in FIG. 6C has ended. As a result, when it is not finished, the motion determination unit 40 returns to the above-described step 71 to detect the motion of the moving image and matches the window area data of the previous field as shown in FIG. 6b with the scanning area data as shown in FIG. 6c. Perform the action.

Accordingly, the matching result signal as shown in FIG. 6 is stored in the output register 38 by the continuous operation of the steps 71 to 75, 77 and 78 of FIG. That is, when the image data VD of b16 shown in FIG. 6C is input, the register controller 24 shifts the input image data VD to transfer the data up to b12, b13, b14, b15, and b16 to the CAM-A 28A. The matching result signal C (0, 1) is stored in the output register 38. By continuing the above process and extracting the matching result signal from C (0, 0) to (2, 2) in FIG. 6d, the motion determination unit 40 performs the data b33, b34, b35 of the recording area set in the scanning area BB. , b36 and b37, the write address is supplied to the address controller 26 in step 76 and recorded in another associative memory cell array CAM-B 28B, and the matching operation as described above is performed. The resultant signals C (2, 3) are stored in the output register 38.

When the above operation is continued and the matching operation to the data b81 placed at the final position of the scanning area BB shown in FIG. 6C is finished, the data of the hatched portion of FIG. 6C is recorded in the CAM-B 28B and outputted. In the register 38, matching result signals as shown in FIG. 6D are stored in a table. The data of the recording area stored in the CAM-B 28B is used as window data for detecting motion when the video data VD of the next field is input.

At this time, if the window data of the previous field as shown in FIG. 6B and the value of the scanning area BB of the current field (particularly, the hatched portion in FIG. 6C) are the same, the table value of the matching result signal stored in the output register 38 is equal to 6E. It is shown in the figure.

That is, in the case of motion M (0, 0), logic 11111 is output to the center position. If the matching result signal table value is the same as that of FIG. 6g as shown in FIG. 6b, it is determined as motion M (-2, 2). This means that the data of the window area AB of FIG. 6B is the same as the data of the upper left of the scanning area BB of FIG. 6C. That is, it means that the coordinate value of the center of 11111 is at the position of (-2, 2) based on the motion M (0, 0).

On the other hand, the motion determination unit 40 determines that the matching operation to the end of the scanning area as described above detects the motion using the information of the matching result signal table stored in the output register 38 in step 79 of FIG. The motion is determined by showing weights in the detection motion. The weighting is applied to the detected motion by the following method.

5 consecutive 1s: Median is motion M (X, Y) × weight 1

If there are four in a row: The median is motion M (X, Y) × weight 2

If there are three in a row: The median is motion M (X, Y) × weight 3

The motion determination unit 40 which adds weight to the motion detected by the above method divides the video screen into a plurality of blocks as described in FIG. 2 at step 80 and gives weight to the motion of the block. . Finally, the true motion vector of the moving image is determined by detecting the final motion amount as the largest value among the motion vectors to which the weighting is finally given.

Accordingly, it can be seen that the above-described configuration makes it possible to compare data of the previous screen with the current screen at high speed, and thus to achieve high speed of motion detection.

In the above-described embodiment, the case where the input image data is 1 bit is described. However, when the input image data is 8 bits, the above-described systems are connected in parallel to each other to detect motion for each bit. As a motion vector having a large amount of motion during motion, the state of the motion can be determined.

As described above, according to the present invention, the amount of motion can be detected at high speed by extracting a comparison result between the data of the previous screen and the data of the current screen at high speed by directly comparing contents with contents instead of position information using an associative memory. It becomes possible. As a result, correction of the video signal of the moving image, compression of the video signal, and the like can be performed more quickly.

From the above description, those skilled in the art will recognize that various changes and modifications can be made to the present invention without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the description of the detailed description but should be defined only by the claims.

Claims (5)

A register controller for converting and outputting serial image data inputted from outside by a shift output control signal in parallel and storing the output data from the register controller in an associative memory cell connected to an activated word line by a write signal; In response to the match control, compare the data stored in the internal bit storage with the output data from the register controller to decode the first and second associative memory cell arrays that generate a match result signal, and to decode the external address input thereto. An address controller for selecting one associative memory cell array among the second associative memory cell arrays and activating a word line corresponding to the address and a match result signal output from one of the first and second associative memory cells. Output registers stored in the storage area The shift output control signal is generated in response to the input of the image data in the canning area, the match signal is output, and the write signal and the external address are generated by the data input of the recording area in the scanning area, and stored in the output register. And a motion determining unit for detecting a motion vector by applying a weight according to a condition of the image data to the match result signal. The memory array of claim 1, wherein each of the first and second associative memory cell arrays comprises: write data lines for inputting first and second write data, and input data lines for inputting first and second input data, respectively; Bit storage having set and reset nodes and one node connected to the first and second write data lines, the other node connected to a word line, and the bit storage set in response to activation of the two input nodes. The set / reset output node and the first and second input data lines of the bit storage and the output node are connected in common and the set of the bit storage A match crab that generates a match signal by comparing a reset output and first and second input data signals input to the first and second input data lines, respectively. Teudeul and motion detection apparatus using an associative memory, characterized in that in response to the activation of the word line having a plurality of associative memory cells consisting of the data bits stored in the bit storage in an output gate for inverting the output. The motion detection apparatus of claim 2, wherein the bit storage is formed by connecting two NAND gates in the form of an R-S pull-up pull loop. In response to the input of the write control signal, the image data of the window area is recorded in a predetermined cell therein, and the match signal is generated by comparing the image data of the window area stored in the cell with the currently input image data by a match signal. A motion detection method comprising first and second associative memory cell arrays, comprising: image data located within a scanning area preset to a predetermined size on one screen to a first associative memory cell array storing image data of the window area; Searching for whether the currently input video data is data of a preset recording area; and supplying a match signal to a first associative memory cell array when the data is not data of the search result recording area. In response to the data being data in a preset recording area A matching operation of recording a second image memory cell array in which no window image data is stored, and supplying a match signal to the first associative memory cell array to an end point of the scanning area, and information on the match signal. Detecting a motion vector by applying a weight to the detected motion, and detecting a motion vector by using the associative memory. The method of claim 4, wherein the scanning area is divided into at least two areas on a single screen.