KR100208663B1 - Formatting apparatus for a camcorder - Google Patents

Abstract

Disclosed is a formatting apparatus of a camcorder for formatting digital image data converted from an image signal photographed by a camcorder into a state suitable for recording on a magnetic tape which is a recording medium. When the main controller applies a read signal to the SRAM controller, the SRAM controller applies a read signal to the SRAM switching unit. When the read signal is applied from the SRAM control unit, the SRAM switching unit reads data stored in the first SRAM memory unit and the second SRAM memory unit while being connected in a zigzag manner to the first SRAM memory unit and the second SRAM memory unit. The SRAM switching unit applies data applied from the first SRAM memory unit and the second SRAM memory unit to the packer through the delay unit, and the packer unit packs the applied data to the SMEM switching unit. The SMEM switching unit alternately stores data applied from the packer unit in a zigzag manner in the first SMEM memory unit and the second SMEM memory unit. The SMEM switching unit alternately reads data stored in the first SMEM memory unit and the second SMEM memory unit under the control of the SMEM controller, and applies the data to the error correcting encoder ECC through the SMEM controller.

Description

Formatting device of the camcorder

The present invention relates to a formatting apparatus of a camcorder, and more particularly, to a formatting apparatus of a camcorder for formatting digital image data converted from an image signal photographed by a camcorder into a state suitable for recording on a magnetic tape which is a recording medium. It is about.

In general, a camcorder is composed of a video camera and a VCR to record a video signal on a recording medium or to play back a video signal recorded on a recording medium, that is, a magnetic tape. do.

Conventional analog VSIs according to the standards of the conventional VHS and β have many problems in resolution, ease of editing, expansion into multimedia, and the like. As a result, the development of digital VSI was led by major consumer electronics companies.As a result, in 1994, about 50 companies around the world including Sony, Thomson, Philips, and MATSUSHIYA were formed in HD DIGITAL VCR CONFERENCE. Has approved the DIGITAL VCR standard and the DIGITAL VCR standard for HD BASEBAND.

Input processing for NTSC and PAL signals, which is the current broadcasting standard, follows CCIR601 standard. In other words, the signal input in 4: 2: 2 (Y: Cr: Cb) is decimated with respect to the color signal, which is 2: 1 in the horizontal direction for NTSC and 2: 2 in the vertical direction for PAL. Decimate to 1 In addition, shuffling is performed on data for one frame with respect to the luminance signal and the decimated color signal. Its purpose is to distribute the energy of the input signal evenly within the same frame so that the compressed data is fixed in a fixed amount without deterioration of image quality.

The shuffled signal is converted into values in the time domain by values of a discrete cosine transform (DCT) operator. At this time, there are two different deity modes, 8 × 8DCT and 4 × 8DCT. This selection is performed by motion detection. If the difference between two fields is large, 4x8DCT is selected, and if the difference between two fields is small, 8x8DCT is selected. The dectified signal is rearranged in the order of frequency components by zigzag scanning. The rearranged signal is quantized (Quantization) process to limit the amount of data to be transmitted within a predetermined size.

In this case, the loss of data can be prevented and the resolution can be prevented only by optimizing the quantization step. The quantized AC coefficient is converted into codes through RLC and RLC. The VLSI (hereinafter referred to as VLC) uses a modified two-dimensional Huffman code.

The video signal subjected to the above process is compressed to a data amount of about 5: 1 ratio. The compressed data is formatted into a predetermined amount of bits within a predetermined transmission unit and input to the error correction coding unit (ECC).

Disclosure of Invention An object of the present invention is to provide a formating apparatus for a camcorder which compresses digital data stored in an SRAM memory unit by quantization and VLC and stores the digital data in accordance with a video segment format and stores the digital data in an SMEM memory unit. To provide.

1 is a block diagram schematically illustrating a formatting apparatus according to an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings *

10: main controller 12: SRAM control unit

14: SRAM Switching Section 16: First SRAM Memory Section

18: second SRAM memory unit 20: VLC (VLC) unit

22: length signal conversion unit 24: delay unit

26: packer part 28: SMEM switching part

30: SMEM control unit 32: first SMEM memory unit

34: second SMEM memory section 38: iobi detection section

40: Error Correction Code (ECC) 42: QNO

In order to achieve the above object, the present invention, SRAM connected to the first SRAM memory unit and the second SRAM memory unit, and adjusts to read the data stored in the first SRAM memory unit and the second SRAM memory unit alternately Switching unit;

An SRAM control unit connected to the SRAM switching unit and adjusting the SRAM switching unit to perform a read operation;

A delay unit connected to the SRAM switching unit and delaying one cycle of data applied from the SRAM switching unit;

A length signal conversion unit connected to the SRAM switching unit and converting a length signal applied from the SRAM switching unit and applying the converted length signal to the delay unit;

A packer unit connected to the delay unit and packing valid data applied from the delay unit by 16 bits;

An IOB detecting unit connected to the SRAM switching unit and detecting an EOB signal from the SRAM switching unit;

A main controller connected to the SRAM control unit, a packer unit, and an IB detecting unit, and controlling an operation of formatting data applied from the first SRAM memory unit and the second SRAM memory unit;

An SMEM controller connected to the main controller and configured to read and write by a signal applied from the main controller; And

Connected to the SMEM control unit and the packer unit, and alternately writes data applied from the packer unit according to a signal applied from the SMEM control unit, or alternately writes the first SMEM memory unit and the second SMEM memory unit; Provided is a camcorder formatting apparatus comprising an SMEM switching unit for alternately reading data stored in an SMEM memory unit.

According to the present invention, first, when the main controller applies the read signal to the SRAM control unit, the SRAM control unit applies the read signal to the SRAM switching unit. When the read signal is applied from the SRAM control unit, the SRAM switching unit reads data stored in the first SRAM memory unit and the second SRAM memory unit while being connected in a zigzag manner to the first SRAM memory unit and the second SRAM memory unit.

The SRAM switching unit applies data applied from the first SRAM memory unit and the second SRAM memory unit to the packer through the delay unit, and the packer unit packs the applied data to the SMEM switching unit. The SMEM switching unit alternately stores data applied from the packer unit in a zigzag manner in the first SMEM memory unit and the second SMEM memory unit. The SMEM switching unit alternately reads data stored in the first SMEM memory unit and the second SMEM memory unit under the control of the SMEM controller, and applies the data to the error correcting encoder ECC through the SMEM controller.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention.

1 is a block diagram schematically illustrating a formatting apparatus according to an embodiment of the present invention.

Referring to FIG. 1, an SRAM is provided in a first SRAM memory unit 16 and a second SRAM memory unit 18 in which data compressed through a quantization process and a VLC unit 20 are stored. A switching unit 14 is connected, and an SRAM control unit 12, a delay unit 24, an EOB detecting unit 38, and a length signal conversion unit 22 are connected to the SRAM switching unit.

The main controller 10 is connected to the SRAM controller 12, and the SRAM controller 12 is controlled by a signal applied from the main controller 10 to operate the SRAM switching unit 14.

The SMEM controller 30 is connected to the main controller 10, and the SMEM controller 30 operates by a signal applied from the main controller 10.

An SMEM switching unit 28 is connected to the SMEM control unit 30, and a first SMEM memory unit 32 and a second SMEM memory unit 34 are connected to the SMEM switching unit 28.

An IOB detecting unit 38 is connected to the main controller 10, and an IOB detecting unit 38 is connected to an SRAM switching unit 14 and a 16-bit data signal and 4 bits outputted from the SRAM control unit 12. The length signal of is applied. The IOB detecting unit 38 detects the block termination signal EOB from the 16-bit data signal and the 4-bit length signal applied from the SRAM switching unit 14 and applies it to the main controller 10. The main controller 10 controls the operation of the packer unit 26 by receiving the block termination signal applied from the IOB detection unit 38.

A synchronous signal bypass unit 36 is connected to the main controller 10, the packer unit 26, the SRAM control unit 12, the SRAM switching unit 14, the SMEM control unit 30, and the SMEM switching unit 28. The synchronization signal bypass unit 36 properly bypasses the 2048 clock synchronization signal applied from the QNO unit 42 to the main controller 10, the packer unit 26, and the SRAM control unit 12. In addition, since the SRAM switching unit 14, the SMEM control unit 30 and the SMEM switching unit 28 are applied, all the operations are performed according to the synchronization signal.

In addition, the length signal converter 22 connected to the SRAM switching unit 14 converts the length signal applied from the SRAM switching unit 14 and applies it to the delay unit 24. The packer unit 26 is connected to the delay unit 24, and the packer unit 26 packs the data applied from the delay unit 24 to a predetermined size under the control of the main controller 10. It is applied to the connected SMEM switching unit 28. The SMEM switching unit 28 memorizes the data applied from the packer unit 26 to the first SMEM memory unit 32 and the second SMEM memory unit 34 in a zigzag manner. In addition, the SMEM switching unit 28 reads the data stored in each of the first SMEM memory unit 32 and the second SMEM memory unit 34 in a zigzag manner under the control of the SMEM control unit 30. Through the output to the error correction coder 40.

According to the present invention thus made, first, an image signal photographed by a video camera (not shown) is converted into digital image data, and the digital image data is quantized in a quantization unit by a number given in a QNO unit. The quantized digital image data is coded by the VLC 20 and is zigzagly stored in the first SRAM memory unit 16 and the second SRAM memory unit 18. That is, the data applied from the VLC 20 is stored in the first SRAM memory unit 16 during the 2048 clock synchronizing signal, and the data is stored in the second SRAM memory unit 18 when the next synchronizing signal is applied.

In addition, the main controller 10 applies an operation signal to the SRAM control unit 12, the SMEM control unit 30 and the packer unit 26, and at the same time the respective SRAM control unit 12, SMEM control unit 30 and packer unit 26 Information corresponding to the operation state is received. When the operation signal is applied from the main controller 10, the SRAM controller 12 applies a read signal to the SRAM switching unit 14, and the SRAM switching unit 14 receives a read signal from the SRAM controller 12. When the data stored in the first SRAM memory section 16 and the second SRAM memory section 18 are read in a zigzag manner.

That is, the SRAM switching unit 14 reads data stored in the second SRAM memory unit 18 when the first SRAM memory unit 16 receives data from the VLC 20 based on the synchronization signal and is in memory. When the next synchronization signal is applied, the VLC 20, which has stored data in the first SRAM memory unit 16, stores the data in the second SRAM memory unit 18, so that the SRAM switching unit 14 also simultaneously operates the first SRAM. The data stored in the memory unit 16 is read.

The data read by the SRAM switching unit 14 from the first SRAM memory unit 16 and the second SRAM memory unit 18 is composed of a 16-bit data signal and a 4-bit length signal. The 16-bit data signal is applied to the delay unit 24 and the 4-bit length signal is applied to the length signal converter 22. The length signal converter 22 converts a 4-bit length signal from the SRAM switching unit 14 into a 5-bit length signal and applies the delay signal to the delay unit 24. The data signal of 5 bits and the length signal of 5 bits are delayed by one cycle and applied to the packer section 26.

The packer unit 26 operates by a signal applied from the main controller 10, packs and formats valid data applied from the delay unit 24 by 16 bits, and applies the same to the SMEM switching unit 28. .

The SMEM switching unit 28 is the first SMEM memory unit 32 and the second SMEM memory unit (32) by a memory signal (write) applied from the packed data applied from the packer unit 26 from the SMEM control unit 30 ( 34) zigzag memory.

Since the memory capacities of the first SMEM memory section 32 and the second SMEM memory section 34 for storing data applied from the SMEM switching section 28 are 385 bytes, respectively, 1500 bytes of data are formatted and 385 bytes are stored. Will be memory.

In addition, the SMEM controller 30 applies a read signal to the SMEM switching unit 28 by a read operation signal applied from the main controller 10. The SMEM switching unit 28 stores the data applied from the packer unit 26 in the first SMEM memory unit 32 and the second SMEM memory unit 34 when a read signal from the SMEM control unit 30 is applied. In addition, a zigzag operation of reading data stored in the first SMEM memory section 32 and the second SMEM memory section 34 is executed.

That is, when the SMEM switching unit 28 operates by the synchronization signal to store data applied from the packer unit 26 in the first SMEM memory unit 32, the second SMEM memory unit 34 is simultaneously used. When the next synchronization signal is applied, the SMEM switching unit 28 stores the data applied from the packer unit 26 in the second SMEM memory unit 34 and at the same time the first SMEM memory unit 32. ) Reads the data memorized.

The SMEM switching unit 28 applies the data read from the first SMEM memory unit 32 and the second SMEM memory unit 34 to the error correction coder (ECC) 40 through the SMEM control unit 30.

As can be seen from the above description, in the present invention, when the main controller applies the read signal to the SRAM controller, the SRAM controller applies the read signal to the SRAM switching unit. When the read signal is applied from the SRAM control unit, the SRAM switching unit reads data stored in the first SRAM memory unit and the second SRAM memory unit while being connected in a zigzag manner to the first SRAM memory unit and the second SRAM memory unit.

The SRAM switching unit applies data applied from the first SRAM memory unit and the second SRAM memory unit to the packer through the delay unit, and the packer unit packs the applied data to the SMEM switching unit. The SMEM switching unit alternately stores data applied from the packer unit in a zigzag manner in the first SMEM memory unit and the second SMEM memory unit. The SMEM switching unit alternately reads data stored in the first SMEM memory unit and the second SMEM memory unit under the control of the SMEM controller, and applies the data to the error correcting encoder ECC through the SMEM controller.

Although the present invention has been described in detail with reference to the accompanying drawings, it is apparent to those skilled in the art that the present invention is not limited thereto and various modifications are possible within the ordinary knowledge of those skilled in the art.

Claims (8)

An SRAM switching unit 14 connected to the first SRAM memory unit 16 and the second SRAM memory unit 18 and reading data stored in the first SRAM memory unit 16 and the second SRAM memory unit 18. ); An SRAM control unit (12) connected to the SRAM switching unit (14), which controls the SRAM switching unit (14) to perform a read operation; A delay unit 24 connected to the SRAM switching unit 14 for delaying one cycle of data applied from the SRAM switching unit 14; A length signal conversion section 22 connected to the SRAM switching section 14 for converting a length signal applied from the SRAM switching section 14 and applying it to a delay section; A packer unit 26 connected to the delay unit 24 for packing valid data applied from the delay unit 24; An obi detection unit (38) connected to the SRAM switching unit (14) for sensing an EOB signal from the SRAM switching unit (14); Connected to the SRAM control unit 12, the packer unit 26, and the OBI detecting unit 38, and the operation of formatting data applied from the first SRAM memory unit 16 and the second SRAM memory unit 18 is performed. A main controller 10 for controlling; An SMEM controller 30 connected to the main controller 10 and outputting a read and write operation signal by a signal applied from the main controller 10; And The first SMEM memory unit 32 and the second SMEM are connected to the SMEM control unit 30 and the packer unit 26, and the data applied from the packer unit 26 according to a signal applied from the SMEM control unit 30. Formatting apparatus of a camcorder comprising an SMEM switching unit 28 for writing to the memory unit 34 or reading data stored in the first SMEM memory unit 32 and the second SMEM memory unit 34. The method of claim 1, wherein the SRAM switching unit 14 alternately reads data stored in the first SRAM memory unit 16 and the second SRAM memory unit 18 every time a synchronization signal is applied. Formatting device of the camcorder. The camcorder according to claim 1, wherein the SRAM switching unit 14 applies a 16-bit data signal to the delay unit 24 and a 4-bit length signal to the length signal converter 22. Formatting device. The camcorder of claim 1, wherein the length signal converter 22 converts a 4-bit length signal into a 5-bit length signal and applies the delay signal to the delay unit 24 and the main controller 10. Device. The apparatus of claim 1, wherein the packer unit packs and formats data applied from the delay unit (24 bits) by 16 bits. The memory of claim 1, wherein the SMEM switching unit 28 stores the data applied from the packer unit 26 in the first SMEM memory unit 32 while one synchronization signal is applied, and simultaneously the second SMEM memory unit ( Read the data stored in 34) and apply it to the SMEM control unit 30, and when the next synchronization signal is applied, it is switched to store the data applied from the packer unit 26 in the second SMEM memory unit 34, and the first SMEM. And a zigzag operation for reading data stored in the memory section (32) and applying it to the SMEM control section (30). 7. The apparatus of claim 1 or 6, wherein the synchronization signal is 2048 clocks. 2. The apparatus as claimed in claim 1, wherein the memory capacities of the first SMEM memory section (32) and the second SMEM memory section (34) are 385 bytes, respectively.