KR100208664B1 - Deformatting apparatus for a camcorder - Google Patents

Abstract

Disclosed is a deformatting apparatus for a camcorder for deformatting digital image data recorded by a camcorder and formatted and recorded on a magnetic tape, which is a recording medium, on a screen. When data and a synchronization signal are applied from the error correction encoder to the SM controller, the SM controller stores the first SM memory unit and the second SM memory unit through the SM switching unit, and then applies the depacker unit through the filter unit. The depacker unit depacks the data according to the size of a predetermined bit and applies the filtered valid data to the VDL unit and the code length generator. The VDL unit calculates the run value and the amplifier value from the applied data and applies data corresponding to the calculated run value and the amplifier value to the SR switching unit, and the SR switching unit applies the first SR memory by a memory signal applied from the SR control unit. Memory in the second and second SR memory sections. The data stored in the first SR memory unit and the second SR memory unit are output to CRT through an inverse quantization unit to display an image.

Description

Deformatting device of the camcorder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a deformatting apparatus of a camcorder, and more particularly, to a deformatting apparatus of a camcorder for formatting digital image data recorded and recorded on a magnetic tape, such as a recording medium, for display on a screen. It is about.

In general, a camcorder is composed of a video camera and a VCR to record a video signal on a recording medium or to reproduce a video signal recorded on a recording medium, that is, a magnetic tape. do.

Conventional analog VSIs according to the conventional VHS and β standards have many problems in resolution, ease of editing, expansion into multimedia, and the like. As a result, the development of digital VSI was led by major consumer electronics companies.As a result, in 1994, about 50 companies around the world including Sony, Thomson, Philips and MATSUSHIYA were formed in HD DIGITAL VCR CONFERENCE. According to the approval of DIGITAL VCR standard and DIGITAL VCR standard for HD BASEBAND, it has been confirmed as the global standard.

Input processing for NTSC and PAL signals, which is the current broadcasting standard, follows CCIR601 standard. In other words, the signal input in 4: 2: 2 (Y: Cr: Cb) is decimated with respect to the color signal, which is 2: 1 in the horizontal direction for NTSC and 2: 2 in the vertical direction for PAL. Decimate to 1 In addition, shuffling is performed on data of one frame with respect to the luminance signal and the decimated color signal. Its purpose is to distribute the energy of the input signal evenly within the same frame so that the compressed data is fixed in a fixed amount without deterioration of image quality.

The shuffled signal is converted into values in the time domain by values of a discrete cosine transform (DCT) operator. At this time, there are two different deity modes, 8 × 8DCT and 4 × 8DCT. This selection is performed by motion detection. If the difference between two fields is large, 4x8DCT is selected, and if the difference between two fields is small, 8x8DCT is selected. The dectified signal is rearranged in the order of frequency components by zigzag scanning. The rearranged signal is quantized to limit the amount of data to be transmitted within a predetermined size.

In this case, the loss of data can be prevented and the resolution can be prevented only by optimizing the quantization step. The quantized AC coefficient is converted into codes through RLC and RLC. The VLSI (hereinafter referred to as VLC) uses a modified two-dimensional Huffman code.

The video signal subjected to the above process has a data amount compressed at a ratio of about 5: 1. The compressed data is formatted into a predetermined amount of bits within a predetermined transmission unit and input to the error correction coding unit (ECC).

The error correction encoding unit corrects an error of data generated in the process of recording the formatted and applied digital image data on a recording medium and reproducing the recorded data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a deformatting apparatus for a camcorder which deformats digital data to which an error is corrected and applied through an error correction encoding unit to reproduce digital image data stored in a recording medium and stores the digital data in an SRAM memory unit. To provide.

1 is a block diagram schematically illustrating a deformatting apparatus according to an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings *

10: main de facto control unit 12: SM control unit

14: SM switching unit 16: second SM memory unit

18: first SM memory unit 20: filter unit

22: depacker part 24: VDL

26: code length generating unit 28: SR control unit

30: SR switching part 32: first SR memory part

34: second SR memory section 36: inverse quantization section

38: error correction coder (ECC) 40: synchronization signal bypass unit

In order to achieve the above object, the present invention is connected to the first SM memory unit and the second SM memory unit, the first SM memory unit and the second SM memory unit to store the data or read the stored data SM switching unit;

The SM switching unit is connected to the error correction coding unit (ECC), and the SM switching unit stores the data applied from the error correction coding unit in the first SM memory unit and the second SM memory unit or the SM switching unit is stored. An SM controller which applies a signal to the SM switching unit for reading data;

A filter unit connected to the SM switching unit and filtering out data applied from the SM switching unit to remove invalid data;

A depacker unit connected to the filter unit and depacking and outputting data of a predetermined size while continuously attaching only valid data from the data applied from the filter unit;

A VLD unit connected to the depacker unit and configured to determine a run and amp value from data applied from the depacker unit and to output corresponding data;

An SR switching unit connected to the VDL unit and storing data applied from the VDL unit into a first SR memory unit and a second SR memory unit;

An SR control unit connected to the SR switching unit and configured to apply a signal to the SR switching unit to perform a memory function;

A main defactor control unit connected to the SM control unit, the SR control unit, and the depacker unit and configured to apply an operation signal to the SM control unit, the SR control unit, and the depacker unit, respectively;

A code length generation unit connected to the depacker unit and obtaining information on a code length from data applied from the depacker unit and applying the code length to the depacker unit and the VDL unit through a main defactor control unit; And

A synchronization signal bypass unit connected to the error correction encoding unit and bypassing the synchronization signal applied from the error correction encoding unit to be applied to the SR control unit, the depacker unit, the SR switching unit, the VDL unit, and the main defactoring unit. Provides a deformatting device for a camcorder.

According to the present invention, first, when data and a synchronization signal are applied from the error correction encoder to the SM controller, the SM controller stores the first SM memory unit and the second SM memory unit through the SM switching unit, and then depacker unit through the filter unit. To apply. The depacker unit depacks the data according to the size of a predetermined bit and applies the filtered valid data to the VDL unit and the code length generator. The VDL unit calculates the run value and the amplifier value from the applied data and applies data corresponding to the calculated run value and the amplifier value to the SR switching unit, and the SR switching unit applies the first SR memory by a memory signal applied from the SR control unit. Memory in the second and second SR memory sections. The data stored in the first SR memory unit and the second SR memory unit are output to CRT through an inverse quantization unit to display an image.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention.

1 is a block diagram schematically illustrating a deformatting apparatus according to an embodiment of the present invention.

Referring to FIG. 1, an SM controller 12 is connected to an error correction encoder 38, and an SM switch unit 14, a filter unit 20, and a main factor control unit are connected to the SM controller 12. 10) is connected.

The SM switching unit 14 is connected to a first SM memory unit 18 and a second SM memory unit 16. The SM switching unit 14 is a first SM memory unit 18 and a second SM memory. The unit 16 stores data or reads the stored data. In addition, a filter unit 20 is connected to the SM switching unit 14, and the SM switching unit 14 filters data read from the first SM memory unit 18 and the second SM memory unit 16. Is applied to (20). The filter unit 20 filters the data applied from the SM switching unit 14 to remove invalid data.

The depacker unit 22 is connected to the filter unit 20, and the depacker unit 22 depacks the data into a predetermined size while continuously attaching only valid data from the data applied from the filter unit 20. And print it out.

A VDL unit 24 is connected to the depacker unit 22, and the VDL unit 24 determines the run value and the amplifier value from the data applied from the depacker unit and then corresponds to the determined run value and the amplifier value. Outputs

The SR switching unit 30 is connected to the VDL unit 24, and the SR switching unit 30 transfers data applied from the VDL unit 24 to the first SR memory unit 32 and the second SR memory. The section 34 is stored in memory.

An SR control unit 28 is connected to the SR switching unit 30, and the SR control unit 28 is configured by the SR switching unit 30 to transmit data to the first SR memory unit 32 and the second SR memory unit 34. A signal is applied to perform a memory function for memory.

The main control unit 10 is connected to the SM control unit 12, the SR control unit 28, and the depacker unit 22, and the main defactor control unit 10 includes the SM control unit 12 and the SR control unit 28. ) And the depacker unit 22 apply an operation signal.

In addition, a code length generating unit 26 is connected to the depacker unit 22, and the code length generating unit 26 obtains information on a code length from data applied from the depacker unit 22 and maintains the main unit. The length signal is applied to the depacker unit 22 and the VDL unit 24 through the factor control unit 10.

In addition, a synchronization signal bypass unit 40 is connected to the error correction encoding unit 38, and the synchronization signal bypass unit 40 bypasses a synchronization signal applied from the error correction encoding unit 38 to SR. The control unit 28, the depacker unit 22, the SR switching unit 30, the VDL unit 24, and the main defactor control unit 10 are applied to the control unit 10.

According to the present invention, the digital image data stored in a recording medium such as a magnetic tape (not shown) in the recording step is applied to the error correction encoding unit 38 when the reproduction step is performed. If an error occurs in the data, the error correction encoder 38 corrects it and applies it to the SM controller 12 together with the synchronization signal SYNC.

In this case, the sync signal SYNC is 2048 clock, and is applied to the SM controller 12, the SM switching unit and the sync signal bypass unit 40, and the sync signal bypass unit 40 is an error correction encoder. The synchronization signal applied from (38) is bypassed and applied to the depacker section 22, the VDL section 24, the SR switching section 30, the SR control section 28, and the main defactoring section 10.

The SM controller 12 applies the data applied from the error correction encoding unit 38 to the SM switching unit 14, and the SM switching unit 14 transmits the data applied from the SM controller 12 to the first SM. The memory unit 18 and the second SM memory unit 16 are stored in a zigzag fashion.

When the SM switching unit 14 stores data in the first SM memory unit 18 during one synchronization signal, the SM controller 12 controls the SM switching unit 14 to simultaneously supply the second SM memory unit 16 to the second SM memory unit 16. The memorized data is read and applied to the filter unit 20. At this time, when the applied synchronization signal is changed to the next synchronization signal, the SM switching unit 14 is switched to store data in the second SM memory unit 16 and simultaneously read data stored in the first SM memory unit 18. It is applied to the filter unit 20.

The filter unit 20 filters out an invalid part corresponding to noise generated in the re-memorized data having less than 16 bits among the data stored in the first SM memory unit 18 or the second SM memory unit 16. After removing it, it is applied to the depacker unit 22.

For example, the remaining residual data depacked by the depacker unit 22 is re-memorized in the first SM memory unit 18 or the second SM memory unit 16 through the SM switching unit 14. The re-memory data is read by the control of the SM control unit 12 and applied to the filter unit 20 via the SM switching unit 14. The filter unit 20 removes the bit more than the corresponding length by the length signal applied from the SM control unit 12 and removes the residual data applied from the SM switching unit 14 and only the data of the bit corresponding to the corresponding length of the depacker unit. Is applied to (22). That is, if the length signal applied from the SM controller 12 to the filter unit 20 is 4 bits, at least 4 bits are zeroed and removed from the residual data applied from the SM switching unit 14, and the 4-bit data is removed. Only the depacker unit 22 is applied.

The depacker unit 22 depacks the data applied from the filter unit 20 to a size between 16 bits and 3 bits, and applies the depacker unit 22 to the VDL unit 24. The size of data depacking the data applied by the depacker unit 22 from the filter unit 20 is between 16 bits and 3 bits, which is 16 bits to 3 bits, which is the size of data depacking the data. Is determined by the length signal applied from the code length generator 26. That is, if the length of data applied to the depacker unit 22 in the code length generator 26 is 5 bits, the depacker unit 22 depacks only 5 bits from the data applied from the filter unit 20. If the length signal applied from the code length generation unit 26 is 16 bits, the depacker unit 22 continuously connects the data applied from the filter unit 20 to the output. If the bit is greater than or equal to 16 bits, the packet is depacked into 16 bits and output to the VDL unit 24. In addition, the depacker unit 22 remains after depacking the data applied from the filter unit 20 under the control of the main defactor control unit 10 according to the length signal applied from the code length generator 26. The remaining data is stored in the first SM memory unit 18 or the second SM memory unit 16 through the SM switching unit 14, and the first SM memory unit 18 or the second switching unit 14 is stored in the first SM memory unit 18. The length signal of the remaining data stored in the second SM memory unit 16 is applied to the SM controller 12 and the main defactor controller 10.

At this time, the length signal applied to the VDL unit 24, the depacker unit 22 and the main defactor control unit 10 by the code length generation unit 26 is formed of a plurality of applied from the depacker unit 22. It is obtained from any number of bits on the MSB side corresponding to the left side of the bits of data.

The VDL unit 24 determines the run value and the amplifier value based on the number of bits constituting the depacked data applied from the depacker unit 22 and the bit values of arbitrary positions among the bits constituting the data. Will be decided.

For example, if the data applied from the depacker unit 22 to the VDL unit 24 is 1101 1010, the number of bits becomes 8, and thus the sixth bit value when the number of bits is 8 The rule that should occur is set in the VDL 24. Accordingly, when the data applied from the depacker unit 22 is 1101 1010, the number of bits constituting the data is 8, and the sixth bit value corresponds to 0, so that the run value and the amplifier value are (5). , 1). In the above (5, 1), if the number of bits of data applied from the depacker unit 22 to the VDL unit 24 is 8 and the sixth bit value is 0, the rule to determine (5, 1) is the VDL unit ( 24).

The VDL unit 24 converts the run value and the amplifier value obtained by the number of bits and bit values of the data applied from the depacker unit 22 into 16-bit data and applies them to the SR switching unit 30.

The SR switching unit 30 applies the data applied from the VDL unit 24 to the first SR memory unit 32 and the second SR memory unit 34 by the memory signal of the SR control unit 28. That is, the SR switching unit 30 causes the memory unit to be stored in any one of the first SR memory unit 32 or the second SR memory unit 34 during one synchronization signal by a memory signal applied from the SR control unit 28. . For example, when data is stored in the first SR memory unit 32, the data is switched immediately when the next synchronization signal is applied to cause the second SR memory unit 34 to store data.

The data stored in the first SR memory unit 32 and the second SR memory unit 34 through the SR switching unit 30 is applied to the DCT operator through the dequantization unit and then displayed on the CRT.

As can be seen from the above description, when the data and the synchronization signal are applied to the SM controller from the error correction coding unit, the SM controller stores the first SM memory unit and the second SM memory unit through the SM switching unit and then filters the filter. It is applied to the packer part through the part. The depacker unit depacks the data according to the size of a predetermined bit and applies the filtered valid data to the VDL unit and the code length generator. The VDL unit calculates the run value and the amplifier value from the applied data and applies data corresponding to the calculated run value and the amplifier value to the SR switching unit, and the SR switching unit applies the first SR memory by a memory signal applied from the SR control unit. Memory in the second and second SR memory sections. The data stored in the first SR memory unit and the second SR memory unit are output to the SRT through the inverse quantization unit 36 to display an image.

Although the present invention has been described in detail with reference to the accompanying drawings, it is apparent to those skilled in the art that the present invention is not limited thereto and various modifications are possible within the ordinary knowledge of those skilled in the art.

Claims (10)

The first SM memory unit 18 and the second SM memory unit 16 are connected to the first SM memory unit 18 and the second SM memory unit 16 to store data or to store the stored data. An SM switching unit 14 for reading; The SM switching unit 14 is connected to the SM switching unit 14 and the error correction encoding unit 38, and the SM switching unit 14 receives data applied from the error correction encoding unit 38. An SM control unit 12 for storing a memory in the SM memory unit 16 or for applying a signal to the SM switching unit 14 so that the SM switching unit 14 reads the stored data; A filter unit 20 connected to the SM switching unit 14 to filter out data applied from the SM switching unit 14 to remove invalid data; A depacker unit 22 connected to the filter unit 20 for depacking and outputting data of a predetermined size while continuously attaching only valid data from the data applied from the filter unit 20; A VDL unit 24 connected to the depacker unit 22 for determining a run value and an amplifier value from data applied from the depacker unit 22 and outputting the corresponding data; An SR switching unit (30) connected to the VDL unit (24) for storing data applied from the VDL unit (24) in the first SR memory unit (32) and the second SR memory unit (34); An SR control unit 28 connected to the SR switching unit 30 and applying a signal to the SR switching unit 30 to perform a memory function; The main controller is connected to the SM controller 12, the SR controller 28, and the depacker 22, and applies a main operation signal to the SM controller 12, the SR controller 28, and the depacker 22, respectively. Defactor control unit 10; It is connected to the depacker unit 22, and obtains information about the code length from the data applied from the depacker unit 22, through the main defactor control unit 10 through the depacker unit 22 and VDL unit ( A code length generator 26 for applying to 24; And The SR control unit 28, the depacker unit 22, the SR switching unit 30, and V are connected to the error correction encoding unit 38 and bypass the synchronization signal applied from the error correction encoding unit 38. A deformatting apparatus for a camcorder, comprising a synchronization signal bypass unit (40) applied to an LCD unit (24) and a main defactor control unit (10). 2. The SM switch of claim 1, wherein the SM switching unit 14 is switched every time a synchronization signal is applied to store data in the first SM memory unit 18 and the second SM memory unit 16, and simultaneously the first SM. A deformatting apparatus for a camcorder, characterized by reading data stored in the memory section (18) and the second SM memory section (16). 3. The SM switching unit (14) according to claim 2, wherein the SM switching unit (14) has a function of storing the first SM memory unit (18) and the second SM memory unit (16) and the first SM memory unit (18) and the second SM memory unit (4). A deformatting apparatus for a camcorder, characterized in that a function of reading data stored in (16) is performed in a zigzag manner. The SM switching unit 14 stores the residual data applied from the depacker unit 22 in the first SM memory unit 18 and the second SM memory unit 16, and stores the first SM. And the remaining data stored in the memory unit (18) and the second SM memory unit (16) is read and applied to the filter unit (20). The apparatus of claim 1, wherein the filter unit (20) filters the residual data applied from the SM switching unit (14) according to the length signal applied from the SM control unit (12). The depacker unit 22 applies the residual data after depacking to the SM switching unit 14 so as to be stored in memory. The number of bits of the residual data is stored in the SM controller 12 and the main defactor. Apparatus for formatting the camcorder, characterized in that applied to the control unit (10). 2. The VD unit 24 determines the run value and the amplifier value according to the number of bits constituting the data applied from the depacker unit 22 and the bit values constituting the data. Deformatting device for the camcorder. 2. The code length generating section (26) according to claim 1, wherein the code length generating section (26) determines the length signal by an arbitrary number of bit values on the MSB side corresponding to the left side of the bits constituting the data generated from the depacker section (22). A deformatting device of a camcorder, characterized in that. 2. The SR switching unit 30 according to claim 1, wherein the SR switching unit 30 stores the data applied from the VDL unit 24 in the first SR memory unit 32 while one synchronization signal is applied, and the next synchronization signal is applied. And is switched to perform a zigzag operation in which the second SR memory unit 34 stores data applied from the VDL unit 24 in a zigzag manner. 10. The apparatus of claim 9, wherein the synchronization signal is 2048 clocks.