KR100208285B1 - Apparatus for transmission and reception of async hdlc - Google Patents

Abstract

The present invention relates to asynchronous high-level Data Link Control (HDLC) data transmission and reception using a CEPT (Conference Europeenne des Administation des Postes et Telecommunication) relay line, and particularly, when transmitting and receiving IPC data in the HDLC format between a host and a local station in an all-electronic switch. By transmitting and receiving HDLC type IPC data using a completely different clock source between the system clock and the IPC clock, IPC communication through the CEPT channel is possible if only the HDLC serial communication port of the general control processor is provided without special IPC hardware. There is no need for special hardware or hardware dedicated to IPC data transmission and reception, thus reducing the amount of hardware, thereby saving the associated hardware costs.

Description

Asynchronous High Level Data Link Control (HDLC) Data Transceiver

The present invention relates to asynchronous high-level data link control (HDLC) data transmission and reception using a communication Europeenne des Administation des Postes et Telecommunication (CEPT) relay line, and more particularly, to an IPC (Inter-Processor Communication) processor between a host and a host of an electronic switching center. Inter-communication) relates to an asynchronous HDLC data transmitting / receiving apparatus which transmits / receives data in an asynchronous manner regardless of system clock / transmission.

In the conventional synchronous HDLC data transmission / reception apparatus using the CEPT transmission line, as shown in FIG. 1, the control unit 15 controls the overall operation of data transmission and reception, and a subhighway of 2.048 Mbps transmitted from a time switch on the exchange system side. A time switch for receiving only SHW data and switching only the voice channel to the relay line framer and the line matching unit 14 under the control of the control unit 15. 10) Receives clocks of 4.096Mhz and 8Khz transmitted from the system side time switch, generates clocks for data transmission and reception, and provides RXDATA and RXCLK from the IPC side of the system. The first rate converter 12 converts the RXDATA into a SHW data type of 2.048 MHz using the clock provided by the clock generator 11 and transmits the converted time to the time switch 10. A second rate converter 13 which extracts only a channel carrying IPC data from the SHW data output from the switch 10 and then transmits TXDATA to the IPC in accordance with TXCLK using a clock provided by the clock generator 11, and SHW data and IPC data inputted from the time switch 10 are converted into a PCM (Pulse Code Modulation) form by a clock provided by the clock generator 11 and transmitted to a PCM line or inversely converted to data received on a PCM line. And a relay line framer and a line matching section 14 output to the time switch 10.

Here, the reception clock RXCLK and the transmission clock TXCLK are system clocks (RXCLK = TXCLK = system clock).

The time switch 10 of FIG. 1 configured as described above receives the 2.048 Mbps SHW data transmitted from the time switch on the exchange system side, and under the control of the controller 15, only the voice channel except the channel on which the HDLC IPC data is carried is relay line framer. And line matching unit 14.

That is, the control unit 15 controls the time switch 10 to switch the SHW data on the system side to the relay line framer and the line matching unit 14.

In addition, the time switch 10 switches the 2.048 Mbps IPC data input through the first rate converter 12 to the IPC data area of the SHW data and transmits the IPC data to the relay line framer and the line matching unit 14.

At this time, the clock generator 11 receives the 4.096Mhz and 8Khz clock transmitted from the time switch of the system side to generate various clocks necessary for data transmission and reception, the time switch 10, the first, second rate converter 12 And 13) to the relay line framer and the line matching section 14.

The first rate converter 12 receives the data RXDATA and the clock RXCLK from the IPC side of the system and then uses the clock provided by the clock generator 11 to receive the received data RXDATA of 2.048 Mbps. The data is converted into SHW data format and transmitted to the time switch 10.

The second rate converter 13 extracts only the channel containing the IPC data from the SHW data output from the time switch 10 and then extracts the extracted data TXDATA using the clock provided by the clock generator 11. Transmit to IPC according to system clock TXCLK.

In addition, the relay line framer and line matching unit 14 converts the SHW data and the IPC data input from the time switch 10 into the PCM form according to the clock provided by the clock generator 11 and transmits the data to the PCM line. The channel data sequence of 2.048Mbps received through the PCM line is inversely converted and output to the time switch 10.

However, in the conventional synchronous HDLC data transmission / reception apparatus using the CEPT transmission path, the IPC side needs to be structured to receive the system clock necessary for data transmission and reception in transmitting and receiving HDLC IPC data synchronized with the system clock. The hardware configuration of the page should be structured to transmit and receive only one IPC data. Therefore, there is a problem in that the hardware is increased, thereby increasing the cost.

The present invention is to solve the above problems, an object of the present invention is to transmit and receive data in an asynchronous manner regardless of the system clock when transmitting and receiving IPC data between the host and the host of the electronic switchboard, thereby reducing the amount of hardware and cost An asynchronous HDLC data transmission / reception apparatus using a reduced CEPT transmission channel is provided.

Features of the asynchronous HDLC data transmission and reception apparatus according to the present invention for achieving the above object, the control unit for controlling the overall operation of data transmission and reception, and the control of the control unit by receiving the SHW data transmitted from the time switch on the exchange system side Time switch for switching only the voice channel to the relay line framer and line matching unit except for the channel carrying HDLC IPC data, and receiving the clock of the predetermined frequency transmitted from the system side time switch to generate various clocks necessary for data transmission and reception. A clock generator that provides the data, a transmission memory that stores only pure HDLC data among the data coming from the IPC side of the system, receives data from the IPC side of the system, extracts only the HDLC data, and writes the data to the transmission memory. After that, the data in the transmission memory is read A first rate converter for transmitting to the trunk line framer and line matching unit, a reception memory for storing only pure HDLC data in a channel data sequence inputted from the relay line framer and line matching unit, and the relay line framer and line matching unit A second rate converter which extracts pure HDLC-type IPC data from the channel data sequence of a predetermined frequency and writes it to the receiving memory, and then reads the data in the receiving memory and transmits the data to the IPC in synchronization with a system clock; The SHW data input from the time switch and the IPC data input from the transmission memory are converted into a PCM form by a clock provided by a clock generator to be transmitted to the PCM line or the data received from the PMC line is reversed. And a relay line framer transmitting the second rate converter. It is a point including a line matching part.

1 is a block diagram showing a synchronous HDLC data transmission and reception apparatus using a conventional CEPT transmission line.

2 is a block diagram showing a synchronous HDLC data transmission and reception apparatus using a CEPT transmission line according to the present invention.

* Explanation of symbols for main parts of the drawings

20: time switch 21: clock generator

22: first rate converter 23: second rate converter

24: relay line framer and line matching unit 25: control unit

26: transmission memory 27: reception memory

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an asynchronous HDLC data transmission and reception apparatus using a CEPT transmission line according to the present invention. The control unit 25 controls the overall operation of data transmission and reception, and SH96 data of 4.096 Mbps transmitted from a time switch on the exchange system side. 16.384 transmitted from the time switch 20 and the system side switch to switch only the voice channel to the relay line framer and the line matching unit 24 under the control of the control unit 25, except for the channel carrying the HDLC IPC data. Receiving clocks of Mhz and 8Khz and generating various clocks necessary for data transmission and reception, the clock generator 21 provides each part and transmit memory (TX) that stores only HDLC data among the data (RXDATA) coming from the IPC side of the system (TX FIFO) (26), data from the IPC side of the system (RXDATA), clock (RXCLK), FS (8Khz) after receiving only the data in HDLC format from the received data (RXDATA) Writes to the transmission memory 26, reads the data from the transmission memory 26, synchronizes it with the system clock, and transfers the data to the relay line framer and the line matching unit 24, and transmits the data according to the state of the transmission memory 26. Receiving memory (RX FIFO) 27 which stores only pure HDLC-type IPC data in the channel data sequence input from the first rate converter 22, the relay line framer and the line matcher 24, which controls the read of the circuit 26. ), IPC data in the form of pure HDLC is extracted from the 2.048 Mbps channel data sequence input from the relay line framer and the line matching unit 24 to the 2.048 Mhz clock provided by the clock generator 21 and written to the receiving memory 27. After receiving FS (8Khz), data (RXDATA), and clock (RXCLK) from the IPC side of the system, read the data in the receiving memory 27 and synchronize read data TXDATA with the system clock (RXCLK). Sending to the IPC The second rate converter 23 controls the read of the reception memory 27 according to the state of the reception memory 27, and the SHW data and the IPC data input from the time switch 20 are clock generators 21. It consists of a relay line framer and a line matching section 24 for converting the data to the PCM form by the clock provided by the reference) and inverting the data received on the PCM line.

Here, the reception clock RXCLK is a system clock, and the transmission memory 26 and the reception memory 27 are memories having a first input first output (FIFO) function.

The time switch 20 according to the present invention configured as described above receives only 4.096 Mbps SHW data transmitted from the time switch on the exchange system side, and according to the control of the controller 25, only the voice channel except the channel on which the HDLC IPC data is carried is relayed. Switch to framer and line matcher 24.

That is, the control unit 25 controls the time switch 20 to switch the SHW data on the system side to the relay line framer and the line matching unit 14.

At this time, the clock generation unit 21 receives the 16.3846Mhz and 8Khz clock transmitted from the time switch of the system side to generate various clocks necessary for data transmission and reception, the time switch 20, the first, second rate converter 22 And 23) and to the trunk line framer and line matching unit 24.

The first rate converter 22 receives the data RXDATA, the clock RXCLK, and the FS (8Khz) from the IPC side of the system, and then inputs the data RXDATA, that is, the FS and RXCLK from the HDLC type IPC data. Is used to extract only pure HDLC format data and write it to the transmission memory 26.

When all one HDLC frame is written to the transmission memory 26, the first rate converter 22 reads the data written to the transmission memory 26 and provides the system 2.048Mhz provided by the clock generator 21. It synchronizes with a clock and transmits it to the trunk line framer and the line matching part 24. FIG.

If there is no data in the transmission memory 26, the first rate converter 22 stops reading data from the transmission memory 26, and the hexadecimal 'FF' data is a relay line framer and a line matching unit. Control to be transmitted to (24).

On the other hand, the second rate converter 23 is a system 2.048Mhz that provides the IPC data of the pure HDLC form in the clock generator 21 in the 2.048Mbps channel data sequence input from the relay line framer and line matching unit 24 The clock is extracted and written to the reception memory 27.

Then, the second rate converter 23 receives the FS (8Khz) and the clock RXCLK coming from the IPC side of the system, reads the data TXDATA in the receiving memory 27, and synchronizes the FS and RXCLK. Send to the IPC side of the system.

In addition, when there is no data in the reception memory 27, the second rate converter 23 stops data reading of the reception memory 27 so that the Hex 'FF' data is transmitted to the IPC side of the system.

Thus, by using a completely different clock source between the system clock and the IPC clock, it is possible to send and receive IPLC data in HDLC format.

On the other hand, the relay line framer and line matching unit 24 is a PCM type of the SHW data input from the time switch 20 and the IPC data input from the transmission memory 26 in accordance with the clock provided by the clock generator 21. The channel data sequence of 2.048 Mbps received by the PCM line or transmitted to the PCM line is inversely converted and outputted to the time switch 20 and the second rate converter 23.

As described above, according to the HDLC data transmitting / receiving apparatus using the CEPT transmission channel according to the present invention, when transmitting / receiving HDLC format IPC data between the host and the local station in an all-electronic exchange, a completely different clock source is used between the system clock and the IPC clock. By transmitting / receiving IPLC data in the form of HDLC, IPC communication through the CEPT channel is possible if only the HDLC serial communication port of the general control processor is provided without special IPC hardware, thereby eliminating the need for special hardware configuring the IPC side or dedicated hardware for transmitting and receiving IPC data. Therefore, the amount of hardware is reduced, thereby saving the associated hardware cost.

Although the present invention has been described as the above-described embodiment, those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A controller for controlling the overall operation of data transmission and reception; After receiving the sub-highway (SHW) data transmitted from the time switch on the exchange system side, only the voice channel except for the channel on which the high-level data link control (HDLC) inter-processor communication (IPC) data is carried under the control of the controller A time switch for switching to the framer and line matcher; A clock generator for receiving a clock of a predetermined frequency transmitted from a system side time switch and generating various clocks necessary for data transmission and reception to each unit; A transmission memory for storing only data in the form of pure HDLC among data coming from the IPC side of the system; A first rate converter which receives data from the IPC side of the system, extracts only HDLC data, writes the data to the transmission memory, and then reads the data from the transmission memory and transmits the data to the relay line framer and the line matching unit; Receiving memory for storing only the IPC data of the pure HDLC type in the channel data sequence input from the relay line framer and line matching unit, and IPC data of the pure HDLC form of the channel data sequence of a predetermined frequency input from the relay line framer and line matching unit A second rate converter which extracts and writes the data to the receiving memory, and then reads the data in the receiving memory and transmits the data to the IPC in synchronization with a system clock; SHW data inputted from the time switch and IPC data inputted from the transmission memory are converted into pulse code modulation (PCM) form by a clock provided by a clock generator to be transmitted to a PCM line or inversely converted to data received on a PCM line. And a relay line framer and a line matcher to transmit the time switch and the second rate converter. 2. The asynchronous high level data link control data transmission / reception apparatus according to claim 1, wherein the transmission memory is a memory having a first-in first-out function. The method of claim 1, wherein the first rate converter extracts only pure HDLC format data from the HDLC type IPC data transmitted from the IPC side of the system using FS (8Khz) and the system clock to write to the transmission memory. Asynchronous high level data link control data transceiver. The apparatus of claim 1, wherein the first rate converter reads the data written in the transmission memory and transmits the data written in the transmission memory to the relay line framer and the line matching unit in synchronization with the system clock provided by the clock generator. Asynchronous high-level data link control data transmission and reception device characterized in that. The asynchronous high-level data of claim 1, wherein the first rate converter stops reading the transmission memory and the data when there is no data in the transmission memory and controls the predetermined data to be transmitted to the relay line framer and the line matching unit. Link control transceiver. 2. The asynchronous high level data link control data transmission / reception apparatus according to claim 1, wherein the reception memory is a memory having a first-in first-out function. The receiving memory of claim 1, wherein the second rate converter extracts IPC data in a pure HDLC form as a system clock provided from the clock generator from a channel data sequence of a predetermined frequency input from the relay line framer and the line matcher. An asynchronous high level data link control data transmission / reception device, characterized in that for writing. The system of claim 1, wherein the second rate converter receives an FS (8Khz) coming from the IPC side of the system, receives a received clock, reads data in a reception memory, and transmits the data to the IPC side of the system in synchronization with the received FS and RXCLK Asynchronous high-level data link control data transmission and reception apparatus characterized by. The asynchronous high-level data link control of claim 1, wherein the second rate converter stops data reading of a receiving memory when data is not present in the receiving memory so that predetermined data is transmitted to the IPC of the system. Data transceiver.