KR100206141B1 - A load detector for decreasing power-loss - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load detector that reduces power loss, and more particularly, to a load detector that includes a control signal generator for outputting a predetermined control signal; A first switching unit connected between the power supply voltage and a first node and responsive to an output signal of the control signal generating unit; A second switching unit connected between the first node and one end of the sense resistor for monitoring a voltage of the first switching unit and outputting a predetermined signal to an input terminal and a next terminal of the first switching unit; A negative terminal coupled between the first node and a ground voltage; A sense resistor connected between the second switching unit and a ground voltage; And a third switching unit for generating a load detection signal in response to the load current detected by the sense resistor.

Therefore, according to the present invention, there is an effect that power loss can be minimized by connecting a load detector for detecting a voltage of a transistor driving a load in parallel to a load without connecting the load detector in series with the load .

Description

Load detector with reduced power loss.

The present invention relates to a load detector with reduced power loss, and more particularly, to a load detector that detects a load state by connecting a sense resistor connected in series to a load stage in parallel at a load stage, .

FIG. 1 is a block diagram showing a conventional load detector. The load detector includes a control signal generating unit 1, a first switching unit 3, a load terminal 5, a sense resistor 7, (9).

The control signal generator 1 is connected between the power supply voltage VCC and the ground voltage GND and is configured to output a predetermined control signal IB. (5) is connected between the voltage (VCC) and the first node (N1) and is responsive to the output control signal (IB) of the control signal generation section (1) And the sense resistor 7 is configured to be connected in series between one end of the negative terminal 5 and the ground voltage GND and the second switch 7 is connected to one end of the sense resistor 7, (9) is configured to generate a load detection signal in response to the load current detected by the sense resistor (7).

FIG. 2 is a circuit diagram showing a load detector according to the embodiment of FIG. 1, including an output transistor Q1, a load terminal 5, a sense resistor R, and a load detection transistor Q2.

The output transistor Q1 is configured such that a current path is connected between the power supply voltage VCC and the first node N1 and responds to the transistor drive control signal IB, The sense resistor R is configured to be connected between the first node N1 and the second node N2 and the sense resistor R is configured to be connected between the second node N2 and the ground voltage GND, The transistor Q2 is connected between the final detection node Detect and the ground voltage GND and is configured to respond to the signal of the second node N2.

In the conventional technique configured as described above, a predetermined load voltage is generated at the second node N2 on the sense resistor R when the load 5 is in a load state or in a no load state, And the signal of the second node N2 is inputted to the base voltage Vbe of the load detection transistor Q2. Further, the sense resistor R1 is connected in series to the load terminal 5, so that the load current always flows to the sense resistor R, and a power loss occurs in a normal operating state as shown in the following equation.

[Formula 1]

P = (I _R ) ² R (I _R : load current, R: sense resistor value)

If the resistance value of the sense resistor R is reduced in order to reduce the power loss as shown in Equation 1, the generated voltage (I _R x R) of the sense resistor becomes small so that the load detection signal generating circuit should be designed to output the low voltage The load detection signal generating circuit portion becomes complicated.

Therefore, the conventional sense resistor of the load detector is connected in series with the load, and the load current always flows to the sense resistor, which causes a problem that a large power loss occurs in a normal operation state.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the power loss by minimizing the power loss upon detecting a load by connecting a sense resistor connected in series to the load stage in parallel in order to solve the above- And a load detector for detecting the load.

According to an aspect of the present invention, there is provided an apparatus comprising: a control signal generator for outputting a predetermined control signal; A first switching unit connected between the power supply voltage and a first node and responsive to an output signal of the control signal generating unit; A second switching unit connected between the first node and one end of the sense resistor for monitoring a voltage of the first switching unit and outputting a predetermined signal to an input terminal and a next terminal of the first switching unit; A negative terminal coupled between the first node and a ground voltage; A sense resistor connected between the second switching unit and a ground voltage; And a third switching unit for generating a load detection signal in response to the load current detected by the sense resistor.

1 is a block diagram showing a conventional load detector;

FIG. 2 is a circuit diagram showing a load detector according to the embodiment of FIG. 1; FIG.

3 is a block diagram showing a load detector according to the present invention.

FIG. 4 is a circuit diagram showing a load detector according to the embodiment of FIG. 3; FIG.

Description of the Related Art [0002]

10: control signal generating unit 20: first switching unit.

30: second switching part.

50: sense register. 60: third switching section.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3 is a block diagram showing a load detector according to the present invention. The load detector includes a control signal generator 10, a first switching unit 20, a second switching unit 30, a negative terminal 40, A register 50 and a third switching unit 60. [

The control signal generator 10 is connected between the power supply voltage VCC and the ground voltage GND and is configured to output a predetermined control signal IB. And the second switching unit 30 is connected between the power supply voltage VCC and the first node Nd1 and configured to respond to the output control signal IB of the control signal generating unit 10, The first switching unit 20 is connected between the node Nd1 and one end of the sense resistor 50 to monitor the voltage of the first switching unit 20 and outputs a predetermined signal to the input terminal of the first switching unit 20 and the next terminal 50 And the negative terminal 40 is configured to be connected between the first node Nd1 and the ground voltage GND and the sense resistor 50 is connected to the second switching unit 30, And the third switching unit 60 is configured to be connected between the ground voltage GND and the sense resistor 50, And generate a load detection signal in response to the load current.

4 is a circuit diagram showing a load detector according to the embodiment of FIG. 3. The output transistor Q0, the first monitoring transistor Q1, the second monitoring transistor Q2, the lower stage 40, , A sense resistor (R), and a load detection transistor (Q3).

The output transistor Q0 is configured such that a current path is connected between the power supply voltage VCC and the first node Nd1 and is responsive to the transistor drive control signal IB, And the second monitoring transistor (Q2) is configured to respond to a signal of the first node (Nd1), and the second monitoring transistor (Q2) is configured to respond to a signal of the first node The current path is connected between the node Nd1 and the second node Nd2 and is configured to respond to the output signal of the first monitoring transistor Q1 and the negative terminal 40 is configured to be connected to the first node Nd1, And the sense resistor R is connected between the second node Nd2 and the ground voltage GND and the load detection transistor Q3 is connected between the second node Nd2 and the ground voltage GND. The final detection stage (Detect) and ground A current path is connected between the voltage (GND) is configured to respond to the signal at the second node (Nd2).

When the control signal IB for driving the output transistor Q0 of the load detector configured as described above is applied to the base end of the output transistor Q0, the output transistor Q0 is turned on, The potential of the node Nd1 is pulled up to the power supply voltage VCC.

The operation state of the first monitoring transistor Q1 in the turn-on state of the output transistor Q0 is as follows.

[Formula 2]

Vbe, Q1 = Vbe, Q0 - Vce, Q0

= Vbe, Q0 - (Io + Id) x Ron

= Vbe, Q0 - (Io x Ron)

(Io; load current, Id; load detector current consumption Id < Io), Ro; Qo turn-on resistance)

It can be seen that the voltage Vbe, Q1 between the base and the emitter of the first monitoring transistor Q1 decreases as the load current Io of the output transistor Q0 increases as shown in Equation 2 above. Therefore, the base-emitter voltage (Vbe, Q1) of the first monitoring transistor (Q1) which varies according to the load current is smaller than the voltage (Von, Q1) required for turning on the first monitoring transistor (Q1) The first and second monitoring transistors Q1 and Q2 are turned off and the base of the first monitoring transistor which changes in accordance with the load current than the voltages Von and Q1 necessary for the first monitoring transistor to turn on, - When the emitter voltage (Vbe, Q1) is large, the first and second monitoring transistors Q1 and Q2 are turned on.

By driving the first monitoring transistor Q1, the base end of the second monitoring transistor Q2 becomes a low voltage and the second monitoring transistor Q2 is also turned on.

Meanwhile, when a load is connected to the negative terminal 40 connected to the first node Nd1, the load current Io flowing through the output transistor Q0 is supplied to the load, The voltages Vbe and Q1 between the base and the emitter of the first monitoring transistor Q1 are reduced so that the first and second monitoring transistors Q1 and Q2 are turned off and the second node Nd2 become low voltage, the load detection transistor Q3 is turned off, and the final detection stage outputs a high signal.

That is, when the negative terminal 40 is not in a no-load state, the consumption of the current Id of the first and second monitoring transistors Q1 and Q2 and the load detection transistor Q3 becomes zero.

When the load 40 is connected to the first node Nd1 and the load current Io is zero, the current supplied from the output transistor Q0 is zero, Current Id. Therefore, as shown in Equation 2, the voltage (Vbe, Q1) between the base and the emitter of the first monitoring transistor Q1 is almost equal to the voltage between the base and the emitter of the output transistor Q0.

Under these conditions, Vbe, Q1? Vbe, Q0 Von, and Q1 are established so that the first and second monitoring transistors Q1 and Q2 are turned on and the potential of the second node Nd2 is controlled by the sense resistor R It has a high potential. Accordingly, the load detection transistor Q3 is turned on and the final detection stage outputs a low signal according to the high voltage of the second node Nd2.

Therefore, as described above, in the present invention, the load detector for detecting the voltage of the transistor driving the load, without connecting the load detector to the load in series, can be connected in parallel with the load to minimize the power loss There is an effect.

Claims (3)

A control signal generator for outputting a predetermined control signal; A first switching unit connected between the power supply voltage and a first node and responsive to an output signal of the control signal generating unit; A second switching unit connected between the first node and one end of the sense resistor for monitoring a voltage of the first switching unit and outputting a predetermined signal to an input terminal and a next terminal of the first switching unit; A negative terminal coupled between the first node and a ground voltage; A sense resistor connected between the second switching unit and a ground voltage; And a third switching unit for generating a load detection signal in response to the load current detected by the sense resistor. [2] The apparatus of claim 1, wherein the second switching unit includes: a first monitoring transistor having a current path connected between a predetermined transistor base stage and a control signal terminal of the first switching unit and responsive to a signal of the first node; And a second monitoring transistor having a current path connected between the first node and the second node and responsive to an output signal of the first monitoring transistor. The load detector according to claim 1, wherein the current consumption of the second switching unit and the third switching unit is zero when the negative terminal is not in a no-load state.