KR100205649B1 - Method and apparatus of transceiver of ir-data - Google Patents

Abstract

The present invention relates to a method and apparatus for transmitting and receiving infrared data, which enables data transmission and reception in parallel using a single infrared wavelength.

In the present invention, the data to be transmitted is set in parallel and the PN code (Pseudo Noise Code) having mutual orthogonality is multiplied with each data. In addition, after a plurality of data multiplied by the PN code are added using an adder, the corresponding data is output through a single infrared diode.

On the receiving device side, a PN code generating device for generating and outputting the same PN code as the PN code generating device adopted on the transmitting device side is multiplied by the PN code outputted from the PN code generating device with respect to the received data. The data is separated and detected.

Therefore, according to the present invention, it is possible to transmit and receive a plurality of parallel data using a single infrared diode and a light receiving transistor, thereby increasing the data transmission speed and receiving infrared data without affecting the external noise environment. And an apparatus.

Description

Infrared data transmission and reception method and apparatus

The present invention relates to an infrared data transmitting and receiving apparatus for transmitting and receiving infrared data, and more particularly, to an infrared data transmitting and receiving method and apparatus capable of performing data transmission and reception in parallel using a single infrared wavelength.

Currently, in general home appliances, a remote control function using infrared rays is adopted so that a user can remotely control the home appliances, and recently, office equipment has adopted a data transmission / reception function using infrared rays, so that a computer main body and a keyboard device, or Wireless is attempted between the computer and the printer.

1 is a configuration diagram schematically showing the configuration of a data transmission and reception system using infrared light.

In Fig. 1, reference numeral 1 denotes a data output port for outputting predetermined data, and 2 denotes an infrared data output unit for converting and outputting an electric code signal output from the data output port 1 into infrared data.

Here, the infrared data output unit 2 is provided on a transistor Q1 which is turned on / off according to the value of data output from the data output port 1 and on a current path flowing through the transistor Q1. Through an infrared diode (LED) corresponding to an on / off state of the transistor (Q1), that is, outputting an infrared signal corresponding to data output from the data output port (1), and through the infrared diode (LED) And a resistor (R1) for limiting the flowing current.

In FIG. 1, reference numeral 3 denotes an infrared data receiver that receives an infrared signal output from the infrared data output unit 2 and generates an electrical code signal corresponding to the corresponding signal, and 4 denotes the infrared data receiver 3. Data input port for inputting electric code signal output from) to system.

In addition, the infrared data receiver 3 is coupled to a light receiving transistor Q2 that is turned on / off according to whether an infrared signal is input, a current limiting resistor R2, and a collector terminal of the light receiving transistor Q2. It is comprised including the inverter IV.

That is, in the above data transmitting / receiving system, first, when the data of " 1 " or " 0 " is output from the infrared data output unit 2 on the transmitting side, the transistor Q1 is turned on / off according to the output data and the infrared light is transmitted. When the diode LED is turned on / off, an infrared signal corresponding to the corresponding code signal is output.

On the receiving side, when an infrared signal is applied from the transmitting side, the light receiving transistor Q2 is driven on / off in accordance with the infrared signal, and the voltage variation of the collector stage according to the on / off of the light receiving transistor Q2 is changed. By being applied to the data input port 4 through (IV), the data output through the data output port 1 is input through the data input port 4.

Therefore, it is possible to transmit and receive the desired data without a separate signal line.

However, in the above-described infrared data transmission / reception system, data transmission takes a long time because data transmission is performed serially, and since the infrared signal is used as a transmission / reception carrier, it is affected by other external light sources. Will be.

Therefore, in recent years, attempts have been made to transmit and receive data in parallel using a plurality of infrared diodes that output infrared signals of different wavelengths, but in this case, the system may be damaged by heat emitted from the plurality of infrared diodes. In particular, there is a problem that is particularly affected by external noise and the like.

Accordingly, the present invention has been made in view of the above circumstances, and is capable of transmitting and receiving transmission data in parallel using a single infrared wavelength, that is, a single infrared diode, and is not affected by external noise environments. It is an object of the present invention to provide a transmission and reception method and an apparatus thereof.

1 is a block diagram showing a general infrared data transmission and reception apparatus.

2 is a block diagram showing an infrared data transmission apparatus according to an embodiment of the present invention.

3 is a configuration diagram showing the configuration of the PN code generation unit in FIG.

4 is a block diagram showing an infrared data receiver corresponding to the transmitter shown in FIG.

5 is a configuration diagram showing the configuration of a synchronization processing unit in FIG.

6 is a configuration diagram showing the configuration of the tracking processing unit in FIG.

7 is a configuration diagram showing the configuration of the clock control unit in FIG.

FIG. 8 is a waveform diagram showing an output waveform of each circuit section in the clock control section shown in FIG.

FIG. 9 is an operation flowchart for explaining the operation of the apparatus shown in FIG. 4; FIG.

* Brief description of the main parts of the drawing

21: serial / parallel converter, 22: multiplier,

23: summer, 24: infrared data output unit,

25: PN code generator, 25 _{0 to} 25n: PN code generator,

25A: shift register, 25B: modular-2 adder,

40: receiving unit, 41: switching unit,

42: PN code generation unit, 43: initial synchronization processing unit,

44: tracking processing unit, 45: clock control unit,

46: ROM table, 47: integrating circuit,

48: comparator, 50: controller,

51: multiplier, 52: parallel / serial converter,

431: multiplier, 432: integral circuit,

433: sampling circuit, 434: comparator,

441, 442: delay circuit, 443-445: multiplier,

446-448: integrating circuit, 449-451: sampling circuit,

452: adder, 453: analog-to-digital converter,

454, 455: comparator, 456: end circuit,

501: reference clock generator, 502: delay circuit,

503, 505: switching unit, 504: frequency multiplier.

An infrared data transmission / reception method according to the first aspect of the present invention for realizing the above object comprises a step of multiplying a PN code multiplication step of multiplying PN codes having mutual orthogonality with respect to each of parallel data and multiplying the data multiplied by the PN code. A data transmission step including an infrared data output step of outputting infrared data of a single wavelength based on the data summing step and the data generated in the data summing step, a data conversion step of converting the received infrared data into an electrical signal; And a PN code generation step of generating a PN code identical to the PN code used in the data transmission step and a PN code multiplication step of multiplying the generated PN code with respect to the received data. It is done.

In addition, the infrared data transmitting and receiving apparatus according to the second aspect of the present invention for realizing the above object has a PN code generating means for generating a plurality of PN codes having mutual orthogonality and different PN codes for a plurality of parallel data to be output. Infrared data transmission comprising a plurality of multiplication means for multiplying, a summation means for summing and outputting a plurality of parallel data output from the multiplication means and an infrared data output means for outputting infrared data corresponding to the data output from the summation means A device, receiving means for converting received infrared data into electrical data with a predetermined PN code added thereto, and PN code generating means for generating and outputting a plurality of PN codes identical to each PN code added to the received data; And a PN code outputted from the PN code generating means for the received data. And an infrared data receiving device including a plurality of multiplication means, each of which multiplies.

According to the present invention having the above-described configuration, the transmitting side multiplies and outputs a PN code having mutual orthogonality to the data to be transmitted, and the receiving side multiplies the same PN code as the PN code added at the time of transmission for the same data. Only data to which the PN code is added is detected.

Thus, by transmitting and receiving a plurality of parallel data using a single infrared diode and a light receiving transistor, it is possible to increase the data transmission speed and to exclude the influence of external noise environment.

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

2 is a block diagram showing a data transmission apparatus in an infrared data transmission and reception apparatus according to an embodiment of the present invention.

In Fig. 2, reference numeral 21 denotes a serial / parallel converter for converting input serial data into parallel data, and 22 _{0 to} 22n denote PNs described later for each of the parallel data output from this serial / parallel converter 21. It is a multiplier that multiplies the PN codes P0 to Pn outputted from the code (Pseudo Noise Code) generating unit 25.

Further, reference numeral 23 denotes an adder for summing up and outputting a plurality of input signals applied from the multipliers 22 _{0 to} 22n, and 24 outputting infrared data corresponding to the digital signal output from the adder 23. Infrared data output unit.

Reference numeral 25 denotes a PN code generator that outputs a plurality of PN codes P0 to Pn having mutually orthogonality in response to the input of the clock signal CLK.

3 is a block diagram showing the configuration of the PN code generator 25. The PN code generator 25 generates and outputs each PN code having orthogonality to each other according to an input clock signal CLK. Further included is a ₀ ~25n).

Each of the PN code generators 25 _{0 to} 25n has a plurality of shift registers 25A connected in series, and the least significant bit (LSB) output is fed back as the most significant bit (MSB), and the least significant bit ( The shift output of LSB) is output as a PN code and is added to the shift output of the most significant bit (MSB) and the shift input of the least significant bit (LSB) by the Modular-2 Adder (25B). The data, that is, the PN code, has orthogonality and constant circularity. Since the PN code generators 25 _{0 to} 25n are generally well known, detailed description thereof will be omitted.

That is, in the above-described configuration, serial data to be transmitted is converted into parallel data through the serial / parallel converter 21, and then multiplied by PN codes having mutual orthogonality in the multipliers 22 _{0 to} 22 n for each parallel data. Done. Therefore, the respective data output from the multipliers 22 _{0 to} 22 n have mutually orthogonality.

The output data of the multipliers 22 _{0 to} 22 n are summed as a single signal by the adder 23 and then output as an infrared signal through a single infrared data output unit 24.

4 is a block diagram showing the configuration of a receiver for detecting original data from infrared data output from the transmitter.

In FIG. 4, reference numeral 40 denotes a receiver for converting the input infrared data into an electrical code signal, and 41 denotes an initial synchronization of data output from the receiver 40 according to a switching signal from the controller 50, which will be described later. The switching unit selectively outputs the processing unit 43 and the tracking processing unit 44.

Further, reference numeral 42 denotes a PN code generator that generates and outputs a plurality of PN codes P0 to Pn each having an orthogonality, which has the same configuration as that of the PN code generator 25 on the transmitter side shown in FIG. It is.

That is, the PN code generator 42 generates a plurality of PN code generators 25 _{0 to} 25 n which generate and output respective PN codes having mutually orthogonality according to the input clock signal CLK as shown in FIG. 2. Each PN code generator 25 _{0 to} 25 n includes a shift register 25A and a modular-2 adder 25B. The shift register 25A is loaded with the same data as the PN code generator 25 in FIG. 2 as its initial value, and the input clock CLK is supplied from the clock controller 45 to be described later. To be authorized.

In FIG. 4, reference numeral 43 denotes a PN code generator by processing received data applied through the switching unit 41 based on a predetermined PN code P0 output from the PN code generator 42. An initial synchronization processing section for outputting a synchronization level signal for initial synchronization processing of the PN codes P0 to Pn outputted from 42).

5 is a block diagram showing the configuration of the initial synchronization processor 43, which is a PN code P0 output from the PN code generator 42 for the received data input through the switching unit 41. An multiplier 431 for multiplying, an integrating circuit 432 for integrating the signal output from the multiplier 431, a sampling circuit 433 for sampling the signal output from the integrating circuit 432 at a predetermined sampling period, and When the level of the signal sampled by the sampling circuit 433 is greater than a predetermined reference value, " 0 " level in this example, a comparator 434 for outputting a high level detection signal is included.

As described above, each of the PN codes P0 to Pn output from the PN code generator 25 or 42 has a periodicity and a mutual orthogonality. Therefore, when the transmission side multiplies the PN code other than the original PN code by multiplying the predetermined PN code, the multiplied data value becomes "0".

In FIG. 5, a predetermined PN code, ie, P0, is multiplied with the received data applied through the switching unit 41 using the above-described principle. By integrating and sampling the multiplied data, a level signal corresponding to the degree of synchronization between the PN code multiplied by the transmitting side and the PN code output from the PN code generator 42 is generated. Then, the comparator 434 compares whether the sampled signal level is greater than the " 0 " level. If the PN code P0 and PN code outputted from the PN code generator 42 When P0) is synchronized within one period, the signal level output from the sampling circuit 433 is greater than the " 0 " level, so that the comparator 434 outputs a high level comparison signal.

In FIG. 4, reference numeral 44 denotes a tracking processor, which processes received data applied by the switching unit 41 based on the PN code P0 output from the PN code generator 42 to process the received data. The added PN code is compared with the phases of the PN codes output from the PN code generator 42, and the data values corresponding to the phase match states of the PN codes are output.

6 is a configuration diagram showing the configuration of the tracking processing unit 44. In the drawing, reference numeral 441 denotes a first delay circuit for delaying the received data applied by the switching unit 41 for a predetermined time, and 442 is the first delay circuit. The second delay circuit delays the data output by the delay circuit 441 for a predetermined time.

Reference numeral 443 denotes a first multiplier that multiplies a predetermined PN code P0 with respect to received data applied by the switching unit 41, and 444 denotes a reception delayed by the first delay circuit 441. A second multiplier for multiplying the PN code P0 with respect to data, and 445 is a multiplier for multiplying the PN code P0 with respect to received data delayed by the first and second delay circuits 441 and 442. 3 multipliers.

Reference numerals 446 to 448 denote first to third integrating circuits for integrating data signals output from the first to third multipliers 443 to 445, respectively, and 449 to 451 for the first to third integrating circuits. The first to third sampling circuits sample and output the signals output from 446 to 448 at predetermined sampling periods.

Reference numeral 452 denotes that the voltage signal output from the first sampling circuit 449 is a negative signal, and the voltage signal output from the third sampling circuit 451 is a positive signal. 453 is an analog / digital converter that converts the analog voltage signal output from the adder 452 into digital data and outputs the digital data.

Also, reference numeral 454 in the drawing compares the level signal output from the second sampling circuit 450 with a predetermined reference voltage set by the resistors R3 and R4, so that the output of the second sampling circuit 450 is reduced. When the reference voltage is greater than the reference voltage, the first comparator outputs a high level comparison signal, and 455 denotes a predetermined reference voltage set by the level signals output from the second sampling circuit 450 and the resistors R5 and R6. In comparison, when the output of the second sampling circuit 450 is smaller than the reference voltage, the second comparator outputs a high level comparison signal, wherein the second comparator 455 is more than the first comparator 455. The voltage is set large. The outputs of the first and second comparators 454 and 455 are multiplied by the AND circuit 456 to be output.

That is, in the configuration of FIG. 6, the output of the first sampling circuit 449 has a high phase, that is, the PN code generation unit compared to the PN code added to the received data based on the output of the second sampling circuit 450. The phase of the PN code outputted from 42 corresponds to a fast phase, and the output of the third sampling circuit 451 is of a phase that is slow, that is, the PN code generator 42 compared to the PN code added to the received data. ) Corresponds to a slow phase of the PN code.

Therefore, if the signal level output from the first sampling circuit 449 is greater than the signal level output from the third sampling circuit 451 because the phase of the PN code currently output from the PN code generator 42 is fast. Data having a negative value corresponding to the level difference is output through the analog / digital converter 453, and the phase of the PN code currently output from the PN code generator 42 is delayed so that the first sampling circuit ( When the signal level output from the 449 is smaller than the signal level output from the third sampling circuit 451, data having a positive value corresponding to the level difference is output through the analog / digital converter 453. Will be.

In addition, the signal level output from the second sampling circuit 450 is applied to the first and second comparators 454 and 455. Accordingly, in the AND circuit 456, the second sampling circuit 450 When the output signal level has a level value between the reference voltage by the resistors R3 and R4 and the reference voltage by the resistors R5 and R6, a high level signal is output.

In FIG. 4, reference numeral 45 denotes a clock controller supplying the clock signal CLK to the PN code generator 42 described above under the control of the controller 50 to be described later.

7 is a block diagram showing the configuration of the clock control unit 45. In the drawing, reference numeral 501 denotes a reference clock for generating and outputting a clock signal having a predetermined frequency according to the clock enable signal CK_EN applied from the controller 50. It is a generator. At the output terminal of the reference clock generator 501, a plurality of delay circuits 502 (502 _{1 to} 502 ₁₅ ) (502 in this example) are coupled in series, and the reference clock generator 501 and the delay circuit 502 are connected in series. And each output of the coupling unit is coupled to an input terminal of the first switching unit 503. The first switching unit 503 selectively outputs one input according to the second switching signal SW2 applied from the controller 50.

In addition, the delay circuits 502 _{1 to} 502 ₁₅ are all set to the same delay time, and each delay time of 1/16 with respect to one cycle of the clock signal output from the reference clock generator 501. It is supposed to have Therefore, even in the order of the delay circuit (502, ₁₅₎ from the delay circuit (502 ₁₎ for a reference clock (A) when, based on the TI as shown in FIG. 8 sequentially 1/16, 2/16, 3/16 ... The phase is delayed by 15/16, or is sequentially 1/16, 2/16, 3/16 ... in order from delay circuit 502 ₁₅ to delay circuit 502 ₁ . It outputs a clock signal with a phase as fast as 15/16.

In FIG. 7, reference numeral 504 denotes a frequency multiplier for multiplying the reference clock output from the reference clock generator 501 by a predetermined multiplier (two multipliers in this example), and 505 denotes a first switching signal applied from the controller 50. According to (SW1) it is a second switching unit for selectively outputting the output of the first switching unit 503 and the frequency multiplier 504. The output of the second switching unit 505 is then applied to the PN code generation unit 42 described above.

In FIG. 4, reference numeral 46 denotes a ROM table, which corresponds to the first switch 503 of the clock controller 45 in response to data applied from the analog / digital converter 453 of the tracking processor 44 described above. Each first switching data SW1 for switching control is stored.

In Fig. 4, reference numeral 47 denotes an integrating circuit for integrating the received data output from the receiving section 40 described above, and 48 denotes an integrating circuit by comparing the signal level output from the integrating circuit 46 with a predetermined reference level. When the output level of (46) is higher than or equal to the reference level, for example, a comparator for outputting a high level comparison signal, these integrating circuits 47 and comparator 48 are for detecting whether infrared data is currently being received. .

Reference numeral 50 denotes a controller for controlling the infrared data receiving apparatus according to the present invention. When the high level comparison signal is input from the above-described comparator 48, the clock enable signal 45 is transmitted to the clock controller 45. CK_EN) to drive the clock control section 45, and the first and second switching sections 503 of the clock control section 45 in accordance with the input data from the initial synchronization processing section 43 and the tracking processing section 44 described above. And 505, the PN code output from the PN code generator 42 is synchronized with the PN code added by the transmitting side.

In FIG. 4, reference numeral 51 denotes a plurality of multipliers respectively coupled in parallel to the received data output from the receiver 40 to multiply the PN codes P0 to Pn output from the PN code generator 42 described above. A multiplication section including 51 _{1 to} 51n, and 52 is a parallel / serial converter for converting a plurality of parallel data input from the multiplication section 51 into serial data and outputting the serial data.

Next, the operation of the infrared data receiver having the above configuration will be described using the operation flowchart shown in FIG.

First, since the clock enable signal CK_EN is not output from the controller 50 in the initial state without data reception, the clock controller 45 is in a disabled state, and accordingly, the PN code generator 42 is also disabled. The infrared data receiving apparatus in the enabled state is set in an inoperative state.

On the other hand, when the infrared data is received from the transmitting apparatus in the above state and the code signal is input through the receiving unit 40, and thus the high level comparison signal is output from the comparing unit 48 as described above (ST1 step) The controller 50 outputs the clock enable signal CK_EN to the reference clock generator 501 of the clock controller 45 to enable the clock controller 45 and the first and second switching units ( 503 and 505 to control the clock signal output from the reference clock generator 501 to the PN code generator 42, and to control the switching unit 41 of FIG. ) And the initial synchronous processing unit 43 are executed to perform the initial synchronous processing (step ST2).

When the data input from the receiver 40 is applied to the initial synchronization processor 43 shown in FIG. 5 by the above operation, the initial synchronization processor 43 is output from the PN code generator 42 as described above. The predetermined PN code signal P0 is multiplied by the input data, and then integrated and sampled to compare with the predetermined reference level.

In the above initial synchronization processing, if the PN code P0 added to the input data and the PN code P0 multiplied by the multiplier 431 are not synchronized, the multiplication result of the multiplier 431 is " 0 ", the output of the comparator 434 is at a low level. When the PN code P0 added to the received data and the PN code P0 supplied to the multiplier 431 are synchronized in one cycle, Since the output of the integrating circuit 432 has a level according to the synchronization, the comparator 434 outputs a high level.

In the controller 50, when a low level is input from the comparator 434, that is, from the initial synchronization processor 43, the controller 50 controls the second switching circuit 505 (FIG. 7) of the clock controller 45 for a predetermined time. While outputting the multiplied clock signal output from the frequency multiplier 504. Then, the clock controller 45 is again controlled by the method of determining whether the high level is input from the initial synchronization processor 43. When the high level determination signal is input from the initial synchronization processor 43 by this process, It is determined that synchronization has been made (steps ST3 and ST4).

As described above, when the initial synchronization process is completed, the controller 50 controls the switching unit 41 to combine the receiving unit 40 and the tracking processing unit 44, and thus the receiving processing unit 44 receives the received data. Will be entered.

As described in FIG. 6, the tracking processing unit 50 adds the outputs of the first sampling circuit 449 and the third sampling circuit 451 to the received data based on the output signal of the second sampling circuit 450. An error voltage according to the phase difference between the added PN code P0 and the PN code P0 output from the PN code generator 42 is generated. The error voltage is then applied to the controller 50 via the analog / digital converter 453.

When the controller 50 receives the error data from the tracking processor 44, the controller 50 reads the switching data corresponding to the error data from the ROM table 46, and controls the first switching unit 503 of FIG. 7 based on the switching data. As a result, the output of the reference clock generator 501 or the first to fifteenth delay circuits 502 _{1 to} 502 ₁₅ is selectively output. In this way, the phase of the PN code added to the received data and the PN code outputted from the PN code generator 42 coincide within a predetermined range so that a high level detection signal is generated from the AND gate 456 of FIG. If it is input, the tracking process ends (steps ST5 and ST6).

Therefore, at this time, the multiplier 51 multiplies the received data with the same PN code as the PN code added to the received data, thereby inputting from the parallel / serial converter 52 to the serial / parallel converter 21 on the transmitting side. The same data is output as the data.

Subsequently, when the data transmission from the transmitting end is terminated in the above data receiving operation state and there is no data input through the receiving unit 40, that is, when the comparison signal of "0" level is output from the comparing unit 48 ( ST7), the controller 50 stops the supply of the clock enable signal CK_EN to the clock controller 45 and sets the clock controller 45 and the PN code generator 42 to the disabled state. The receiving operation is completed (ST8 step).

That is, according to the embodiment, the transmitting side multiplies and outputs a PN code having mutual orthogonality to the data to be transmitted, and the receiving side multiplies the same PN code as the PN code added at the time of transmission to the same PN code. Only data to which is added is detected.

Therefore, by transmitting and receiving a plurality of parallel data using a single infrared diode and a light receiving transistor, it is possible to increase the data transmission speed and fundamentally solve the heating problem by using a plurality of infrared diodes. .

Further, according to the above embodiment, only data to which the same PN code as the PN code multiplied by the receiving device is added is detected, so that it is not influenced by an external noise environment.

In addition, this invention is not limited to the said Example, It can implement in a various deformation | transformation in the range which does not deviate from the technical summary of this invention.

That is, for example, in the above embodiment, the case where the parallel data is transmitted and received using a single infrared wavelength has been described. However, the present invention can be applied in the same manner even when the serial data is transmitted and received. The effect of excluding the influence on the noise can be obtained.

In addition, although not described in detail in the above embodiment, when employing the infrared transceiver according to the present invention, it is preferable to transmit predetermined data for a predetermined time before transmitting data from the transmitting side. This is advantageous for good synchronization processing and tracking processing as well, since it is possible to prevent data loss during the time corresponding to synchronization processing and tracking processing on the receiving side. In this case, the predetermined data is preferably data in which all bits are "1" or "0", which is not limited to any particular data but is loaded into the shift register 25A of the PN code generator 25 ₀ in FIG. It can be set appropriately according to the data to be generated.

That is, the technical scope of the present invention may be limited only by the claims described in the present specification.

As described above, according to the present invention, a single infrared wavelength, i.e., a single infrared diode, can transmit and receive transmission data in parallel, and realize an infrared data transmission / reception method and apparatus that are not affected by an external noise environment. It becomes possible.

Claims (15)

A data transmission step including a code multiplication step of multiplying a code having orthogonality with another code with respect to output data, and an infrared data output step of outputting infrared data based on the data multiplied by the code; A data conversion step of converting the received infrared data into an electrical signal, a code generation step of generating the same code as the code used in the data transmission step, and a code multiplication step of multiplying the generated code by the received data Infrared data transmission and reception method characterized in that it comprises a data receiving step comprising a. The infrared data transmitting / receiving method according to claim 1, wherein the multiplication code is a PN code. A PN code multiplication step of multiplying PN codes having mutual orthogonality with respect to each of the parallel data, a data adding step of adding up data multiplied by the PN code, and a data having a single wavelength based on the data generated in the data adding step. A data transmission step including an infrared data output step of outputting infrared data; A data conversion step of converting the received infrared data into an electrical signal, a PN code generation step of generating the same PN code as the PN code used in the data transmission step, and multiplying the generated PN code by the received data And a data receiving step comprising a PN code multiplication step. PN code generating means for generating a predetermined PN code, Multiplication means for multiplying the PN code with respect to data to be output; And infrared data output means for outputting infrared data corresponding to data output from the multiplication means. Receiving means for converting infrared data received with a predetermined PN code into electrical data; PN code generating means for generating and outputting the same PN code as the PN code added to the received data according to the input clock signal; And multiplication means for multiplying the received data by the PN code outputted from the PN code generating means. 6. The synchronization processing apparatus according to claim 5, further comprising: synchronization processing means for driving control of said PN code generating means in synchronization with a PN code added to said received data; Infrared data reception, characterized in that it further comprises a tracking processing means for driving control of the PN code generating means so that the phase of the PN code added to the received data and the PN code output from the PN code generating means coincide. Device. 7. The apparatus according to claim 6, wherein the synchronization processing means includes: multiplication means for multiplying a predetermined PN code among the PN codes outputted from the PN code generation means with respect to received data, an integration means for integrating the output of the multiplication means, the integration Comparison means for comparing the output level of the means with a predetermined reference level, reference clock generating means for generating a clock signal having a predetermined reference frequency, frequency multiplying means for multiplying the reference clock by a predetermined multiple, the reference clock generating means and the frequency And switching means for selectively outputting the output of the multiplication means to the PN code generating means, and control means for switching and controlling the switching means in accordance with the output of the comparing means. 7. The apparatus according to claim 6, wherein said tracking processing means is output from said PN code generating means for each of first delay means for delaying received data for a predetermined first time and for output of said received data and first delay means, respectively. First and second multiplication means for multiplying a predetermined PN code among the PN codes, first and second integrating means for integrating the outputs of the first and second multiplication means, respectively, and outputs of the first and second integrating means. Adding means for adding and subtracting a number, a reference frequency generating means for generating a predetermined reference frequency, a plurality of delay means coupled in series with the reference frequency generating means, each having a predetermined delay time, and the reference frequency and the delay means. Switching means for selectively applying an output to said PN code generating means, and control means for switching and controlling said switching means based on an output level of said adding means. Infrared data receiving device, characterized by. 9. The apparatus according to claim 8, wherein said tracking processing means comprises: second delay means for delaying said received data for a second delay time less than said first delay time, and from said PN code generating means for an output of said second delay means. Third multiplication means for multiplying a predetermined PN code among output PN codes, third integration means for integrating the output of the third multiplication means, and comparison means for comparing whether the output level of the third integration means is within a predetermined range. And the control means fixedly sets the switching state of the switching means when it is determined by the comparing means that the output of the third integrating means is within a predetermined range. Device. PN code generating means for generating a plurality of PN codes having mutual orthogonality, a plurality of multiplication means for multiplying different PN codes for a plurality of parallel data to be output, and a plurality of parallel data output from the multiplication means An infrared data transmitting apparatus comprising an adding means for outputting, and an infrared data output means for outputting infrared data corresponding to data output from the adding means; Receiving means for converting infrared data received by adding a predetermined PN code into electrical data, PN code generating means for generating and outputting a plurality of PN codes identical to each PN code added to the received data; And an infrared data receiving device including a plurality of multiplication means for multiplying the received data with the PN code output from the PN code generating means. 11. The apparatus of claim 10, wherein the infrared data receiving apparatus comprises: synchronization processing means for driving control of the PN code generating means in synchronization with a PN code added to received data, a PN code added to the received data and the PN code; And a tracking processing means for driving control of the PN code generating means so that the phase of the PN code outputted from the code generating means is matched. The infrared data receiving apparatus according to claim 10 or 11, wherein the infrared data receiving apparatus includes receiving data determining means for determining whether or not the received data is input through the receiving means, and the PN code according to the determination result by the receiving data determining means. An infrared data transmitting and receiving device, characterized in that it further comprises a controller for controlling the operation of the generating means on / off. The infrared data transmitting / receiving apparatus according to claim 12, wherein the infrared data transmitting apparatus transmits predetermined data for synchronization and tracking processing before outputting data to be transmitted. 13. The infrared data according to claim 12, wherein the received data determining means comprises an integrating means for integrating the received received data and a comparing means for comparing the integrating level by the integrating means with a predetermined reference level. Transceiver. 15. The infrared data transmitting / receiving apparatus according to claim 10, 11 or 14, wherein the infrared data transmitting apparatus transmits predetermined data for synchronization and tracking processing before outputting data to be transmitted.