KR100202132B1 - Semiconductor dram structure - Google Patents

Abstract

The present invention relates to a semiconductor DRAM structure, and more particularly to a semiconductor DRAM structure that can increase the capacity by expanding the area of the semiconductor DRAM structure and the charge storage electrode, according to the present invention, the configuration of the semiconductor DRAM structure By forming a conventional stack capacitor structure, the wiring arrangement efficiency is increased, and the area of the charge storage electrode is increased by placing the bit line contacts in the center of four neighboring unit cells when the cells are arranged.

Description

Semiconductor DRAM structure

1 is a plan view of a semiconductor DRAM structure having a conventional stack capacitor structure manufactured according to a conventional method.

2 is a plan view of a semiconductor DRAM structure manufactured according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

A: active area B: bit line contact

C: charge storage electrode contact S: charge storage electrode

Technical Field of the Invention

The present invention relates to a semiconductor DRAM structure of the present invention, and more particularly, to a semiconductor DRAM structure capable of increasing a capacity by expanding an area of a charge storage electrode of a semiconductor DRAM structure.

[Prior art]

In general, memory devices used in logic semiconductor devices require high speed, and thus, full CMOS SRAMs having six transistors are widely used. However, full C-MORAM SRAM has a problem of relatively large cell size, and thus, DRAM devices using a small area are used to pursue high integration.

The DRAM device is focused on increasing the area of the charge storage electrode of the capacitor in order to increase the memory capacity, and a stack structure is used as a method for increasing the area.

The conventional stack capacitor DRAM is classified into a conventional stack capacitor structure and a bit line shielded stack capacitor depending on whether the bit line is located above or below the capacitor.

First, a conventional conventional stacked capacitor structure will be described with reference to FIG. 1 of the accompanying drawings. First, A shown in the drawing represents an active region of a semiconductor DRAM device, B represents a bit line contact, and C represents a charge. Means the contact of the storage electrode, and S represents the charge storage polarity.

A gate electrode and a source, a drain electrode (not shown), a charge storage electrode contact C, a charge storage electrode S, a bit line contact B, and a bit line (shown in an active region A) in one unit cell Not formed) is formed. The bit line contact B is positioned at the center of two neighboring cells, the charge storage electrode contact is located at the center of the unit cell, and is spaced apart from the charge storage electrode of the neighboring cell by a predetermined distance or more.

Although the bit line shield stack capacitor structure is not shown in the drawing, the bit line shield stack capacitor structure is located under the bit line capacitor. Since the bit line is formed before the capacitor forming step, an additional area required for connection in the cell after the capacitor formation is provided. This is not required, whereby the structure in which the capacity area in the cell can be maximized.

However, such a conventional stack capacitor structure has a limitation in increasing the electrode area of the capacitor since the capacitor is formed and then the bit line is formed, and further, a certain distance from the charge storage electrode and the plate electrode under the bit line contact. Since the capacitor area is to be spaced apart by a distance, there is a problem in that the storage area is reduced by reducing the space.

In addition, the bit line shield stack capacitor structure has to consider wiring layout efficiency in order to design a highly integrated device in a logical semiconductor device. In terms of wiring layout efficiency, the polyline used as a bit line in the bit line shield stack capacitor structure Since N can be used only in the N-MOS transistor region, there is a problem in that the wiring arrangement rate for constructing a logic circuit composed of a combination of an n-MOS transistor and a P-MOS transistor is greatly reduced.

[Technical problem to be achieved]

Therefore, in the DRAM cell structure included in the logic circuit, the conventional stack capacitor structure is used to increase the efficiency of wiring, and in addition, by arranging four unit cells adjacent to the bit line contacts in the cell arrangement, An object of the present invention is to provide a semiconductor DRAM structure capable of expanding the area of a charge storage electrode.

[Configuration and Function of Invention]

In order to achieve the above object of the present invention, the present invention provides an active region including a gate source and drain electrode of a semiconductor device, and a charge storage electrode contact and a charge storage electrode contact to which a source or drain electrode of the active region is connected. A charge storage electrode for charging the charge of the DRAM element, a plate electrode constituting a capacitor of the DRAM element with the charge storage electrode and the dielectric interposed therebetween, and a source or drain on the other side where the charge storage electrode and the plate electrode are shaped. A semiconductor DRAM device in which one unit cell including a formed bit line and a bit line contact are disposed adjacent to each other, the bit line contact being formed at an intersection point of the four unit cells neighboring each other; The charge storage electrode may be formed in the center of each unit cell, and a portion of the edge of the charge storage electrode disposed close to the bit line contact may be removed.

EXAMPLE

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view illustrating a semiconductor DRAM structure according to the present invention. As shown in FIG. 2, a gate electrode, a source, and a drain electrode (not shown) are formed in an active region A in one unit cell. , Charge storage electrode contact C, charge storage electrode S, bit line contact B and bit line (not shown) are formed. The bit line contact B is positioned at the center of four neighboring cells, and the charge storage electrode S is located at the center of each unit cell, and is disposed by a predetermined distance from the charge storage electrode of the neighboring cell. Are spaced apart. In order to be separated from the bit line contact B, only a portion of the corner portion is removed. At this time, the area of the part removed at the edge of the charge storage electrode is minute. In further detail, in forming the contact hole, a contact hole is formed by coating a photoresist film on the silicon, exposing and patterning the silicon, and etching to form a mask pattern. When viewed from the top view, the contact hole is formed in the shape of a square, the difference in area seems to be remarkable. 0.7 When forming a contact hole having a diameter below, a circular contact hole is formed by a rounding effect. As a result, in the case of the charge storage electrode, the area of the electrode edge is removed at the four corners according to the rounding effect and the proximity effect, and thus the area of the charge storage electrode is significantly larger than that of the conventional conventional stack capacitor structure. It can be confirmed through drawing.

[Effects of the Invention]

As described in detail above, according to the present invention, the semiconductor DRAM structure is formed as a conventional stack capacitor structure to increase wiring arrangement efficiency, and when the cell is arranged, the bit line contacts are positioned at the center of four neighboring unit cells. This increases the area of the charge electrode.

Claims (2)

An active region including a gate, a source, and a drain nation of the semiconductor device; A charge storage electrode contact connected to the source or drain electrode of the active region; A charge storage electrode connected to the charge storage electrode contact to charge a charge of a DRAM device; A plate electrode constituting a capacitor of a DRAM device with the charge storage electrode and a dielectric interposed therebetween; In a semiconductor DRAM structure in which one unit cell including a bit line and a bit line contact formed in a source or a drain on the other side where the charge storage electrode and the plate electrode are formed are adjacent to each other, the bit line contacts are adjacent to each other. The four unit cells are formed at an intersection point at which they are in contact; The charge storage electrode is formed in the center of each unit cell, the semiconductor DRAM structure, characterized in that a portion of the corner of the charge storage electrode disposed close to the bit line contact is removed. The semiconductor DRAM structure of claim 1, wherein the active region is a diagonal unit cell formed diagonally.