KR100201832B1 - Optical path controller with homogeneous stress distribution and the production method thereof - Google Patents

Abstract

Disclosed are a thin film actuated mirror array (TFAMA) having a uniform stress distribution for use in an optical image projection system and a method of manufacturing the same. The optical path adjusting apparatus prepares an active matrix to which an image signal voltage is applied, forms an actuator operated by the applied image signal voltage, and transfers an image signal voltage applied to the active matrix to the actuator. It is made by forming a via contact (Via Contact) to. The membrane layer of the actuator consists of silicon nitride (Si ₃ N ₄ ) deposited under a Plasma Enhanced Chemical Vapor Deposition (PECVD) process of about 25 ° C. to 400 ° C. and has a thickness of about 1 to 2 μm. . The deformation part of the actuator is made of zinc oxide (ZnO) deposited by a sol-gel method, a sputtering or a chemical vapor deposition process (Chemical Vapor Deposition = CVD), and has a thickness of about 0.7 to 2 m.

Description

Optical path control device having a uniform stress distribution and its manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film type optical path control device having a uniform stress distribution and a method of manufacturing the same. It relates to a manufacturing method.

In general, spatial light modulators, which are devices for projecting optical energy onto a screen, can be applied to various fields such as optical communication, image processing, and information display devices.

Typically, such devices are classified into a direct view type image display device and a projection type image display device according to a method of displaying optical energy on a screen.

An example of a direct view type image display apparatus is a CRT (Cathod Ray Tube). Such a CRT is called a CRT, which is excellent in image quality but difficult to enlarge a screen. That is, as the screen is enlarged, there is a problem that the weight and volume of the CRT increase, and thus the manufacturing cost increases.

The projection type image display apparatus includes a liquid crystal display (hereinafter referred to as LCD), a deformable mirror array (hereinafter referred to as DMD) and an actuated mirror array (hereinafter referred to as "DMD"). AMA)).

Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Although the transmission optical modulator as described above is a very simple optical device, it has low light efficiency due to the polarity of light and has drawbacks such as problems inherent in liquid crystal materials such as slow reaction and overheating. In addition, the maximum light efficiency of existing transmission optical modulators is limited to a range of 1-2% and requires dark room conditions to provide acceptable display quality.

Optical path control devices such as DMD and AMA have been developed to solve the problems of the LCD type optical path control devices.

DMD shows relatively good light efficiency, but serious fatigue problems are caused by the hinge structure employed in the DMD. In addition, very complex and expensive driving circuits are required in DMD.

In contrast, AMA is a piezoelectrically driven mirror array, which has a simple structure and principle of operation, and provides high optical efficiency of 10% or more. It also provides a sufficient contrast ratio to provide bright and clear images under normal room temperature light conditions. In addition, AMA is not only affected by the polarity of light, but also does not affect the polarity of light. Therefore, AMA is more efficient than LCD devices. In addition, since the reflective properties of the AMA are relatively less sensitive to temperature, AMA offers the advantage of improving the brightness of the screen over other devices that are easily affected by high power light sources.

This AMA was used as a display device in the early stages of development, mainly as a microactuator consisting of two vertical morphological structures. That is, it was used as a bulk AMA, a bonded vertical bulk piezoelectric wafer structure.

Such bulk AMAs were disclosed in US Pat. No. 5,175,465, issued December 31, 1992 to Gregory Um et al. Bulk AMA has a central electrode between two piezoelectric layers. The center electrode is connected to an active matrix having a conductive epoxy for the signal voltage. At the top of the bulk AMA is a mirror layer, which has an inclination angle of +/- 0.25 degrees under a voltage of up to 30 volts. For this reason, such a bulk AMA requires very high precision in design and manufacture, and there are many difficulties in assembling the structure.

Therefore, recently, a thin-film optical path control device has been newly developed to complete the quality of mirror arrays. For example, Korean Patent Application No. 95-13358, filed on May 26, 1995 by the present applicant, discloses such a thin film type optical path control device.

Thin film type optical path control devices are manufactured using thin film processes well known in the semiconductor industry. Thin film type light path control devices have been developed to transmit enough light on the screen to display digital images at high brightness and high contrast under normal room lighting conditions. Thin-film optical path control devices are reflective optical modulators using thin film piezo-electric actuators in conjunction with microscopic mirrors. Thin-film optical path control devices have been developed to obtain sufficient light efficiency to provide improved tilt angles and high brightness to provide high contrast. In addition, more than 300,000 pixels of a mirror made of a single panel have been developed to have uniformity of large scale integration.

The thin film type optical path control device is composed of panels of 640 x 480 pixels representing red, green and blue, respectively. The size of the individual pixels of the thin film optical path control device is, for example, 100 μm × 100 μm. The size of these pixels can be easily reduced to 50μm x 50μm to satisfy the resolution required for high-definition TV. Generally, 640 x 480 pixels are assembled on a 4 inch silicon wafer to make a single thin film optical path control module. Multiple thin-film optical path control module can be assembled on a 6 inch or 8 inch wafer down to the mirror pixel size required for good productivity and low production cost. The pixels are designed as cantilever structures to maximize the mirror surface area to increase light efficiency. Cantilever structures are made using micromachining and thin film fabrication techniques.

4, 5A and 5B show a conventional light path control device 10 made in the form of a cantilever structure. The optical path control device 10 largely includes an active matrix 12 to which an image signal voltage is applied and an actuator 40 operated by the applied signal voltage. The actuator 40 includes a membrane layer 20, a lower electrode 22, a deformable portion 24, which is a piezoelectric layer, and an upper electrode 26.

The manufacturing process of the conventional optical path control apparatus 10 will be briefly described with reference to FIGS. 5A and 5B as follows.

First, a protective layer 14 made of passivation phosphorosilicate glass (hereinafter referred to as PSG) is formed on the active matrix 12 to a thickness of about 1 μm. Next, an etching stopper 16, which is a silicon nitride (Si ₃ N ₄ ) layer, is deposited on the protective layer 14 to a thickness of about 2000 μs. After the etch stop layer 16 is deposited, a sacrificial layer 18 made of a high concentration of PSG is deposited. On the other hand, since the sacrificial layer 18 covers the surface of the active matrix 12, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 18 is planarized by using a conventional spin on glass (SOG) layer or chemical mechanical polishing (CMP). The surface of the sacrificial layer 18 is planarized and then scrubbed.

Next, the sacrificial layer 18 is patterned using a dry process or a wet process to create a support formation position. Thereafter, the membrane layer 20 made of silicon nitride (Si _x N _y ) is formed to a thickness of about 1 μm to 2 μm. The membrane layer 20 is deposited using a Low Pressure Chemical Vapor Deposition (hereinafter referred to as LPCVD) process in a furnace at about 700 to 800 ° C. After the membrane layer 20 has been formed, a buffered oxide etchant is used to clean the membrane layer 20 surface. Next, platinum (Pt) or platinum (Pt) / tantalum (Ta) is deposited on the membrane layer 20 by a thickness of about 500 to 2000 microseconds using a hot sputtering process. As a result, the lower electrode 22 which is a signal electrode is formed.

After the lower electrode 22 is formed, the lower electrode 22 is dry etched and patterned to separate the pixels. Thereafter, PZT (= Pb (Zr, Ti) O ₃ ) was about 0.7 to 2 μm using the sol-gel method, sputtering or chemical vapor deposition process (hereinafter referred to as CVD). The deformation part 24 is formed by laminating to a thickness of. Next, the deformation part 24 is phase-shifted by heat treatment using Rapid Thermal Annealing (RTA). Then, aluminum or platinum (Pt) having good reflectivity is deposited on the surface of the deformable portion 24 using a sputtering process or an evaporation process. As a result, the upper electrode 26 which is a common electrode is formed. In addition, in order to increase the light efficiency of the thin film type optical path control device, the center portion of the upper electrode 26 is cut off to form the groove 27.

After this step, the upper electrode 26, the deformable portion 24, the lower electrode 22, and the membrane layer 20 are sequentially patterned in a pixel shape. Next, in order to form a via contact 30 for electrically connecting the drain 32 of the active matrix 12 and the lower electrode 22, the membrane layer 20 and the etch stop layer 16 are formed. And the protective layer 14 is etched. After etching, the via hole 28 is formed. After the via hole 28 is formed, the via contact 30 is formed using a lift-off method. That is, the drain 32 and the lower electrode 22 are electrically connected to each other by filling the conductive material 36, for example, tungsten (W) or titanium (Ti), in the via hole 28.

Next, a metal thin film such as Pt / Ta is formed on the back surface of the semiconductor substrate, that is, the bottom surface of the active matrix 12 using a sputtering process. This forms an ohmic contact. Next, the silicon substrate is cut out to a desired shape for later thermal bonding (TCP bonding). Thereafter, in order to expose out bonding pads for thermocompression bonding, the sacrificial layer 18, the etch stop layer 16, and the protective layer 14 on the pad portion are dry etched. At this time, a passivation layer is applied over the sacrificial layer 18 with photoresist so as not to damage the device. When the sacrificial layer 18 is removed using hydrogen fluoride (HF) vapor, an air gap 18 'is formed. After removing the sacrificial layer 18, a rinse / dry treatment is performed. Finally, after the substrate on which the thin film type optical path control device is formed is completely cut out into a desired shape, a thin film optical path control device module is manufactured by TCP bonding.

On the other hand, in the conventional optical path control apparatus 10 manufactured as described above, the active matrix 12 is a semiconductor wafer on which a metal oxide semiconductor (MOS) switch array is made. The active matrix 12 contains M × N transistors (M and N are integers).

6 schematically illustrates some internal structures of the active matrix 12. Referring to the drawings, the process of forming the active matrix 12 will be briefly described. First, the surface of the silicon substrate 42 is oxidized to form a silicon oxide layer 44. The silicon oxide layer 44 is generally formed by charging a semiconductor wafer in an electric furnace and then heating it to a high temperature of 1,000 to 1,200 ° C while supplying oxygen gas or a mixture of oxygen gas and water vapor.

Next, the silicon oxide layer 44 is patterned by applying a photoresist (PR) protective layer (not shown) on the silicon oxide layer 44. Thereafter, in order to diffuse the n-type impurity in the region where the silicon oxide layer 44 has been selectively removed, a semiconductor wafer is loaded into the furnace, and an impurity source such as antimony (Sb) is injected and deposited. Thereafter, high temperature heat is applied in the diffusion path in order to distribute the deposited impurities to a suitable thickness and concentration inside the semiconductor wafer. As a result, a junction 54 is formed. Preferably, the junction 54 is a buried layer in which a high concentration of n-type impurities are diffused to reduce the resistance of the transistor.

After the junction 54 is formed, a titanium (Ti) layer 46 is deposited. Titanium layer 46 is deposited to increase the bond between the silicon substrate 42 and the titanium nitride (TiN) layer 48 to be deposited later. Once the titanium layer 46 is deposited, the Si atoms of the silicon substrate 42 combine with the titanium (Ti) atoms to form titanium silicate (TiSi ₂ ). As a result, the diffusion of Si atoms is greatly reduced.

After the titanium layer 46 is deposited, a titanium nitride (TiN) layer 48 is deposited. Titanium nitride (TiN) layer 48 prevents interdiffusion between Si atoms of silicon substrate 42 and tungsten (W) atoms of tungsten (W) layer 50 to be subsequently deposited, and the optical energy of the optical source When irradiated from the thin film type optical path control device, a photocurrent is deposited to prevent penetration of the current into the active matrix 12 and damaging the MOS switch array. After depositing the titanium nitride (TiN) layer 48, a photoresist (PR) protective layer is applied and patterned on the titanium nitride (TiN) layer 48, and then a tungsten (W) layer 50 is deposited. Let's do it.

As briefly described above, the active matrix 12 is stacked, and a tungsten (W) material drain 32 electrically connected to each transistor is formed on the surface of the active matrix 12.

However, Si atoms of the active matrix 12 may typically pass through the titanium nitride layer 48 and diffuse to the tungsten layer 50 as the temperature increases. For example, in the conventional thin film optical path control apparatus manufacturing process as described above, the membrane layer 20 (see FIGS. 5A and 5B) is formed using a low pressure chemical vapor deposition (LPCVD) process. The low pressure chemical vapor deposition (LPCVD) process is performed at a temperature of about 700 ° C. to 800 ° C. under a pressure of 0.1 to 10 Torr.

Therefore, in forming the membrane layer 20, the Si atoms of the active matrix 12 are moved horizontally to the localized region as indicated by arrow 52 due to the high temperature, and then vertically diffused upwardly to form tungsten (W). ) Combine with atoms. As such, if the diffusion motion of Si atoms occurs locally deeply, it leads to the destruction of the PN junction. That is, the horizontal spike (H) due to the horizontal movement of the Si atoms (H) and the vertical spike phenomenon (L) due to the vertical movement of the Si atoms occurs. Typically, the spike phenomenon takes place vigorously at temperatures above about 500 ° C. When such spike phenomenon occurs, the junction 54 may be cracked, and the junction 54 may be destroyed. As a result, the MOS semiconductor switch array is defective.

The present invention has been made to solve the above conventional problems, the first object of the present invention is to provide a thin film type optical path control apparatus having a uniform stress distribution.

A second object of the present invention is to provide a method of manufacturing a thin film type optical path control device having a uniform stress distribution.

In order to achieve the first object of the present invention as described above, the present invention,

(a) an active matrix to which an image signal voltage is applied;

(b) an actuator that operates by receiving an image signal voltage from an active matrix, the actuator comprising a layer of nitride that provides stability to the actuator and is deposited under a plasma-excited chemical vapor deposition process, the bottom electrode deposited on the membrane layer and functioning as a signal electrode An actuator having a strain portion deposited on the lower electrode and having a stress balancing function, and an upper electrode deposited on the strain portion and reflecting optical energy; And

(c) Provides an optical path adjusting apparatus including a via contact for transferring an image signal voltage applied to an active matrix to an actuator.

Preferably, the nitride consists of silicon nitride (Si ₃ N ₄ ).

Preferably, the membrane layer has a thickness of 1 to 2 μm, and the lower electrode is made of tantalum (Ta) or platinum (Pt) / tantalum (Ta) and has a thickness of 500 to 2,000 GPa. The deformation part is made of zinc oxide (ZnO) and has a thickness of 0.7 to 2 μm, and the upper electrode is made of aluminum (Al) or silver (Ag) and has a thickness of 500 to 2,000 μm.

In addition, in order to achieve the second object of the present invention described above, the present invention,

(a) providing an active matrix to which an image signal voltage is applied;

(b) forming a membrane layer of nitride deposited on the active matrix under a plasma-excited chemical vapor deposition process to provide stability;

(c) depositing the bottom electrode on the membrane layer;

(d) depositing a strain having a stress balancing function on the lower electrode;

(e) depositing an upper electrode that reflects optical energy on the deformable portion;

(f) patterning the membrane layer, the lower electrode, the deformable portion, and the upper electrode to complete an actuator having the stability; And

(g) forming a via contact for transmitting the image signal voltage applied to the active matrix to the actuator.

Preferably, before forming the membrane layer, a protective layer is deposited on the active matrix and an etch stop layer is deposited on the protective layer. Next, after depositing a sacrificial layer on the etch stop layer, a membrane layer is deposited on the sacrificial layer. The protective layer is formed by diffusing phosphorus on the surface of the silicon oxide layer (SiO ₂ ) of the active matrix, and the etch stop layer is formed by depositing nitride on the protective layer using a low pressure chemical vapor deposition process. The sacrificial layer is formed by depositing a high concentration of passivation silicate glass on the etch stop layer using an atmospheric pressure chemical vapor deposition process.

The deformable portion is formed by depositing a zinc oxide (ZnO) layer on the lower electrode by using a sol-gel method, sputtering, or CVD, followed by heat treatment.

In addition, the lower electrode deposits platinum (Pt) or platinum (Pt) / tantalum (Ta) on the membrane layer by using a high-temperature sputtering process, and depositing the upper electrode may be performed by using a sputtering process or a deposition process. It is formed by depositing aluminum (Al) or silver (Ag) on the electrode.

As described above, in the thin film type optical path control apparatus and the manufacturing method thereof according to the present invention, zinc oxide (ZnO) having a low process temperature is laminated to form a deformation portion, and in this connection, a PECVD process is performed before forming the deformation portion. The membrane layer can be laminated. Therefore, the membrane layer can be deposited at a low temperature of 400 ° C or lower as compared with the conventional thin film type optical path control device manufacturing process. As a result, it is possible to effectively prevent the junction spike phenomenon of the active matrix actively occurring at a temperature of 500 ° C. or more, and to maintain the stress of the thin film type optical path control device uniformly.

1 is a cross-sectional view of an optical path control apparatus according to the present invention.

2 is a cross-sectional view of an optical path control apparatus according to the present invention showing a state of depositing a membrane layer on a sacrificial layer.

3 is a cross-sectional view of the optical path control apparatus according to the present invention showing a state in which the deformation portion is deposited on the lower electrode.

4 is a perspective view of a conventional optical path adjusting device.

FIG. 5A is a cross-sectional view taken along the line VV of FIG. 4.

5B is a cross-sectional view showing a state before etching the sacrificial layer shown in FIG. 5A.

FIG. 6 is a schematic view illustrating some internal structures of the active matrix shown in FIG. 5A.

<Explanation of symbols for main parts of drawing>

10,100: optical path control device 12,112: active matrix

14,114: protective layer 16,116: etch stop layer

18,118: sacrificial layer 18 ': air gap

20,120: membrane layer 22,122: lower electrode

24,124: deformation part 26,126: upper electrode

28: beer hall 30,130: beer contact

32,132 Drain 36,136 Conductive material

40, 140: actuator 42: silicon substrate

44 silicon oxide layer 46 titanium layer

48: titanium nitride layer 50: tungsten layer

54: junk

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 3 schematically show the optical path control device 100 according to the present invention. The optical path control device 100 includes an active matrix 112 and an actuator 140. The active matrix 112 is a semiconductor wafer from which a simple MOS switch array is made, similar to the active matrix used on LCD panels. Each mirror pixel has a corresponding transistor switch in this switch array. In other words, the active matrix 112 contains M × N transistors. In addition, a drain 132 electrically connected to each transistor is formed on the surface of the active matrix 112.

The actuator 140 includes a membrane layer 120, a lower electrode 122, a deformation portion 124 that is a piezoelectric layer, and an upper electrode 126. The inclination angle of the actuator 140 varies linearly according to the applied voltage, and has an almost instantaneous frequency response characteristic. Actuator 140 has a maximum inclination angle of 3 degrees when a maximum voltage of 10V is applied. Preferably, actuator 140 has a maximum tilt angle of 5 degrees.

The manufacturing process of the thin film type optical path control apparatus 100 according to the present invention will be described in detail with reference to FIGS. 1 to 3 as follows.

First, an active matrix 112, which is a MOS that has a feature of increasing the degree of integration and is widely used in a large scale integrated circuit as a semiconductor memory device, is provided. Next, the protective layer 114 is formed to a thickness of about 1 μm on the silicon wafer on which the P-type MOS is formed. The protective layer 114 is made of a passivation phosphorus silicate glass made by diffusing phosphorus on the surface of the silicon oxide film (SiO ₂ ).

Next, the etch stop layer 116, which is a silicon nitride (Si ₃ N ₄ ) layer, is deposited on the protective layer 114 to a thickness of about 2000 kPa. The etch stop layer 116 is deposited using a low pressure chemical vapor deposition (LPCVD) process in which a thin film is deposited. That is, the etch stop layer 116 is formed by depositing a nitride layer on the protective layer 114 using a simple thermal energy chemical reaction in a low pressure (200 to 700 mTorr) reaction vessel.

After the etch stop layer 116 is deposited, the sacrificial layer 118 is deposited. The sacrificial layer 118 serves to facilitate lamination to form a thin film optical path control device module, and is removed by hydrogen fluoride (HF) solution after lamination is complete. The sacrificial layer 118 is a high concentration of silicate glass (PSG), and is formed to a thickness of about 1 μm using an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process. That is, the sacrificial layer 118 is deposited using a simple thermal energy chemical reaction in a reaction vessel under atmospheric pressure (760 mm Torr). On the other hand, since the sacrificial layer 118 covers the surface of the active matrix 112 on which the P-MOS is formed, the surface flatness is very poor. Thus, the surface of the sacrificial layer 118 is planarized using a spin on glass (SOG) layer of siloxane or silicate mixed in an alcohol-based solvent, or the sacrificial layer 118 using chemical mechanical polishing (CMP). ) Flatten the surface. Preferably, the surface of the sacrificial layer 118 is planarized using a CMP process, and then scrubbing is performed.

Next, the sacrificial layer 118 is patterned using a dry or wet process to create a support formation location. That is, the sacrificial layer 118 is etched using, for example, an etching solution such as hydrogen fluoride (HF) solution, or the sacrificial layer 118 is etched using a plasma or an ion beam to form a support formation position.

Thereafter, the membrane layer 120 made of silicon nitride is formed to a thickness of about 1 μm to 2 μm. The membrane layer 120 is for stabilizing the actuator 140. That is, the membrane layer 120 made of silicon nitride functions to block the oxide film growth in the active region when the oxide film is grown in the field region. The membrane layer 120 is deposited using a plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD) process. Typically, PECVD is performed at a temperature of 400 ° C. or less. At this time, by forming the membrane layer 120 while changing the ratio of the reactive gas by time in the reaction vessel of a low pressure, the stress of the thin film type optical path control device is controlled.

After the membrane layer 120 is formed as shown in FIG. 2, the surface of the membrane layer 120 is formed by using a buffered oxide etchant mainly used for etching oxides as a mixed chemical of NH ₄ F and HF. Clean. Next, as shown in FIG. 3, platinum (Pt) or platinum (Pt) / tantalum (Ta) is deposited on the membrane layer 120 by a thickness of about 500 to 2000 microseconds using a high temperature sputtering process. As a result, the lower electrode 122 which is a signal electrode is formed.

After the lower electrode 122 is formed, the lower electrode 122 is dry etched and patterned to separate the pixels. Thereafter, zinc oxide (ZnO) having a low process temperature is laminated to a thickness of about 0.7 to 2 μm by using a sol-gel method, sputtering, or CVD to form a deformation part 124. Next, the phase change by heat treatment using RTA (Rapid Thermal Annealing). Thereafter, sputtering or vapor deposition is used to sputter aluminum (Al) or platinum (Pt) having good reflectivity on the surface of the deformable portion 124. As a result, an upper electrode 126 that is a common electrode is formed.

Next, in order to form a pixel, the upper electrode 126, the deformable portion 124, the lower electrode 122, and the membrane layer 120 are sequentially patterned. That is, the upper electrode 126 is etched using the photoresist (PR) protective layer 134 resistant to the material to be etched on the upper electrode 126 as a mask. After etching the upper electrode 126, the photoresist (PR) protective layer 134 is applied on the upper electrode 126 and the deformable portion 124, and then the deformable portion 124 is etched. In this manner, after etching the deformable portion 124, the lower electrode 122 and the membrane layer 120 are sequentially patterned in a pixel shape.

After the patterning is completed, as described above, the membrane layer 120, the etch stop layer 116, and the protective layer 114 are removed from the formation position of the via hole 128 to form a complete via hole 128. Etch sequentially in the same manner.

When the etching is completed and the via hole 128 is formed, a photoresist (PR) protective layer is applied to the via hole 128 and the conductive material 136 is filled into the via hole 128 using a high temperature sputtering process. Let's do it. In other words, the conductive tungsten (W) or titanium (Ti) is filled in the via hole 128 using a metal sputtering process. As such, by filling the via hole 128 with tungsten (W) or titanium (Ti) as the conductive material 136, the drain 132 and the lower electrode 122 are electrically connected. As a result, the via contact 130 is formed.

After the stacking of the thin film type optical path control device is completed through the above steps, a metal such as Pt / Ta is formed on the back surface of the semiconductor substrate, that is, the bottom surface of the active matrix 112 using a sputtering process for electrical characteristics of the P-MOS circuit. Form a thin film. This forms a resistance contact. Next, a photoresist (PR) protective layer is coated on the front surface of the pixel-patterned substrate up to the membrane layer 120 to protect the device, and then silicon in a desired shape for later TCP bonding. Cut out the substrate. When cutting the substrate, however, the substrate is not cut completely, but only up to one third of the thickness for subsequent processing.

Next, in order to expose the out bonding pad for thermocompression bonding, dry etching of the sacrificial insect 118, the etch stop layer 116, and the protective layer 114 on the pad portion is performed. On the other hand, when removing the sacrificial layer 118, a protective layer is applied with a photoresist in order not to damage the device. The sacrificial layer 118 is then removed using hydrogen fluoride (HF) vapor, followed by a rinse / dry treatment. When the sacrificial layer 118 is removed, an air gap 118 'is formed. Finally, after the substrate on which the thin film type optical path control device is formed is completely cut out into a desired shape, a thin film optical path control device module is manufactured by TCP bonding.

As described above, in the thin film type optical path control apparatus according to the present invention, zinc oxide (ZnO) having a low process temperature is laminated to form the deformation portion 124, and in this regard, the PECVD process before the formation of the deformation portion 124. The membrane layer 120 may be laminated using the same. Therefore, the membrane layer 120 can be deposited at a low temperature of 400 ° C. or lower as compared with the conventional thin film type optical path control device manufacturing process. As a result, it is possible to effectively prevent the junction spike phenomenon of the active matrix 112 actively occurring at a temperature of 500 ° C or more, and to maintain the stress of the thin film type optical path control device uniformly.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (10)

(a) an active matrix 112 to which an image signal voltage is applied; (b) an actuator 140 which operates by receiving the image signal voltage from the active matrix 112, which provides a stability to the actuator 140 and comprises a membrane layer of nitride deposited under a plasma-excited chemical vapor deposition process ( 120, a lower electrode 122 deposited on the membrane layer 120 and functioning as a signal electrode, a deformation part 124 deposited on the lower electrode 122 and having a stress balancing function, and the deformation part ( An actuator 140 deposited on 124 and having an upper electrode 126 that reflects optical energy; And and (c) a via contact (130) for transferring said image signal voltage applied to said active matrix (112) to said actuator (140). The apparatus of claim 1, wherein the nitride is silicon nitride (Si _x N _y ). According to claim 1, wherein the membrane layer 120 has a thickness of 1 to 2μm, the lower electrode 122 is made of tantalum (Ta) or platinum (Pt) / tantalum (Ta) of 500 to 2,000Å Light path control device characterized in that it has a thickness. According to claim 1, wherein the deformable portion 124 is made of zinc oxide (ZnO) and has a thickness of 0.7 to 2μm, the upper electrode 126 is made of aluminum (Al) or silver (Ag) and 500 to An optical path control device having a thickness of 2,000 kHz. (a) providing an active matrix to which an image signal voltage is applied; (b) forming a membrane layer of nitride deposited on the active matrix under a plasma-excited chemical vapor deposition process to provide stability; (c) depositing the bottom electrode on the membrane layer; (d) depositing a strain having a stress balancing function on the lower electrode; (e) depositing an upper electrode that reflects optical energy on the deformable portion; (f) patterning the membrane layer, the lower electrode, the deformable portion and the upper electrode to complete an actuator having the stability; And (g) forming a via contact for transferring said image signal voltage applied to said active matrix to said actuator. The method of claim 5, wherein the manufacturing method of the optical path control device comprises: depositing a protective layer on the active matrix before forming the membrane layer, depositing an etch stop layer on the protective layer, wherein the etch stop layer And depositing a sacrificial layer on said sacrificial layer, wherein said membrane layer is deposited on said sacrificial layer. The method of claim 6, wherein depositing the protective layer is performed by diffusing phosphorus on a surface of a silicon oxide layer (SiO ₂ ) of the active matrix, and depositing the etch stop layer using the low pressure chemical vapor deposition process. Depositing nitride on the protective layer, and depositing the sacrificial layer depositing a high concentration of passivation silicate glass on the etch stop layer using an atmospheric pressure chemical vapor deposition process. The method of claim 5, wherein the depositing of the strain portion comprises depositing a zinc oxide (ZnO) layer on the lower electrode using a process selected from the group consisting of sol-gel method, sputtering, and chemical vapor deposition. Method of manufacturing an optical path control device characterized in that the heat treatment after deposition. The method of claim 5, wherein the depositing of the lower electrode comprises depositing platinum (Pt) or platinum (Pt) / tantalum (Ta) on the membrane layer using a hot sputtering process, and depositing the upper electrode. Is depositing aluminum (Al) or silver (Ag) on the deformable portion using a process selected from the group consisting of sputtering and evaporation. The method of claim 5, wherein the plasma excited chemical vapor deposition process is performed at a temperature ranging from room temperature to 400 ° C. 7.