KR100200506B1 - Scan-chain order change apparatus - Google Patents

Abstract

The present invention relates to a scan chain reordering apparatus of a magnetic test circuit, and more particularly, to an interconnect matrix for outputting test data input in response to a scan chain sequence control signal to a scan chain. And a plurality of scan chains that are ordered by the interconnect matrix and test peripheral circuits by test data output through the interconnect matrix.

Thus, the present invention can adjust the contents of the flip-flop in the memory test circuit to adjust the connection content of the interconnect matrix so that the order of the scan shift chain between each scan chain in the circuit outside the memory test circuit can be arbitrarily adjusted This method has an effect that only a specific scan chain can be used as a scan shift chain

Description

Scan chain change order device of magnetic test circuit

FIG. 1 is a diagram showing an apparatus for changing the scan chain order of a magnetic test circuit according to the present invention. FIG.

Figure 2 shows the internal structure of the interconnect matrix shown in Figure 1;

Figure 3 shows the internal structure of the switching means shown in Figure 2;

FIG. 4 is an exemplary diagram for explaining an arbitrary adjustment of the order of scan chains when testing peripheral circuits using three scan chains in the scan chain reordering apparatus of the magnetic test circuit shown in FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

100: interconnect matrix 200a to 200c: scan chain

110a to 110d: Switching parts 112a to 112d:

114a to 14d: Decoders 116a to 116d:

The present invention relates to a scan chain reordering apparatus for a magnetic test circuit. In particular, the order of each scan chain can be arbitrarily adjusted by the scan chain reordering control data input from the outside by inserting an additional circuit in a test circuit, And the hold violation caused by a phase deviation between clock inputs of the flip-flop provided in the scan flip-flop can be removed without re-checking the circuit.

For efficient testing of semiconductors, design circuits for various tests have been developed and used in semiconductor design. Among them, scan test methods are widely used.

The scan test is a method of replacing a common flip-flop with a scan flip-flop and composing it into one or more shift chains. However, because the delay between the adjacent flip-flops is very small, the shift violation may occur when there is a phase difference between the clock inputs of the flip-flops. However, when designing a circuit, it is common that the flip-flops provided in the same scan chain are disposed adjacent to each other. Therefore, the phase deviation between the flip-flops in the same scan chain will be relatively small. However, the phase deviation between the clock inputs of the flip-flops belonging to different scan chains becomes relatively large, which may cause hold violation.

Since the phase deviation is relatively small between the flip-flops in the same scan chain, it is considered that the hold violation due to the phase deviation does not occur frequently in one scan chain. However, the hold violation that occurs between the different scan chains There was a problem that it could not be avoided.

It is an object of the present invention to shorten the clock input of the scan chain in the rear side of the scan chain clock input to eliminate the hold violation due to the phase deviation between each scan chain clock input, The scan chain of the magnetic test circuit which eliminates the hold violation occurring between each scan chain by arbitrarily adjusting the order of the scan chains according to the data by inputting the scan chain change control data from the outside without modifying the circuit, Order change device.

According to another aspect of the present invention, there is provided an apparatus and method for controlling a scan chain, the apparatus comprising: an interconnect matrix for outputting test input data input in response to a scan chain sequence control signal to a scan chain; And a plurality of scan chains for testing the peripheral circuit by the test input data.

The interconnect matrix may comprise a plurality of switching means.

Wherein the switching means includes: a shift register for receiving switching driving control data from the outside, shifting the data by a shift pulse, and outputting the shifted data; A decoder for driving only one of the plurality of switching means in response to data output from the shift register; And a switch driven by the data output from the decoder and outputting test data to the scan chain means.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

(100) for outputting test data input in response to a scan chain sequence control signal to a scan chain, and a control unit for controlling the scan chain, which is ordered by the interconnect matrix (100) And a plurality of scan chains 200 for testing peripheral circuits by outputting test input data.

The interconnect matrix 100 comprises switches 110, 120 and 130 having a plurality of input and output terminals.

The switching units 110, 120 and 130 include a shift register 112 for receiving switching driving control data from the outside and shifting and outputting the data by shift pulses, And a switch 116 which is driven by the data output from the decoder 114 and outputs the test data to the scan chain 200.

1 is a block diagram of a scan chain reordering apparatus of a magnetic test circuit according to an embodiment of the present invention. Referring to FIG. 1, Matrix 100 and connects the test signal (Sin) input and the test output (Sout) output of each scan chain in the circuit to the interconnect matrix 100.

The order of the scan shift chains between each scan chain is determined by the internal connection state of the interconnect matrix 100.

Therefore, the order of the scan flip-flops is determined so that the delay from the circuit design to the clock input of the flip-flops of each scan chain is located in front of the large scan chain.

Figure 2 shows the internal structure of the interconnect matrix 100 shown in Figure 1 wherein the input stages A0-An of the interconnect matrix 100, when there are N scan chains 200 in the circuit, And has a one-to-one mapping function to the scan chains 200 through the output stages Y0 to Yn. To implement this, N + 1 connections are made to the switching unit 110 having 1 to N + 1 switches 116 for the interconnect matrix 100 having N + 1 inputs.

As shown in FIG. 3, the switching unit 110 includes N + 1 switches 116, a decoder 114, and a shift register 112. In order to control each switch 116, (114), since only one of the (N + 1) switches 116 is active at any given time. The input of the decoder 114 is taken in the shift register 112, and the connection state of the switch 116 is determined according to the contents of the register 112.

The shift registers 112 of the N + 1 switching units 110 in the interconnect matrix 110 are constituted by one shift chain and the contents of the shift registers 112 are connected to the shift registers 112 ) To the outside of the test circuitry and to the outside to connect the serial data output stage to increase the test efficiency of the interconnect matrix 100. [

The above-mentioned contents will be briefly described as follows.

FIG. 4 is an exemplary diagram for explaining an arbitrary adjustment of the order of scan chains when testing peripheral circuits using three scan chains in the scan chain reordering apparatus of the magnetic test circuit shown in FIG. 1 The scan chain change control signal 1001011 is input so that the switch control signal of the decoder has 0010 (116a), 0001 (116b), 0100 (116c), and 1000 (16d) for each switch. Then, in the first switch unit, only the second switch 116b is turned on by the decoder 114a, so that the test input signal Sin is input to the first input terminal A0 of the interconnect matrix 100, And outputs it to the second scan chain 220.

The result of testing the peripheral circuit by the flip flops F1 to F6 of the second scan chain 220 is input to the second input terminal A2 of the interconnect matrix 100. [ In the third switch, only the third switch 116c is turned on to output the input data through the input terminal A2 to the third scan chain 230 through the output terminal Y2. The results of testing the peripheral circuits by the flip flops F1 to F6 of the third scan chain 230 are input to the input terminal A3 of the interconnect matrix 100. In the fourth switch unit, 116d are turned on to output the final test result signal through the output terminal Y3 of the interconnection matrix 100 via the input terminal A3.

The contents of the flip-flop can be adjusted in the test circuit to adjust the connection content of the interconnect matrix so that the order of the scan shift chain between each scan chain in the circuit outside the test circuit can be adjusted. Only the scan chain can be used as a scan shift chain.

Claims (1)

An interconnect matrix having a plurality of switching means for outputting test data input in response to a scan chain sequence control signal to a scan chain; And a plurality of scan chains that are ordered by the interconnect matrix and test peripheral circuits by test data output through the interconnect matrix, A shift register for receiving control data, shifting the data by shift pulses, and outputting the shifted data; A decoder for driving only one of the plurality of switching means in response to data output from the shift register; And a switch that is driven by data output from the decoder and outputs test data.