KR100197995B1 - Sam redundancy circuit of a dual port memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling redundancy circuit for dual port memories, and in particular, to improve repair efficiency of sampling ports. A first spare column pass transistor means for turning on by the first spare column pass signal to transfer the first spare column data to the spare sam area as a means for achieving the above object, and a second spare column pass A second spare column pass transistor means for turning on the signal and transferring second spare column data to the spare sam area; and storing the first spare column data or the second spare column data. Spare SAM circuit means for outputting to the spare data bus line and the spare data bus line through two NMOS transistors turned on by an output signal of a 5 NAND gate, and an output signal of the fifth NAND gate. The first spare column data or the second spare column that is turned on by the second memory and is stored in the spare sam circuit. A spare SAM pass transistor means for transferring data to the spare data bus line and the spare data bus line, and a first spare column pass signal inverted so as to be input to one input terminal of the first NAND gate of the flip-flop circuit portion. A first inverter for outputting a signal, a second inverter for outputting a low signal to one input terminal of a second NAND gate of the flip-flop circuit part by inverting the second spare column pass signal, and the first inverter or the first inverter 2, a flip-flop circuit section for outputting a high signal to each input terminal of the third NAND gate or the fourth NAND gate by inputting the output signal of the inverter as an input, and the first serial counter signal is applied to the gate. A first redundant sam fuse box for cutting the fuse and outputting a first spare sam column line selection signal; 2 When the serial counter signal is applied to the gate, the second redundant sam fuse box for cutting the fuse and outputting the second spare sam column line selection signal, the output signal of the first redundant sam fuse box part, and the flip-flop circuit part; A third NAND gate for outputting a low signal to one input terminal of the fifth NAND gate by using an output signal of a first NAND gate, an output signal of the second redundant sample fuse box unit, and a second NAND of the flip-flop circuit unit A fourth NAND gate for outputting a low signal to one input terminal of the fifth NAND gate by inputting an output signal of the gate as an input, an output signal of the third NAND gate, and an output signal of the fourth NAND gate as inputs And a fifth NAND gate for turning on two transistors of the spare sam pass transistor unit.

Description

Dual Redundancy Memory Redundancy Circuit

1 is a block diagram of a dual port memory in a conventional low density.

2 is a block diagram of a dual port memory in a conventional low density.

3 is a sample redundant circuit diagram at the dual port shown in FIG.

4 is a sample redundant circuit diagram according to an embodiment of the present invention.

5 is an operation timing diagram according to an embodiment of the present invention shown in FIG.

* Explanation of symbols for main parts of the drawings

DESCRIPTION OF SYMBOLS 1 First spare column pass transistor part 2 Second spare column pass transistor part

3: Spare Sam circuit part 4: Flip-flop circuit part

5: Spare Sam Pass Transistor Section St1: First Spare Column Pass Signal

St2: Second spare column pass signal EN1: First enable signal

EN2: second enable signal Vcc: power supply voltage

Vss: Ground Voltage SDB: Spare Data Bus Line

/ SDB: / Spare data bus line MN: NMOS transistor

MP: PMOS transistor IV: Inverter

ND: Nand Gate

The present invention relates to a SAM redundancy circuit of dual port memory, and more particularly, to a redundancy circuit for repairing defective column lines having different column line selection signals with one spare sample.

In general, dual port memory is one of graphic application memories and includes a DRAM port and a SAM port.

FIG. 1 is a configuration diagram of a dual port memory at a low density, which is a chip structure used at low density, and each spring exists in each DRAM array. In this case, since there is one SAM in the DRAM array, the repair efficiency is good, but the chip area is large.

FIG. 2 is a configuration diagram of a DRAM port and a sam port at a high integration level in the related art, in which two DRAM arrays share one fountain. In this case, since one fountain shares two DRAM arrays, the chip area is reduced while the repair efficiency is lowered.

FIG. 3 is a sample redundant circuit diagram of the dual port shown in FIG. 2, and when a defect occurs in the first normal column line, the second normal column line is also repaired with the first normal column line and the second normal column. Repair is not possible if the column addresses of the lines are different.

Therefore, in the present invention, when a data is transmitted from DRAM to SAM, the redundant SAM decoder stores whether the data of the first DRAM port or the second DRAM port is data, and determines whether it is from a DRAM port having a defective column line or not, and thus one spare. It is an object of the present invention to provide a redundancy circuit of dual port memory for repairing defective column lines having different column line selection signals.

The SAM redundancy circuit of the present invention for achieving the above object comprises a first spare column pass transistor means for being turned on by the first spare column pass signal to transfer the first spare column data to the spare sam area; Second spare column pass transistor means for being turned on by a second spare column pass signal to transfer second spare column data to the spare fountain (SAM), and the first spare column data or second spare column; Spare SAM circuit means for storing data and outputting the data to the spare data bus line and the spare data bus line through two NMOS transistors turned on by the output signal of the fifth NAND gate; First spare column data that is turned on by an output signal of a NAND gate and stored in the spare sam circuit unit. A spare SAM pass transistor means for transferring second spare column data to the spare data bus line and / or the spare data bus line, and inverting the first spare column pass signal to convert the first spare column pass signal to the first NAND gate of the flip-flop circuit unit. A first inverter for outputting a low signal to one input terminal, a second inverter for outputting a low signal to one input terminal of a second NAND gate of the flip-flop circuit part by inverting the second spare column pass signal, and the second inverter A flip-flop circuit section for outputting a high signal to one input terminal of the third NAND gate or the fourth NAND gate, respectively, by inputting an output signal of the first inverter or the second inverter as an input, and a first serial counter signal; Is applied to the gate, the first redundant to cut the fuse to output the first spare sam column line selection signal A second fuse box, a second redundant sam fuse box for outputting a second spare sam column line selection signal by cutting the fuse when the second serial counter signal is applied to the gate, and an output signal of the first redundant sam fuse box part; A third NAND gate for outputting a low signal to an input terminal of a fifth NAND gate by inputting an output signal of the first NAND gate of the flip-flop circuit unit, an output signal of the second redundant sample fuse box unit, and the flip A fourth NAND gate for outputting a low signal to one input terminal of the fifth NAND gate by inputting an output signal of the second NAND gate of the flop circuit unit, an output signal of the third NAND gate, and an output signal of the fourth NAND gate A fifth NAND gate for turning on two transistors of the spare sampling path transistor unit using an output signal as an input is included. And it characterized in that.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a sample redundant circuit diagram according to an embodiment of the present invention, and is turned on by a first spare column pass signal St1 to transfer first spare column data to a spare sam area. The second spare column pass transistor unit 1 is turned on by the spare column pass transistor unit 1 and the second spare column pass signal St2 to transfer second spare column data to the spare sam area. (2) and the spare data through the two NMOS transistors MN21 and MN22 stored in the first spare column data or the second spare column data and turned on by the output signal of the fifth NAND gate ND5. A spare thumb circuit section 3 for outputting to a bus line SDB and a spare data bus line / SDB, and an output signal of the fifth NAND gate ND5 to turn on the spare thumb circuit section 3. Save to) A spare sample pass transistor section 5 for transferring the first spare column data or the second spare column data to the spare data bus line SDB and the spare data bus line / SDB, and the first spare column data. The first inverter IN1 and the second spare column pass signal St2 for inverting the pass signal St1 and outputting a low signal to one input terminal of the first NAND gate ND1 of the flip-flop circuit unit 4. The second inverter IV2 for outputting a low signal to one input terminal of the second NAND gate ND2 of the flip-flop circuit unit 4, and the first inverter IV1 or the second inverter IV2. And a flip-flop circuit section 4 for outputting a high signal to one input terminal of the third NAND gate ND3 or the fourth NAND gate ND4 by inputting an output signal of When a signal is applied to the gate A first redundant sample fuse box for cutting the first spare sam column line selection signal and a second redundant sample for cutting the fuse when the serial counter signal is applied to the gate to output the second spare sample column line selection signal; One input terminal of the fifth NAND gate ND5 is used as an input signal of the fuse fuse, the output signal of the first redundant sample fuse box unit, and the output signal of the first NAND gate ND1 of the flip-flop circuit unit 4. A fifth NAND gate ND3 for outputting a low signal, an output signal of the second redundant sample fuse box unit, and an output signal of the second NAND gate ND2 of the flip-flop circuit unit 4 as inputs; A fourth NAND gate ND4 for outputting a low signal to one input terminal of the NAND gate ND5, an output signal of the third NAND gate ND3, and an output signal of the fourth NAND gate ND4. It is composed of a fifth NAND gate ND5 for turning on two transistors of the spare thumb pass transistor section 5 as an input.

The first spare column pass transistor unit 1 includes a sixteenth NMOS transistor MN16 connected to a high potential line HL and a fifteenth NMOS transistor MN15 connected to a low potential line LL. .

The second spare column pass transistor unit 1 includes an eighteenth NMOS transistor MN18 connected to a high potential line HL and a seventeenth NMOS transistor MN17 connected to a low potential line LL. .

The spare sam circuit unit 3 is a third PMOS to which a first or second data signal transmitted through a low potential line LL is applied to a gate, and is connected between a power supply voltage Vcc and the high potential line HL. A nineteenth NMOS connected to the transistors MP3 and a first or second data signal transferred through the low potential line LL to a gate and connected between the high potential line HL and a ground voltage Vss. A fourth transistor connected to the transistor MN19 and a first or second data signal transmitted through the high potential line HL to a gate and connected between the power supply voltage Vcc and the low potential line LL. A PMOS transistor MP4 and a first or second data signal transferred through the high potential line HL to a gate, and connected between the low potential line LL and the ground voltage Vss. 20 NMOS transistors MN20.

The spare sample pass transistor unit 5 has a 21st NMOS transistor (5) connected to the high potential line HL and the spare data bus line SDB to which an output signal of the fifth NAND gate ND5 is applied as a gate. MN21 and an output signal of the fifth NAND gate ND5 to the gate are applied to the 22nd NMOS transistor MN22 connected between the low potential line LL and the spare data bus line / SDB. It is composed.

Hereinafter, an operation according to the configuration will be described as an example.

When the first defective column line is present in the first DRAM port and the second defective column line is present in the second DRAM port, the first redundant sample fuse is the first spare column line, and the second redundant sample fuse is the second spare column. Program the line so that the first enable signal EN1 goes high when the serial counter output SC becomes equal to the first spare column line and the second enable when the serial counter output SC becomes equal to the second spare column line. The signal EN2 goes high. When the data of the first DRAM port is transferred to the sam, the first spare column pass signal St1 becomes high and the output signal of the first NAND gate of the flip-flop becomes high to maintain the high state until the next data transfer occurs. Will be maintained. Subsequently, when the serial counter output SC becomes the same as the first spare column line during the serial read cycle, the first enable signal EN1 becomes high. Thus, the output of the fifth NAND gate ND5 is decreased. It will go high and the spare fountain will be selected. After that, when the serial counter output SC becomes equal to the second spare column line, the second enable signal EN2 becomes high, but the output signal of the second NAND gate ND2 of the flip-flop is low. Sam is not chosen.

Meanwhile, the same applies to the case where the data of the second DRAM port is transmitted to the fountain, and thus the description thereof will be weak.

FIG. 5 is an operation timing diagram according to an embodiment of the present invention shown in FIG. 4. When the first spare column pass signal St1 rises high while the / RAS signal falls low, the first NAND of the flip-flop is shown in FIG. Since the output signal of the gate ND1 is kept high for a predetermined time, the data transfer cycle from the DRAM port to the sam port ends. Subsequently, in the serial read cycle, when the serial counter output SC becomes equal to the first defective column line, the first enable signal EN1 becomes high to output the output signal of the fifth NAND gate ND5. Enable Spare Sam by going high. On the other hand, when the serial counter output SC becomes equal to the second defective column line, the second enable signal EN2 becomes high and the output signal of the fifth NAND gate ND5 becomes high, thereby enabling the spare thumb. .

As a result, the present invention can replace two defective column lines with one spare fountain.

As described above, implementing the redundancy circuit of the dual-port memory of the present invention in the semiconductor memory device can reduce the chip area and increase the redundancy efficiency twice as compared to the conventional method, thereby contributing to the improvement of the yield.

Preferred embodiments of the present invention are for purposes of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

Claims (1)

First spare column transfer means for being turned on by the first spare column pass signal to transfer the first spare column data to the spare sam area, and turned on by the second spare column pass signal, and A second spare column transfer means for transferring 2 spare column data to the spare sam area, and storing the first spare column data or the second spare column data and turning the spare column data by the output signal of the first logic gate; A spare sam means for outputting to the spare data bus line and the spare data bus line through the on transfer means, and a spare sam circuit portion turned on by the output signal of the first logic gate. When the stored first spare column data or second spare column data is transferred to the spare data bus line and / or spare data bus line. In the SAM redundancy circuit of the dual-port memory, characterized in that it comprises a spare SAM transfer means for inverting the first spare column pass signal by inverting the first spare column pass signal. First inverting means for outputting a low row signal, second inverting means for inverting a second spare column pass signal and outputting a low signal to one input terminal of a third logic gate of a flip-flop circuit portion, and the first A flip-flop means for outputting a high signal to one input terminal of a fourth logic gate or a fifth logic gate by inputting an output signal of the inverting means or the second inverting means, respectively, and a first serial counter A first redundant sam fuse box for cutting the fuse and outputting a first spare sam column line selection signal when the signal is applied to the gate; When the real counter signal is applied to the gate, a second redundant sam fuse box for outputting a second spare sam column line selection signal by cutting a corresponding fuse, an output signal of the first redundant sam fuse box part, and a second of the flip-flop circuit part A fourth logic gate for outputting a low signal to one input terminal of the first logic gate by inputting an output signal of the logic gate, an output signal of the second redundant sample fuse box unit, and a third logic gate of the flip-flop circuit unit A fifth logic gate for outputting a low signal to the other input terminal of the first logic gate, an output signal of the fourth logic gate, and an output signal of the fifth logic gate as the input A dual logic gate comprising a first logic gate for turning on both transistors of the leak transfer section Redundancy circuit for a memory spring.