KR100197990B1 - Redundancy circuit of a semiconductor memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundancy circuit of a semiconductor memory device for compensating defects in a spare word line or a spare column line caused by defects in a manufacturing process, A word line selection circuit means for driving a normal word line in a semiconductor memory device including a plurality of memory cell blocks composed of at least two or more spare memory cell arrays for replacing a memory cell array having the word line selection circuit, Spare word line selection circuit means for controlling the operation of the circuit means and driving the first or second spare word line, and a signal detecting the defective word line from the input address to the word line selection circuit means To replace the defective word line First and second furnace fuse box sections each including a fuse for controlling a repair operation regardless of the input address if a defect is present in one spare word line or a second spare word line; A spare column line selection circuit means for controlling the operation of the column line selection circuit means and driving the first or second spare column line; To the column line selection circuit means, and when there is a defect in the first spare column line or the second spare column line for replacing the defective column line, the fuse for controlling the repair operation regardless of the input address And a first and a second column fuse box portions It relates to a redundancy circuit of the apparatus.

Description

The redundancy circuit of the semiconductor memory device

FIG. 1 is a block diagram of a typical redundancy circuit of a semiconductor memory device; FIG.

Fig. 2 is a fuse box circuit diagram of a redundancy circuit according to the prior art; Fig.

Figure 3 is a circuit diagram of a fuse box of a redundancy circuit according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a spare word line selection circuit of a redundancy circuit according to an embodiment of the present invention; FIG.

FIG. 5 is a circuit diagram of a spare column line selection circuit of a redundancy circuit according to an embodiment of the present invention; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

11: first memory cell block 12, 22: word line selection circuit

13, 23: first rear fuse box portion 14, 24: spare word line selection circuit

15, 25: second late fuse box section 21: nth memory cell block section

31: Column line selection circuit part 32: Spare column line selection circuit part

33: first column fuse box part 34: second column fuse box part

41: first lao / column controller 42: second lao / column controller

49: nth row / column controller Vpre: precharge voltage

Vcc: Power supply voltage Vss: Ground voltage

srd: Spare word line designation decoder signal

scd: Spare column line designation decoder signal

sre: Operation time control signal of the word line selection circuit part and the spare word line selection circuit part

cs: Operation time control signal of the column line selection circuit part and the spare column line selection circuit part

nrd: Word line selection circuit section control signal

ncd: Column line select circuit control signal

sw11, sw12: Spare word line designation signal

sy1, sy2: Spare column line designation signal

MP1 and MP2: PMOS transistors MN1 to MN (n): NMOS transistors

f1 to fn, fp: Fuses I1 to I6: Inverter

N1 to N21: Nodes ND1 to ND6: NAND gate

A1, A2 to A (n-1), (An): Address signals

The present invention relates to a redundancy circuit of a semiconductor memory device, and more particularly to a redundancy circuit of a semiconductor memory device for compensating defects generated in a spare word line or a spare column line of a semiconductor memory device to another spare word line or a spare column line .

In general, a redundancy apparatus is a device for compensating for defects in a cell connected to a word line or a word line of a semiconductor memory device, or a cell connected to a column line or a column line, in which defective word lines or column lines are selected When an address is applied to the device, a normal path for selecting the word line or the column line is cut off, and the redundancy device operates to compensate for the defect by enabling the spare word line or the spare column line.

FIG. 1 is a block diagram of a general redundancy circuit, which includes memory cell blocks 11 and 21 each composed of a plurality of normal memory cell arrays and spare memory cell arrays for replacing defective memory cell arrays, Word line selection circuit portions (12, 22) for selecting and driving a normal word line of a cell block, and an address for selecting a defective word line to block selection of a defective word line and designate a spare word line (13, 23, 15, 25) for enabling the spare word line selection circuit portions (14, 24) for the first or second fuse box portion and the output signals (srd1, srd2 A spare word line selection circuit portion (14, 24) for controlling operation of the word line selection circuit portion (12, 22) and driving a spare word line when any one of the word line selection circuit portions A spare column line selecting circuit 32 for selecting a defective column line by programming an address for selecting a defective column line and designating a spare column line; The first or second column fuse box portion 33 or 34 for enabling the column fuse box portion and the column line selection circuit portion when the output signal scd1 or scd2 of the first or second column fuse box portion is enabled, And a spare column line selection circuit part 32 for controlling the operation of the spare column line 31 and driving the spare column line.

First, if a defect occurs in any word line of the first memory cell block 11, an address corresponding to the defective word line is programmed in the first low-fuse box 13. At this time, when an address for selecting a defective word line is inputted, the spare word line designating decoder signal srd1 for enabling the spare word line selecting circuit section 14 by the first fuse box section 13 is output do.

The enabled spare word line selection circuit part 14 generates an output signal nrd for controlling the operation of the word line selection circuit part 12 designating the defective word line and outputs the output signal nrd to the spare And generates a signal designating a word line.

When a defect occurs in any of the column lines of the first memory cell block unit 11, an address corresponding to the defective column line is programmed in the first column fuse box unit 33. At this time, when an address for selecting a defective column line is inputted, the spare column line designating decoder signal scd1 for enabling the spare column line selecting circuit portion 32 by the first column fuse box portion 33 is output do. The enabled spare column line selecting circuit portion 32 generates an output signal ncd for controlling the operation of the column line selecting circuit portion 31 designating the defective column line and outputs the output signal ncd to the spare column line selecting circuit 32 instead of the defective column line. And generates a signal specifying the line.

FIG. 2 is a circuit diagram of a fuse box of a redundant circuit according to the related art. FIG. 2 is a circuit diagram of a fuse box of a redundant circuit according to the related art, A first inverter I1 for inverting a signal on the first node N1 and transferring the inverted signal to the second node N2; A second inverter I2 for inverting a signal on the node N2 and transferring the inverted signal to the third node N3; a second inverter I2 connected between the power supply voltage Vcc and the first node N1, A second PMOS transistor MP2 which is turned on by a signal on the first node N1 to supply the power supply voltage Vcc to the first node N1; And the N row / column controller connected in parallel between the ground voltage Vss. Each of the row / column control units 41 to 49 includes a fuse connected between the first node N1 and the ground voltage Vss, and an NMOS type transistor connected between the fuse and the ground voltage, Transistors.

When the precharge signal Vpre transitions from high to low, the first PMOS transistor MP1 is turned on and turned on to the first node N1 And supplies the power source potential Vcc. When one of the address signals A1 to A (n) is applied to the row / column controllers 41 to 49 while the power supply potential Vcc is supplied to the first node N1, the row / column controller The first node N1 is either high or low depending on the operation of the NMOS transistors MN1 to MN (N) of the first to N-th MOS transistors 41 to 49 and the opening and closing of the fuses f1 to f (n) To determine the states of the output signals srd and scd.

For example, if the address of the defective word line is A2, the fuse f2 must be cut off to replace the defective word line with a spare word line. When the address A2 is inputted at a high level and the remaining address is inputted at a low level in a state where the fuse f2 is disconnected, the second NMOS transistor MN2 is turned on but the fuse f2 is disconnected, 1 node N1 remains in the high state. Therefore, the output signal srd operates as a redundancy circuit in which a high voltage is applied to replace the defective word line with a spare word line.

On the other hand, when the address signal for selecting another normal word line in a state where the fuse f2 is disconnected, for example, A1 is input as High and the other address signal is input as Low, the NMOS transistor MN1 And the ground voltage is applied to the first node N1 by being turned on. Therefore, the output signal srd becomes low and the redundancy operation is not performed.

Similarly, the column redundancy operation for replacing a defective column line with a spare column line is the same as the above-mentioned Roy redundancy operation.

However, when defects are generated even in a spare word line or a spare column line replaced by a conventional redundancy operation, the memory element can not be used.

Accordingly, it is an object of the present invention to provide a redundancy circuit for compensating defects in a spare word line or a spare column line, which is caused by defects in manufacturing processes of a semiconductor memory device.

According to an aspect of the present invention, there is provided a redundancy circuit including memory cell blocks each composed of a plurality of normal memory cell arrays and a spare memory cell array for replacing a defective memory cell array, A word line selection circuit means for driving a line; and an address for selecting a defective word line is programmed into a fuse to block selection of a defective word line when the defective address is input and to select a spare word line A first and a second fuse box section for enabling a word line selection circuit section and a second fuse box section for controlling the operation of the word line selection circuit section when any one of the output signals of the first and second fuse box sections is enabled, Spare word line selection circuit means for driving the normal column line, One column line selection circuit means and one or more columns for programming the address for selecting the defective column line to block the selection of the defective column line and enable the spare column line selection circuit portion for selecting the spare column line. And a spare column line selecting circuit unit for controlling the operation of the column line selecting circuit unit and driving the spare column line when any one of the output signals of the first and second column fuse box units is enabled .

The above and other objects and features of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a fuse box of a redundancy circuit according to an embodiment of the present invention. The fuse box circuit is connected between the power supply voltage Vcc and the first node N1 and is connected to the power supply voltage Vcc by the precharge signal Vpre. A first PMOS transistor MP1 connected between the first node N1 and the second node N2 for inverting a signal on the first node N1, And a second inverter connected between the second node N2 and the third node N3 for inverting the signal of the second node N2 to transfer the inverted signal to the second node N2, A second inverter I2 which is connected between the power supply voltage Vcc and the first node N1 and is turned on by a low signal on the second node N2, A second PMOS transistor MP2 for turning on the first node N1 and supplying the power supply voltage Vcc to the first node N1; Parallel connection (N1) of the first PMOS transistor (MP1) and the first node (N1) to block the selection signal of the spare word line or the spare column line in which the defect is generated The fuse fp is provided.

The roo / column control units 41 to 49 include n fuses f1 to fn connected in parallel between the first node N1 and the ground voltage Vss and fuses f1 to fn, And n NMOS transistors MN1 to MN (N), which are connected between the gate of the NMOS transistors MN1 and MNn and whose gate receives the address signals A1 to An, respectively.

A scheme of storing the address of a word line or a column line in which the defect is generated in the redundancy circuit is to cut the fuse connected to the transistor to which the defect address is input to program the defect address. If the fuse of the redundancy circuit is not programmed or the normal operation is performed because the programmed address is not applied, the power supply voltage Vcc and the PMOS type connected between the first node N1 and the first node N1 Since the power supply voltage Vcc transferred to the node N1 through the transistor MP1 is discharged to the ground voltage Vss through the transistor turned on by the input address and the fuse connected thereto, Lt; / RTI > Therefore, the output terminal is kept in the low state, so that the redundancy operation is not performed.

On the other hand, if an address for selecting a defective cell is applied to the programmed redundancy circuit, the redundancy circuit may be configured such that the address signal corresponding to the cell to be redundant is already programmed into the fuse, so that the charge of the first node (N1) Vss), the first node N1 is maintained in the high state by the charge transferred through the PMOS transistor MP1.

Therefore, the output terminal N3 is kept in the high state to perform the redundancy operation.

However, if a spare word line or a spare column line replaced by the redundancy operation is generated, the spare word line or the spare column line should be replaced with another spare word line or a spare column line. In order to control the operation of the redundancy circuit for driving the spare word line or the spare column line in which the defect is generated, as shown in FIG. 3, between the first PMOS transistor MP1 and the first node N1 The fuse (fp) was added. Accordingly, when a defect occurs in a spare word line or a spare column line to be repaired, the redundancy operation is not performed by simply disconnecting the fuse fp implemented to control the operation of the redundancy circuit for driving the redundancy circuit.

FIG. 4 is a circuit diagram of a spare word line selection circuit of a redundancy circuit according to an embodiment of the present invention, which includes a first NAND gate ND1 connected between two input terminals srd1, sre and a sixth node N6, A third inverter I3 connected between the sixth node and the seventh node N7 and a second NAND gate ND2 connected between the two input terminals srd2 and sre and the eleventh node N11, A fourth inverter I4 connected between the eleventh node N11 and the twelfth node N12 and a fourth inverter I4 connected between the eleventh node N11 and the twelfth node N12 with the sixth node N6 and the eleventh node N11 as input terminals, And a third NAND gate ND3 connected to the node N8.

The operation according to the above configuration is performed in the state where the control signal sre for controlling the operation time of the word line selection circuit part 12 and the spare word line selection circuit part 14 is transitioned to high, The first spare word line designating decoder signal srd1 which is an output signal is input to the fourth node N4 at a high level and the second spare word line designating decoder signal srd2 is input at a ninth node N9 at a low level The sixth node N6 is driven low by the first NAND gate ND1 and the eleventh node N11 is driven high by the second NAND gate ND2.

Therefore, the signals of the sixth node N6 and the eleventh node N11 are respectively inverted by the third inverter I3 and the fourth inverter I4 to enable the first spare word line sw11 , The second spare word line sw12 is disabled.

Meanwhile, the low signal on the sixth node N6 and the high signal on the eleventh node N11 are input to the third internode ND3, and the signal for controlling the operation of the first word line selection circuit portion 12 .

If a defect occurs in the first spare word line sw11, the control signal sre for controlling the operation time of the word line selection circuit part 12 and the spare word line selection circuit part 14 is high The first spare word line decoder decoder signal srd1 is input at a low level and the second spare word line decoder decoder signal srd2 is input at a high level so that the first spare word line sw11 is not selected, The spare word line sw12 is selected.

On the other hand, the high signal on the sixth node N6 and the low signal on the eleventh node N11 are logically operated by the third NAND gate ND3 to output a high signal to the eighth node N8 The operation of the first word line selection circuit unit 12 is interrupted.

That is, when a defect occurs in an arbitrary word line, the spare word line replaces the word line, the spare word line also becomes defective, and another spare word line replaces the spare word line.

5 is a circuit diagram of a spare column line selection circuit of a redundancy circuit according to an embodiment of the present invention. The circuit includes a fourth NAND gate ND4 connected between two input terminals scd1 and cs and a fifteenth node N15, A fifth inverter I5 connected between the fifteenth node N15 and the sixteenth node N16 and a fifth inverter I5 connected between the two input terminals scd2 and cs and the twentieth node N20. And a sixth NAND gate ND6 connected to the seventeenth node N17 with the fifteenth node and the twentieth node as input terminals.

In the operation according to the above configuration, when the control signal cs for controlling the operation time of the column line selecting circuit unit 31 and the spare column line selecting circuit unit 32 is transited high, the first spare column line specifying decoder signal when the second spare column line designation decoder signal scd2 is input to the seventeenth node N13 as a high and the second spare column line designation decoder signal scd2 is input to the eighteenth node N18 as a low signal, A high signal is generated at the node N20.

The low signal on the fifteenth node N15 is inverted by the fifth inverter I5 to designate the first spare column line sy1 by transmitting a high signal to the sixteenth node N16.

The high signal of the twentieth node N20 is inverted by the sixth inverter N6 and a row signal is transmitted to the twenty-first node N21, so that the designation of the second spare column line sy2 is not made.

The low signal on the fifteenth node N15 and the high signal on the twentieth node N20 are logically operated by the sixth NAND gate N6 to output a high signal to the seventeenth node N17, The operation of the selection circuit section 31 is controlled to interrupt the designation of the column line.

If a defect occurs in the first spare column line, the control signal cs for controlling the operation time of the column line selecting circuit unit 31 and the spare column line selecting circuit unit 32 is controlled to be high, 1 spare column line select decoder signal scd1 is input low and the second spare column line select decoder signal scd2 is input high to cause the fifteenth node N15 to be high and the twentieth node N20 to be high, It becomes low.

The high signal on the fifteenth node N15 is inverted by the fifth inverter I5 and the row signal is transferred to the sixteenth node N16 so that the designation of the first spare column line is not performed.

On the other hand, the row signal of the twentieth node N20 is inverted by the sixth inverter I6 to designate the second spare column line by transmitting a high signal to the twenty-first node N21.

The high signal on the fifteenth node N15 and the low signal on the twentieth node N20 are output to the seventeenth node N17 by outputting a high signal logically calculated by the sixth NAND gate N6 to the seventeenth node N17 The operation of the one-column line selection circuit unit 31 is interrupted.

That is, when a defect occurs in an arbitrary column line, the spare column line replaces the spare column line, the spare column line also becomes defective, and another spare column line replaces the spare column line.

As described above, the redundancy circuit of the present invention has the effect of increasing the yield of a device by repairing a spare cell for replacing a defective memory cell with another spare cell without discarding the memory cell.

The preferred embodiments of the present invention are for the purpose of illustration and various modifications, alterations, substitutions and additions can be made by those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

Claims (4)

A semiconductor memory device comprising a plurality of normal memory cell arrays and a plurality of memory cell blocks constituted by at least two or more spare memory cell arrays for replacing defective memory cell arrays, Spare word line selection circuit means for controlling the operation of the word line selection circuit means and driving the first or second spare word line; Respectively, and a fuse for controlling the repair operation regardless of the input address when the first spare word line or the second spare word line for replacing the defective word line is defective First and second furnace fuse box sections, and a normal column line A spare column line selection circuit means for controlling the operation of the column line selection circuit means and for driving the first or second spare column line; Outputting the detected signals to the column line selecting circuit means respectively so that the repair operation can be controlled irrespective of the input address when there is a defect in the first spare column line or the second spare column line for replacing the defective column line And a first and a second column fuse box portions, each of which includes a fuse to be connected to the first and second fuse boxes. 2. The semiconductor memory device according to claim 1, wherein the first and second fuse box portions and the first and second column fuse box portions include first switching means for transferring a power source potential to a first node by a precharge signal, A second inverter for inverting a signal from the second node and transferring the signal to the third node; and a second inverter for inverting the signal from the second node by a signal on the second node, Second switching means for turning on the power supply voltage and transmitting the power supply voltage to the first node; n fuses each connected in parallel between the first node and the ground voltage; and a second switching means connected between the respective fuses and the ground voltage And a spare word line connected between the first switching means and the first node for generating the defect or a spare column line for which a defect is generated, In that it comprises a fuse device for controlling the generation of the signal for selecting a redundancy circuit according to claim. 2. The semiconductor memory device according to claim 1, wherein the spare word line selection circuit means comprises: a first NAND gate for logically calculating and outputting a first spare word line designation decoder signal, an operation time control signal of a word line selection circuit portion and a spare word line selection circuit portion, A third inverter for inverting an output signal of the first NAND gate to operate a first spare word line, and a third inverter for inverting an operation time control signal of a second spare word line designating decoder signal, a word line selecting circuit portion and a spare word line selecting circuit portion, A fourth inverter for inverting an output signal of the second NAND gate and operating a second spare word line, a second NAND gate for inverting an output signal of the second NAND gate to operate the second spare word line, And a third NAND gate for controlling the word line selection circuit portion by logically operating a signal. . 2. The semiconductor memory device according to claim 1, wherein the spare column line selection circuit means comprises: a fourth NAND gate for logically calculating and outputting a first spare column line designation decoder signal, an operation time control signal of a column line selection circuit portion and a spare column line selection circuit portion, A fifth inverter for inverting an output signal of the fourth NAND gate to operate a first spare column line, and a fifth inverter for inverting an operation time control signal of a second spare column line designating decoder signal, a column line selecting circuit portion, and a spare column selecting circuit portion, A sixth inverter for inverting an output signal of the fifth NAND gate to operate a second spare column line, and a fifth inverter for inverting the output signal of the fifth NAND gate and the output of the fifth NAND gate, And a sixth NAND gate for controlling the column line selection circuitry by logically operating the signal. .