KR100197573B1 - Circuit and method for preventing data erase and program about special address of non-volatile semiconductor memory device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A data erase and program protection circuit and method for a nonvolatile semiconductor memory device for preserving a specific address in erase and program operations.

2. The technical problem to be solved by the invention

A data erasing and program preventing circuit and method of a nonvolatile semiconductor memory device capable of arbitrarily adjusting the size of a blocking block for preserving data for a specific address in erase and program operations.

3. Summary of Solution to Invention

A first inverter for outputting an inverted signal, a depletion-type N-channel transistor having a gate and a drain commonly connected to an output line, a fuse portion connected to an output terminal of the depletion-type transistor, a second end of the fuse portion and an output terminal of the first inverter Incremental N-channel transistor, one end of which is connected to the output line and the first and second ends of the NAND gate and the NAND gate for receiving the output signal of the anti-block detection enable signal and the pre-decoder and outputs a combined signal A key point is to have a control unit made up of a second inverter for outputting an inverted signal.

4. Important uses of the invention

It can be suitably used for nonvolatile semiconductor memory data erasing and program protection circuits and methods.

Description

Circuit and method for data erasing and program prevention for specific address of nonvolatile semiconductor memory device

1 is a schematic block diagram of an NAND type nonvolatile semiconductor memory device according to an embodiment of the present invention.

2 is a schematic block diagram of an anti-block detection circuit and its peripheral circuits according to an embodiment of the present invention.

3 is a timing diagram according to an embodiment of the present invention.

4 is a detailed view of the preventive block detection enable circuit 202 shown in FIG.

5 is a detailed view of the prevention block detection circuit 203 shown in FIG.

6 is a schematic block diagram for performing data erase and program operations according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electrically erasable and programmable (EEPROM) nonvolatile semiconductor memory devices, and more particularly to circuits for data erasure and program protection of nonvolatile semiconductor memory devices for preserving specific addresses in data erase and program operations. And to a method thereof.

In general, in the case of a nonvolatile semiconductor memory device (hereinafter, referred to as EEPROM) that is electrically erasable and programmable, data erase and program operations are desired in which a specific address portion is not erased or programmed for data storage. User demands are emerging.

In the case of a NAND flash nonvolatile semiconductor memory device (hereinafter referred to as NAND flash EEPROM), portions of the memory cell in which data erasure and program are prevented by the preventing means are mainly composed of block units. It is called a block (lockable block).

The technique of the conventional preventive block circuit is mainly performed at the manufacturing stage, and mainly provides a storage function only for the data erase operation. Because the program operation in the case of NAND flash EEPROM is performed in units of pages, a conventional block unit preventive means cannot be used, and since the block size is determined at the manufacturing stage, the block size can be changed. Because there is not.

Accordingly, an object of the present invention to solve the above problems is to provide a data erasing and program protection circuit and a method of a nonvolatile semiconductor memory device for storing data for a specific address in the data erasing and program operation.

Another object of the present invention is to provide a data erasing and program preventing circuit and a method of a nonvolatile semiconductor memory device which can arbitrarily adjust the size of a block for preserving data for a specific address in data erasing and program operation.

It is still another object of the present invention to prevent data erasure and program protection of a nonvolatile semiconductor memory device capable of adjusting the size of a prevention block at the completion of wafers and packages in data erasing and program operation to preserve data for a specific addresser. It is to provide a circuit and method.

In order to achieve the above object, the present invention comprises a source and drain region, a channel region formed between the source region and the drain region, and a floating gate for storing binary data and a control gate to which a voltage is applied from a word line. Memory cells are gathered to form a NAND cell unit, and the NAND cell units are gathered to form a memory cell block, and the data for preserving a specific address of a nonvolatile semiconductor memory device in which the memory cell blocks are assembled to form a memory cell array. An erase and program protection circuit; A first inverter for outputting an inverted chip enable signal and a source is a depletion type en-channel transistor connected to a power supply voltage and a gate and a drain are connected to an output line, and a fuse unit having one end connected to an output terminal of the depletion type n-channel transistor. A drain is connected to the other end of the fuse part, the gate is connected to the output end of the first inverter, and the source is an increased N-channel transistor connected to the ground voltage end, one end of which is connected to the output line and the other end of the anti-block detection enable circuit. The other end receiving the output signal and the other end has a control unit consisting of a NAND gate for receiving the output signal of the pre-decoder and output the combined signal and a second inverter connected to the output terminal of the NAND gate to output the inverted signal Data for storing a specific address of a nonvolatile semiconductor device And program protection circuitry.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of an NAND type nonvolatile semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, the memory cell array 109 is divided into a plurality of row blocks from the first block to the 511 block, and includes eight columns to correspond to eight data input / output pins 1/00 to 1/07, respectively. It is divided into blocks Q0 to Q7. The driving of the memory cell array 109 is controlled by the first decoder 108, and the first decoder 108 selects a specific row block selected from the row blocks according to a block selection signal input from the first predecoder 103. Activate The control buffer 101 also responds to data command signals, address signals, data input / output signals, and the like, which are input from the outside of the memory device. That is, when the instruction latch enable signal CLEx is enabled to the high level, and the write enable signal WEx transitions to the low level and then transitions to the high level again, the command latch enable signal CLEx is operated as a means for inputting a command. The command signal is input to the data register 106 through the input / output pins 1/00 to 1/07.

The information stored in the data register 106 is used as a means for informing performance of a series of data erasing, program and read operations. In addition, the address latch enable signal ALEx is enabled at a high level, and the same as when the WEx command is inputted, and at this time, an address signal is transmitted through the first address buffer 102 and the second address through 1/00 to 1/07. The input is divided into the address buffer 113, which is used as a means for storing and distributing the input address signal. The first predecoder 103 decodes the output of the first address buffer 102 and acts as a means of activating a specific decoder of the first decoder 108, the first decoder 108 decoded output. The activated signal acts as a means for activating the row block of the cell array.

In addition, the high voltage generator circuit 104, the lead and light clock chain 105, the page buffer 110, the selection circuit 111, and the data input / output buffer 112, which are not mentioned above, will be presented in the following detailed description. .

FIG. 2 is a schematic block diagram of an anti-block detection circuit 203 and a peripheral circuit thereof according to an embodiment of the present invention, and FIG. 3 is a timing diagram according to an embodiment of the present invention.

2 and 3, the prevention block detection circuit 203 may include an LBen signal which is an output signal of the prevention block detection enable circuit 202, P which is an output signal of the first predecoder 206, and It is activated and operated by Q and R signals. In this case, the size of the prevention block may be determined by the output signals P, Q, and R signals of the first predecoder 206.

In the case of the NAND flash memory, in order to decode 511 blocks in the memory cell array 109, the P, Q, and R signals are used in combination of 24 signals of P0 to P7, Q0 to Q7, and R0 to R7. At this time, the P0 to P7 signals are LSB (Least Signigicant Bit) signals, and the R0 to R7 signals mean MSB (Most Signigicant Bits). The first predecoder 206 is decoded by A0 to A21, which are output signals of the first address buffer 205 used as a means for storing and distributing the input address signal. In addition, the first address buffer 205 is a global buffer by the ADload signal activated through the ALE buffer 207 driven by the address latch enable signal ALEx and the input / output pins 1/00 to 1/07. It is stored and distributed to A0-A21 by the GL0-GL7 signal activated via 204.

At this time, the ADload signal, which is the output signal of the ALE buffer 207, is a pulse signal that transitions from the low level to the high level, and then transitions back to the low level after a predetermined period has elapsed. The prevention block detection enable circuit 202 transitions the GNDx pin, which is an external input signal, from low level to high level to activate the GND signal to a high level through the GND buffer 201, and outputs the ALE buffer 207. When the ADload signal is activated by a pulse, the antiblock detection enable circuit 202 operates and activates the LBen signal by a pulse.

4 is a detailed view of the preventive block detection enable circuit 202 shown in FIG. Referring to FIG. 4, the NAND gate 402 which receives the above-described output signal GND of the GND buffer 201 and the ADload signal inverted by the inverter 401, the output of the NAND gate 402, and NAND gate 404 for outputting the delayed output of the NAND gate 402 through a delay circuit as a first input and a second input, respectively, and an inverter 405 connected to the output terminal of the NAND gate 404. The LBen signal is output to the input terminal of the prevention block detection circuit 203. At this time, the LBen signal is input to the prevention block detection circuit 203 in the form of a pulse in which the pulse of the ADload signal is inactivated, and is maintained at a high level for a time delayed by the delay circuit 403 and then inactivated to a low level. It works.

5 is a detailed view of the prevention block detection circuit 203 shown in FIG. Referring to FIG. 5, an inverter 501 for outputting an inverted chip enable signal CE, and a depletion-type N-channel transistor 502 having a source connected to a power supply voltage and a gate and a drain connected to a line 505 together. And an increased N-channel connected to an output line 505 at one end thereof, a drain connected to the other end of the fuse 503, a gate connected to an output end of the inverter 501, and a source connected to the ground voltage terminal. A transistor 504, one end of which is connected to line 505, the other end of which receives LBen, the output signal of the antiblock detection enable circuit 202 shown in FIGS. The NAND gate 506 for receiving the output signals P, Q, and R which are the output signals of the first predecoder 206 shown in FIG. The inverter 507 outputs a signal.

The polyfuse 503 is required for the normal operation of the protection block detection circuit 203. When there is a block to prevent data erase and program operation of a memory cell, the polyfuse 503 is required. Can be prevented by cutting.

The polyfuse 503 is a fuse cut by a laser beam, and is preferably cut in a wafer state before package assembly, that is, in a state in which the fuse region is exposed. In addition, the line 505 is determined to be activated or deactivated according to whether the polyfuse 503 is cut while the chip enable signal CE is activated at a low level. In other words, if the polyfuse 503 is cut off, the line 505 is activated to a high level by the depletion transistor 502. If the polyfuse 503 is not cut off, the depletion transistor 502 The drive capability of the low incremental transistor 504 is greater than the drive capability of the drive transistor.

Accordingly, the NAND gate 506 activates the LBen signal in the form of a pulse and activates the LBi signal in the form of a pulse in a block in which the P, Q, and R signals are selected.

6 is a schematic block diagram for performing data erase and program operations according to an embodiment of the present invention. Referring to FIG. 6, the first, second, third, ... protection block detection circuits 601, 602, 603, ... are blocked by the output signals P, Q, R of the first predecoder 206. Activates any one of the first, second, third ... prevention block detection circuits (601, 602, 603 ...) of different sizes. According to an embodiment of the present invention, the P, Q, and R signals are determined from the block 511 of the plurality of row blocks (first to 511 blocks) of the memory cell array 109. For example, data erasing and program protection for 32K bytes may include the P, Q, and R signals for the eight blocks (blocks 504 to 511) to which the Q7 signal and the R7 signal are input at a high level. Means erasure and program protection. When one of the prevention block detection circuits 601, 602, 603... Is activated at a high level, the NOA gate 604 is activated to bring the LOCK signal, which is an output signal of the NOA gate 604, to a low level. Transition to level. The LOCK signal is input as a signal for deactivating the data register 605 which is used as a means for informing performance of a series of data erasing, program and read operations, thereby deactivating the output signal of the data register 605 to a low level. It is possible to prevent data erase and program operations from being performed on the block selected by the P, Q, and R signals.

As described above, according to the present invention, it is possible to preserve data already stored at a specific address by interrupting data erase and program operations of the memory cell. That is, when the polyfuse is cut in order to adjust the size of the prevention block, the prevention block in which the polyfuse is cut is deactivated, so that the data stored at the specific address is preserved as it is. In addition, adjusting the size of the prevention block by activating or deactivating the protection block according to whether the polyfuse is cut may be arbitrarily adjusted by cutting the polyfuse at the completion stage of the wafer and the package.

Claims (3)

The memory cells include a source and drain region, a channel region formed between the source region and the drain region, a floating gate for storing binary data, and a control gate to which a voltage is applied from a word line. A data erasing and program protection circuit for preserving a specific address of a nonvolatile semiconductor memory device in which these NAND cell units are gathered to form a memory cell block and the memory cell blocks are formed to constitute a memory cell array; A first inverter for outputting an inverted chip enable signal and a source is a depletion type en-channel transistor connected to a power supply voltage and a gate and a drain are connected to an output line, and a fuse unit having one end connected to an output terminal of the depletion type n-channel transistor. A drain is connected to the other end of the fuse part, the gate is connected to the output end of the first inverter, and the source is an increased N-channel transistor connected to the ground voltage end, one end of which is connected to the output line and the other end of the anti-block detection enable circuit. The other end receiving the output signal and the other end has a control unit consisting of a NAND gate for receiving the output signal of the pre-decoder and output the combined signal and a second inverter connected to the output terminal of the NAND gate to output the inverted signal For storing a specific address of a nonvolatile semiconductor memory device Data erase and program protection circuit. The nonvolatile device of claim 1, wherein the fuse unit cuts the fuse of the fuse unit by a laser beam in a wafer state before assembling a package in a memory cell block to prevent data erase and program operations. A data erase and program protection circuit for assisting a specific address of the semiconductor memory device. Memory cells comprising a source and drain region, a channel region formed between the source region and a drain region, a floating gate for storing binary data, and a control gate insulated from the floating gate, and form a NAND cell unit, A method for erasing data and preventing a program for preserving a specific address stored in an unselected memory block in a nonvolatile semiconductor memory device in which the NAND cell units are gathered to form a memory cell block, and the memory cell blocks are assembled to form a memory cell array. To; A first inverter for outputting an inverted chip enable signal and a source is a depletion type en-channel transistor connected to a power supply voltage and a gate and a drain are connected to an output line, and a fuse unit having one end connected to an output terminal of the depletion type n-channel transistor. A drain is connected to the other end of the fuse part, the gate is connected to the output end of the first inverter, and the source is an incremental N-channel transistor connected to the ground voltage end, one end of which is connected to the output line and the other end of the antiblock detection enable circuit. The fuse of the control unit includes an NAND gate configured to receive an output signal and receive an output signal of the predecoder and output a combined signal, and a second inverter connected to an output terminal of the NAND gate to output an inverted signal. By truncating, preserve specific addresses stored in unselected memory blocks A method of data erase and program protection for storing specific address of the non-volatile semiconductor memory device.