KR970051329A - Erasing and Program-Protecting Circuits and Methods for Specific Addresses of Nonvolatile Semiconductor Memory Devices - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

An erase and program protection circuit and method for a nonvolatile semiconductor memory device for protecting a specific address in erase and program operations.

2. The technical problem to be solved by the invention

An erase and program prevention circuit and method for a nonvolatile semiconductor memory device in which an erase block can be arbitrarily adjusted in size to protect data for a specific address in erase and program operations.

3. Summary of Solution to Invention

Has a plurality of word lines formed on a semiconductor substrate, and has a plurality of NAND cell units composed of a plurality of memory transistors connected in series, wherein the plurality of NAND cell units form a memory cell block, and the plurality of memory cell blocks Each of the memory transistors includes a source and drain junction formed in the semiconductor substrate, a channel region between the source region and the drain region, a floating gate configured to store binary data formed on the channel region, and An erase and program protection circuit for protecting a specific address of a nonvolatile semiconductor memory device formed over a floating gate and connected to a corresponding word line of the word lines, wherein the selected NAND is selected during data erase and program operations. Memory Transitions in Cell Units In order to prevent changing the binary data previously stored to a base that has a control means that enables arbitrarily adjusting the memory cell array region.

4. Important uses of the invention

It can be suitably used for the erase and program protection circuit and method of the nonvolatile semiconductor conductor device.

Description

Erasing and Program-Protection Circuits for Specific Addresses in Nonvolatile Semiconductor Memory Devices

Since this is an open matter, no full text was included.

1 is a schematic block diagram of a NAND type nonvolatile semiconductor memory device according to an embodiment of the present invention;

2 is a schematic block diagram of a protection block detection circuit and a peripheral circuit thereof according to an embodiment of the present invention;

5 is a detailed view of an anti-block detection circuit 203 according to an embodiment of the present invention.

Claims (4)

Has a plurality of word lines formed on a semiconductor substrate, and has a plurality of NAND cell units composed of a plurality of memory transistors connected in series, wherein the plurality of NAND cell units form a memory cell block, and the plurality of memory cell blocks Each of the memory transistors includes a source and drain junction formed in the semiconductor substrate, a channel region between the source region and the drain region, a floating gate configured to store binary data formed on the channel region, and CLAIMS 1. An erase and program protection circuit for protecting a particular address of a nonvolatile semiconductor memory device, the control gate formed over a floating gate and connected to a corresponding word line of said word lines; And control means for arbitrarily adjusting the memory cell array region so that the binary data previously stored in the memory transistors in the selected NAND cell unit during data erase and program operations are not changed. Clear and program protection circuitry to protect specific addresses. The method of claim 1; The control means includes a first inverter for outputting an inverted chip enable signal, a source depletion type N-channel transistor connected to a power supply voltage, a gate and a drain connected to an output line, and one end of the fuse connected to the output line. An n-channel transistor having a drain and a drain connected to the other end of the fuse part, a gate connected to an output end of the first inverter, a source connected to a ground voltage end, and an end connected to the output line and the other end of the anti-block detection. A second gate for receiving an output signal of the enable circuit and another end for receiving an output signal of the first predecoder and outputting a combined signal; and a second terminal for outputting an inverted signal connected to the output terminal of the nAND gate; In order to protect a specific address of the nonvolatile semiconductor memory device, characterized in that consisting of an inverter Clear and program protection circuit. The method of claim 2; Non-volatile semiconductor memory, characterized in that for the block to prevent the erase and program operation of the memory cell is to be performed, the fuse of the fuse unit must be cut by a laser beam in the wafer state before the package assembly. Clear and program protection circuitry to protect the device's specific address. And a plurality of word lines formed on one surface of the semiconductor substrate, and an array of a plurality of cell units formed on the one surface, each cell unit having at least one memory transistor, wherein the memory transistor comprises a source formed on the semiconductor substrate. A channel region between the region and drain region and the two regions, and a floating gate insulated over the channel region and a control gate insulated over the floating gate, the control gate of each memory transistor corresponding to one of the word lines. Connected to a word line, the array is divided into a plurality of memory blocks, and each memory block is erased and programmed to protect a specific address stored in an unselected memory block in a nonvolatile semiconductor memory device composed of a plurality of cell units. How to prevent In; And control means for arbitrarily adjusting the memory cell array region so that the binary data previously stored in the memory transistors in the selected NAND cell unit during data erase and program operations are not changed. Erasing and program protection methods to protect specific addresses. ※ Note: The disclosure is based on the initial application.