KR100196326B1 - Frequency compensating circuit - Google Patents

Abstract

The present invention relates to a frequency correction circuit in an audio system that requires high linearity. In particular, an integrator, a weight level A / D converter, and a digital control circuit constitute a correction circuit, and a capacitor in an active RC filter has a positive variation and a negative value. By configuring capacitor strings to allow different capacitors to react to fluctuations to keep the RC time constant and frequency response set in the filter constant, large errors between correction code values and actual integral output values can be reduced, and also low voltage dependence. Passive elements with a filter determine the time constant of the filter, and the correction code is fixed while the signal is being processed, and because the correction code is fixed during normal operation, it does not cause the modulation of the signal processed in the integrated circuit. It can be integrated with the active pulter, the main circuit, and has an RC time constant of ± 50%. The RC time constant and cutoff frequency of the integrated system have an error range within ± 10%.

Description

Frequency correction circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency correction circuit in an audio system requiring high linearity. In particular, the present invention relates to a frequency correction circuit for generating an actual correction code for each time constant variation using a voltage level distribution due to actual RC time constant variation as a reference voltage. (Tunning) circuit.

Recently, in audio frequency applications requiring high linearity, the design of analog / digital (A / D) or digital / analog (D / A) converters using oversampling techniques has been actively performed.

In such a converter, an anti-aliasing filter is required for an A / D converter and a data reconstruction filter is required for a D / A converter.

At this time, the analog filter such as the anti-aliasing filter or the data reconstruction filter should not act as a deterioration factor of the related digital signal processing processor, so that linearity of 90 dB or more should be ensured.

FIG. 1 shows the structure of a biquadtic (BIQD) bi-low Low Pass Filter (LPF), which is one of the active RC filters.

Referring to FIG. 1, three op amps and R and C are basically included, and each parameter value may be independently set. In other words, when C1 = C2 = C3, the term of C is included only in the -3dB frequency equation, and the term of R1 is included only in the equation that determines the quality factor (Q), so it does not affect other parameters. You can adjust the parameters.

here,

Becomes

However, in the case of integrating such an analog filter, the absolute value variation of the passive elements, ie, R and C, integrated due to various environmental factors such as process dependency, temperature change, and aging occurs, resulting in a change in frequency response. That is, the passive element value changed by various factors from the set passive element value may distort the specification of the entire circuit, and if it is not compensated for, the frequency response change may be up to ± 50%.

Thus, recently reported analog filters have corrected for frequency response variations using a triode-mode MOS transistor and a transconductor that can be tuned.

However, these techniques produce harmonic noise, with a linearity limit of less than 65dB.

Thus, most of the continuous-time analog filters associated with audio processors that require high linearity are designed off-chip.

In addition, most anti-aliasing filters and data reconstruction filters perform precise filtering inside the digital processor, requiring only a frequency response accuracy of 5 to 10%.

Under these circumstances, Durham et al. (A. Durham, W. Rendom-White, High-linearity continuous-time filter in 5-V VLSI CMOS, IEEE J. Solid-State Circuits, vol. 27, pp. 1270-1276, Sept. 1992.) We have reported a paper on the design of on-chip compensation filter applicable to audio frequency applications where linearity is required.

This paper generates a calibration code using a dual-slope calibration circuit as shown in FIGS. 2 and 3.

That is, after the initial reset period, the analog portion 21 of the circuit is a fixed time, a continuous time integrator (Φ _A = low, Φ _B = high, Φ _C = low) with Vref as input during 2 ^N T _CK . Acts as.

As shown in FIG. 3, the output result is a negative voltage lamp starting from V _{AG which} is an analog ground, and after this time, the output voltage of the integrator is V _{o (peak)} .

It then operates as a switched-capacitor integrator (Φ _A = pulse, Φ _B = low, Φ _C = low) which creates a step voltage (δVo) toward the positive side.

The nominal values of R1, C1 and C0 are chosen so that a particular step is exactly matched to V _AG , and the total number of voltage steps up to V _AG is (ns + P).

Where P is the offset used to make n zero when the largest time constant (R1C) max occurs.

The initially preset counter 24 increments with the number of steps in the step waveform until the integrator output passes through V _AG . The counter 24 stops counting when the output of the comparator 22 becomes positive under the control of the logic unit 23.

That is, the number of steps of the stepped waveform from Δt time until passing through the analog ground (V _AG ) is counted and then set as a correction code as it is and transmitted to the latch 25 for outputting the correction code.

Actual correction is performed by replacing capacitors C1 and C2 for determining time constants in the filter circuit as shown in FIG. 1 with a programmable capacitor row as shown in FIG. 4 and then switching according to a correction code.

However, the above-described double tilt correction method has the following error.

First, the integral output V _{o (peak)} values V _{o (peak)} ^{RC max} , V _{o (peak)} ^RCnom , V _{o (peak} , assuming RC time constant fluctuations of ± 50%. ₎ ^RCmin is determined by Equation 1 as Equation 3 below.

[Equation 3]

Here, RCmax is the value of time constant when the rate of change is + 50%, RCnom is the normal value, and RCmin is the time constant value when the rate of change is -50%.

Meanwhile, FIG. 5 As an example of an analog integral waveform from ± 50% to + 50% in increments of -50% to + 6.25% with a ± 50% RC time constant rate of change, the magnitude of the change due to the change in the RC time constant on the positive side is determined by the overall integral level distribution. It accounts for only 25%, with the remaining 75% represented by the change in the RC time constant on the negative side.

However, in the double slope correction circuit as shown in FIG. 2, such a level distribution is ignored so that the total integrated level width due to the variation from -50% to + 50% is simply divided by the number of correction codes.

In other words, even though the correction codes must have different level intervals, the corrected RC time constant error range can not satisfy the error range within ± 10% reported in the paper.

Second, there is an error in the process of calculating the element value in each capacitor column for correction. That is, when the device value calculated in this paper has ± 50% RC time constant variation rate and Cnom = 40pF, Cmin is 20.625pF and δC is 1.25pF for 5-bit correction code, so that the switchable capacitors are 1.25, 2.5, It is set to a value of 5, 10, 20.

Therefore, the range of capacitor values that can be implemented ranges from 20.625 to 59.375 pF.

However, in order to maintain a constant RC time constant, that is, the integrator resistance value can be changed from 1.375 to 4.125mΩ due to a change in resistance value of ± 50%, so that the capacitor column must be selectable from 26.67 to 80pF by switching.

Therefore, the RC time constant corrected for the negative time constant fluctuation has a very large error.

Third, because the integration level change is distributed in different widths in the positive and negative variations, different Cmin values and capacitors are required according to this variation direction but are ignored.

The present invention is to solve the above problems, an object of the present invention is to generate the actual correction code for each time constant variation using the voltage level distribution by the actual RC time constant variation as a reference voltage, (+) The present invention provides a frequency correction circuit that maintains a constant RC time constant error range by allowing different capacitors to react to variations and negative variations.

A characteristic of the frequency correction circuit according to the present invention for achieving the above object is an integrator for obtaining a change in time constant, and a sample / hold for maintaining the integral output level due to the time constant change obtained in the integrator while the correction code is generated. A code value calculator for generating a correction code by comparing the integral level output from the sample / hold unit with each of the approximated reference voltage levels, and a time constant set by the correction code output from the code value calculator. It is configured to include a filter to keep a constant.

1 is a block diagram of a general active RC filter

2 is a block diagram of a conventional frequency correction circuit

3 is a timing diagram of each part of FIG. 2;

4 is a circuit diagram showing a capacitor string in a filter that is switched by the correction code generated in FIG. 2 to correct the RC time constant;

5 shows an example of an analog integral waveform from + 50% to + 50% in increments of -50% to + 6.25% with a ± 50% RC time constant rate of change;

6 is a block diagram illustrating a configuration of a frequency correction circuit according to the present invention.

7 is a block diagram illustrating an embodiment of the weight level analog-to-digital converter of FIG.

8 is a block diagram illustrating another embodiment of the weight level analog-to-digital converter of FIG.

FIG. 9 is a diagram showing an example of an integration level output from the integrator of FIG. 6 with respect to a RC time constant variation from -50% to + 6.25% in increments of up to + 50%.

10 is a table illustrating an example of an integration level and a correction code according to the present invention.

FIG. 11 is a circuit diagram showing a capacitor string in a filter switched by the correction code generated in FIG. 6 to correct an RC time constant.

12 is a graph showing the RC time constant correction result and the state before the correction according to the present invention

Figure 13 is a graph showing the cut-off frequency correction result and the state before the correction according to the present invention

14A and 14B show variation distributions of a frequency response waveform and a cutoff frequency when no correction is made;

15A and 15B show variation distributions of a frequency response waveform and a cutoff frequency when the correction code generated in FIG. 6 is applied to the capacitor string of FIG. 4.

16A and 16B illustrate variation distributions of a frequency response waveform and a cutoff frequency when the correction code generated in FIG. 6 is applied to the capacitor string of FIG. 11.

* Explanation of symbols for main parts of the drawings

61: integrator 62: sample hold unit

63: weight level A / D converter 63-1,81: comparator

63-2: OR gate 63-3: AND gate

64: logic section 65: latch

Q1-Q3: shift register

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 is a simple block diagram of a frequency correction circuit according to the present invention, integrating 61 for obtaining a change in RC time constant, and maintaining an integral output level due to the changed RC time constant obtained in the integrator 61 while a correction code is generated. A sample / hold unit 62 to adjust the weight level A / D converter 63 to calculate a code according to the integration level value, a logic unit 64 to provide a timing signal to the A / D converter 63; And a latch 65 for storing the output of the A / D converter 63 for a predetermined time.

7 and 8 illustrate embodiments of the weight level A / D converter, FIG. 7 is an A / D converter using a weighted resistance string, and FIG. 8 is an A / D converter using a weighted capacitor string.

In this case, since the integral voltage levels have different intervals, the resistance strings of FIG. 7 are connected in series with different weights so that all the corresponding integration levels are implemented, and the capacitor columns of FIG. 8 are connected in parallel with different weights. do.

FIG. 11 is a detailed circuit diagram of a capacitor column in an RC active filter for correcting an RC time constant value by a correction code outputted from the correction circuit of FIG. 6, and includes a plurality of logic gates O1 to O6 and A1 to logic combination of correction codes. A6), a plurality of CMOS switches X1L to X4L and X1H to X4H that are turned on / off in accordance with the most significant bit MSB of the correction code and the respective outputs of the logic gates O1 to O6 and A1 to A6, and A plurality of capacitors C1L to C4L and C1H to C4H in parallel configuration respectively connected to the plurality of CMOS switches X1L to X4L and X1H to X4H.

Here, the use of a capacitor rather than a resistor in the RC time constant correction is because the capacitor has a relatively small variation in environmental factors.

In the present invention configured as described above, the operational amplifier 61-1 of the integrator 61 uses the same one as the operational amplifier in the active RC filter to accurately correct the change in the RC time constant used in the active RC filter.

9 shows the integral level output from the integrator 61 when 2.65 V is applied to the input (V _INT ) of the integrator 61 in response to a final + 50% RC time constant change from -50% to 6.25%. As an example, it is shown that the integrated voltage levels have different intervals, which are represented by numbers as shown in FIG. 10.

Here, the integration level for each time constant is shown when the integration value by RCmin time constant reaches 0V after starting integration from 5us with C0 = 1 pF and R0 = 2.75 MΩ.

In this case, it can be seen that the change caused by the change of the RC time constant on the (+) side accounts for only 25% of the total integration level distribution, and the remaining 75% is represented by the change of the RC time constant on the (-) side.

At this time, the mode clock mclk is applied to the sample / hold unit 62 to maintain the voltage level after a certain integration period (for example, about 4.513us) after starting integration in the integrator 61.

Therefore, the sample / hold unit 62 samples the integration level due to the RC time constant variation output from the integrator 61 and maintains it while the correction code is generated.

As the integral level output from the sample / hold part 62 is difficult to compare because% comes out to two decimal places as shown in FIG. 10 and the number of resistors or capacitors of the A / D converter increases, the number of hardware, that is, the number of resistors or capacitors, is increased. Integrate the level of integration in the A / D converter to reduce

To this end, the output of the sample / hold unit 62 is input to the weight level A / D converter 63.

That is, in order to generate each reference level to be compared in the comparator 63-1 of the A / D converter 63 to generate the 4-bit correction code, the weighted resistance string of the series configuration as shown in FIG. 7 may be used. It is also possible to use weighted capacitor sequences of the same parallel connection.

In this case, the operation of the A / D converter 63 using the weighted resistance string as shown in FIG. 7 is as follows.

The voltage level V _LV held by the sample / hold unit 62 has a voltage level for each RC time constant and is input to the comparator 63-1 of the A / D converter 63.

For example, it has a voltage level of 1.1V at RCmax, 0.829V at RCnom, and 0V at RCmin.

At this time, the system clock clk is applied to a 5-bit ring counter (not shown) of the logic unit 64 to obtain timings t1 to t5.

The timing signals t1 to t5 are applied to the AND gate 63-3 through the OR gate 63-2 of the A / D converter 63, and the timings are input to the AND gate 63-3. One correction period is achieved by the clock clk.

The determination registers Q1 to Q3 of the A / D converter 63 operate as shift registers.

The voltage level V _LV held at t1 is first compared with 75% Vref at comparator 63-1. That is, the voltage at the position where the switch is turned on by t1 is 75% Vref because it is 10R upward and 30R downward.

At t2, the result at t1 is stored in the shift register Q1, and the MSB bit of the correction code is determined and stored in the latch 65 according to the content of Q1. If Q1 is low, the comparator 63-1 is held. Compare the voltage V _LV with 50% Vref and compare with 90% Vref if Q1 is high.

At t3, the result at t2 is stored in the shift register Q1, and the next bit of the correction code is determined and stored in the latch 65 according to the contents of the shift register Q1, and the determination at t1 is the shift register Q2. Shift to.

Further, the reference voltage level to be compared next is determined according to the contents of Q1 and Q2.

In this way, the LSB bit of the correction code is determined at t5 so that all correction codes are made.

On the other hand, the operation of the A / D converter 63 using the weighted capacitor sequence as shown in FIG.

Here, the 7-bit ring counter (not shown) of the logic unit 64 generates t1 to t7 timing in response to the system clock clk, outputs it to the A / D converter 63, and the sample / hold unit 62. Assume that a calibration cycle occurs when is in hold mode.

First, at t1, the top switch S1 is turned on so that the upper plate of each capacitor is connected to ground and the lower plate is connected to the held voltage level V _LV .

At t2 this switch S1 is turned off and the lower plates of all capacitors C1 to C7 are connected to ground so that the top plate voltage has the opposite polarity value -V _LV of the held voltage level V _LV .

Subsequent conversion takes place by switching some of the lower plates of C1 to C7 to Vref according to the binary search algorithm and eventually returning the upper plate to ground again.

For example, to determine the MSB of the correction code at t3, the bottoms of C7, C6, C4, C3 are switched from ground to Vref, so the top plate voltage increases by 75% Vref.

The comparator 81 then determines the polarity of the difference between the top plate voltage 75% Vref and ground to determine the MSB of the correction code.

This next step is the same as the operation of the A / D converter using the weighted resistance train described above.

The correction code obtained in FIG. 7 or FIG. 8 turns the capacitor string of the active RC filter of FIG. 11 on / off.

That is, when the correction code is 1111, the CMOS switch (X1L) is turned on and the CMOS switches (X2L-X4L) are turned on by the logic gates (O1-O6, A1-A6) so that the capacitor C1L + C2L + C3L + C4L values are RC time constants. Is the C value of.

For example, if C1L = 40pF, C2L = 20pF, C3L = 10pF, and C4L = 5pF, the C value of the active RC filter is 75pF.

When the correction code is 0000, only the CMOS switch X1H is turned on, and both the CMOS switches X2H-X4H and X1L-X4L are turned off by the logic gates O1-O6 and A1-A6, so that the capacitor C1H value is the RC time constant. Will be the C value.

For example, if C1H = 26.67pF, the C value would be 26.67pF.

If the correction code is 0001, the CMOS switch X1H is turned on, and the CMOS switches X4H are turned on by the logic gates O1-O6 and A1-A6, and the capacitor C1H + C4H value becomes the C value of the RC time constant.

For example, if C1H = 26.67pF and C4H = 1.67pF, the C value is 28.34pF.

In this way, switching of four capacitors out of a total of eight capacitors is required according to the MSB of the correction code.

Each device value is selected by the following Equation 4 to maintain the RC time constant error within ± 10%.

[Equation 4]

Therefore, assuming a steady state capacitor value of 40 pF, the capacitors responding to the (+) fluctuation are C1H (Cmin (+)) = 26.67pF, C2H = 6.67pF, C3H = 3.33pF, C4H = 1.67pF, respectively. The capacitors responding to the (-) fluctuation have values of C1L (Cmin (-)) = 40pF, C2L = 20pF, C3L = 10pF and C4L = 5pF, respectively.

The RC time constant and cutoff frequency of the integrated system with RC time constant fluctuation rate of ± 50% due to the correction circuit and the modified capacitor train designed as described above are within ± 10% of the error compared to before the correction using the 4-bit compensation code. To have

That is, as shown in FIG. 12, the RC time constant was measured in the -9.71 to + 9.71% error range, and the cutoff frequency was measured in the -9.53 to + 9.52% error range.

14 to 16 show cutoff frequency changes for a representative value of a correction code from 0000 to 1111.

14A, 15A, and 16A are frequency response waveforms, and FIGS. 14B, 15B, and 16B are variation distributions of the -3 dB cutoff frequency.

14A and 14B are waveform diagrams before correction by the correction code, and FIGS. 15A and 15B are waveform diagrams when the correction code generated by the present invention is applied to a capacitor column adopted by the double slope correction technique. 16A and 16B are waveform diagrams when the correction code generated by the present invention is applied to the capacitor string of the present invention.

14 to 16, it can be seen that the cutoff frequency error range according to the present invention is the smallest.

By extending the correction circuit of the present invention to a correction circuit of 5 bits or more, a more accurate error range can be obtained.

At this time, the correction circuit of 5 bits or more can be easily extended.

That is, as the number of correction code bits is increased, a cutoff frequency error range of a smaller range can be obtained.

On the other hand, the capacitor circuit in the correction circuit and the active RC filter according to the present invention can be applied to all circuits in which the RC time constant is used, and in particular, it can be applied to the field of digital audio.

For example, it can be applied when performing data reconstruction by processing Pulse Density Modulation (PDM) or Pulse Width Modulation (PWM) signals, which are outputs of ΣΔ D / A modulators, on a single chip of a compact disc player (CDP).

As described above, according to the frequency correction circuit according to the present invention, the correction circuit is composed of an integrator, a weight level A / D converter, and a digital control circuit, and the capacitor in the active RC filter is used for positive and negative variations. Capacitor rows can be configured to react with different capacitors to keep the RC time constant and frequency response set in the filter constant.

In addition, the passive elements with low voltage dependence determine the time constant of the filter, and the correction code is fixed while the signal is being processed, and the correction code is fixed during normal operation. It can be integrated with active pulsers, the main circuit, on the chip.

In addition, the RC time constant and the cutoff frequency of the integrated system having the RC time constant variation rate of ± 50% by the correction circuit of the present invention has an error within ± 10%.

Claims (6)

An integrator for obtaining a change in time constant, a sample / hold unit for maintaining the integral output level due to the time constant change obtained in the integrator during the generation of a correction code, and each reference approximating an integration level output from the sample / hold unit And a filter for generating a correction code in comparison with the voltage level, and a filter for maintaining a constant time constant set by the correction code output from the code value calculator. The weight level analog / digital digital signal of claim 1, wherein the code value calculator continuously approximates integral voltage levels having different intervals and compares the integrated voltage levels with the timing signals to generate a correction code. A converter configured to generate a plurality of timing signals having a correction period in response to a system clock, and to provide the plurality of timing signals to the analog / digital converter, and a latch to temporarily store the correction code generated by the analog / digital converter. Frequency correction circuit. 3. The method of claim 2, wherein the analog-to-digital converter comprises: a resistor column for successively approximating integrated voltage levels having different intervals by connecting a plurality of resistors having different weights in series; A comparator for comparing with the integral level output from the sample / hold unit, a plurality of shift registers for storing and shifting the output of the comparator and sequentially outputting a correction code, and an output and timing signal of the shift register. And a switching element for switching the corresponding resistance of the resistor column to determine the reference voltage level to be compared next. The analog / digital converter of claim 2, wherein the analog / digital converter includes a capacitor string configured to sequentially approximate integral voltage levels having different spacings by connecting a plurality of capacitors having different weights in parallel, and an integration level output from the sample / hold part. A reference voltage level of the compensation code is determined according to on / off of the corresponding capacitor in the capacitor column, and a comparator comparing the determined reference voltage level with a ground voltage, and storing and shifting the output of the comparator A plurality of shift registers for sequentially outputting a correction code, and a switching element for switching the corresponding capacitors in the capacitor column by using the output of the shift register and a timing signal to determine a reference voltage level to be compared next. Correction circuit. 5. The method of claim 4, wherein the capacitor row connects the upper side of all capacitors to which the switching element is connected to ground through the switching element turned on at the timing t1, and the lower side of the capacitor to the integral level held at the sample / hold part. Turn off the switching element at t2 and connect the lower side of all capacitors to ground so that the upper side of the capacitor has the opposite polarity value of the held integral level, and after timing t3, among the plurality of capacitors according to the corresponding bits of the correction code. And a reference voltage level is set on the upper side of the capacitor by switching the lower side of the capacitor to the reference voltage. The frequency compensating circuit of claim 1, wherein the filter comprises a plurality of programmable capacitors to switch different capacitors according to RC time constant fluctuation directions.

Images