KR20010088175A - Correction code generrator - Google Patents

Abstract

PURPOSE: A correction code generator is provided, which is able to create exact correction codes based on an actual integral level distribution and externally adjust time constant. CONSTITUTION: A correction code generator includes an integrator(1), a comparator(2), a signal generator(3), a (N+RB) - bit counter(6), a (N+RB) - decoder(7), and a latch(5). The integrator continuously integrates a reference voltage for a predetermined period of time after initial reset and integrates the reference voltage in a step waveform according to the switching operation of a switch after the lapse of the predetermined period of time. The comparator compares the output signal of the integrator with an analog ground voltage to output a comparison signal according to the compared result. The signal generator receives the output signal of the comparator and synchronizes the output signal to generate a count enable signal and a timing signal. The bit counter counts the count enable signal during the active section of the clock signal to output a counting signal. The decoder receives and decodes the counting signal. The latch accepts and latches the decoded signal to generate a correction code.

Description

Calibration code generator {CORRECTION CODE GENERRATOR}

The present invention relates to a correction code generator, and more particularly, to a correction code generator capable of automatically correcting an absolute value change caused by various environmental factors of a passive element integrated therein.

In general, the absolute value change of the passive element used in the active RC filter as shown in FIG. 1 or the passive RC filter as shown in FIG. 2 causes distortion of the gain or cutoff frequency, and also due to various environmental factors when integrating the circuit. Distortion of gain or cutoff frequency is required and a technique for correcting this is required. A conventional correction code generator for such a correction will be described.

3 is a circuit diagram showing a configuration of a conventional correction code generator. As shown in FIG. Tck) during the reference voltage ( ) Are continuously integrated and the predetermined time ( Tck) after the switch ( An integrator (1) integrating with a stepped waveform according to the switching; Output signal of the integrator 1 ) And analog ground voltage ( A comparator (2) for comparing) and outputting a comparison signal accordingly; A signal generator (3) receiving the output signal of the comparator (2) and synchronizing it with a clock signal (Tck) to generate a counting enable signal (EN) and a timing signal (TIMING SIGNALS) accordingly; An N-bit counter (4) for counting the counting enable signal (EN) of the signal generator (3) during the active period of the clock signal (Tck); It consists of a latch 5 which latches the counting signal of the N-bit counter 4 and generates a correction code. The operation of such a conventional apparatus will be described with reference to the waveform diagram of FIG.

First, integrator 1 has a clock time after initial reset ( Reference voltage (Tck) ) Is continuously integrated to output a negative voltage ramp as shown in FIG. After Tck), the peak voltage ( )

= ----------- Equation (1)

After that, the step voltage (+) It operates as a switched-capacitor integrator, which is implemented as follows.

= ---------------- Equation (2)

Analog ground voltage after PTck time (where P is offset to set N to '0' when time constant is maximum) The number of steps of the stepped wave until passing through) is counted by the N-counter 4, and it is set as a correction code as it is and transmitted to the latch 5.

Here, the actual correction is a capacitor that determines the time constant in the filter circuit as shown in FIG. ) And then switch the switches (S1 ~ SN) according to the calibration code.

In the above correction method, the corresponding integrated output peak voltage (when the RC time constant maximum / minimum value changes by ± Q [%] relative to the design value) ) Is defined as shown in Figure 5. = K / RC, K = Q1 is a value between 0 and Q)

Here, in the above correction technique, a correct code is generated when the following equation is satisfied.

------------- Formula (3)

That is, the position (POS) without change in RC time constant (Norminal value) in the total integral output width should always satisfy 50%, but it is actually 50 [% because POS (0) = (100 + Q) / 2. ], And the above formula (3) is not always satisfied.

FIG. 7 shows an example of an analog integral waveform from + 50% (RCmax) in increments of -50% (RCmin) to + 6.25% when Q = 50, that is, the RC time constant variation rate is ± 50%. The change in RC time constant on the (+) side accounts for only 25% of the total change, and the remaining 75% is represented by the change in the RC time constant on the (-) side. In the above calibration method, the correction code is formed by uniform distribution. As a result, an accurate correction code cannot be generated, and a missing code can be generated for time constant variation on the positive side.

That is, as described above, since the conventional apparatus is set to form a correction code by a uniform distribution, an accurate correction code cannot be generated, and a missing code is generated for a time constant variation on the '+' side. .

Accordingly, an object of the present invention is to provide a correction code generator capable of generating an accurate correction code based on an actual integration level distribution and to adjust a time constant externally.

1 is a circuit diagram showing the configuration of a general active RC filter.

2 is a circuit diagram showing a configuration of a general passive RC filter.

3 is a circuit diagram showing the configuration of a conventional correction code generator.

4 is a timing diagram in FIG. 3;

FIG. 5 shows the corresponding integrated output peak voltages when the RC time constant maximum value / minimum value changes by ± Q [%] relative to the design value in FIG. Show value.

Figure 6 shows a capacitor row for correction in Figure 3;

FIG. 7 is an integral waveform diagram of variation of ± 50% RC time constant in FIG. 3; FIG.

Fig. 8 is a circuit diagram showing the construction of the present invention correction code generator.

Fig. 9 shows generation of a correction code when N = 5 in Fig. 8;

***** Description of the symbols for the main parts of the drawings *****

1: integrator 2: comparator

3: signal generator 5: latch

6: (N + RB) -Counter 7: (N + RB) -Decoder

The present invention for achieving the above object is an integrator for continuously integrating the reference voltage for a predetermined time after the initial reset, integrating stepwise waveform in accordance with the switching of the switch after the predetermined time; A comparator for comparing the output signal of the integrator with an analog ground voltage and outputting a corresponding comparison signal; A signal generator which receives an output signal of the comparator and generates a count enable signal and a timing signal in synchronization with a clock signal; A (N + RB) -bit counter for counting the count enable signal of the signal generator in the active period of the clock signal and outputting a counting signal according thereto; A (N + RB) -decoder that receives the counting signal of the (N + RB) -bit counter and decodes it; And a latch unit for receiving a decoding signal of the (N + RB) -decoder and latching it to generate a correction code.

Hereinafter, operations and effects of the correction code generator according to the present invention will be described in detail with reference to the accompanying drawings.

8 is a circuit diagram showing the configuration of the correction code generator of the present invention. As shown in FIG. Reference voltage ( ) Are continuously integrated and the predetermined time ( After the switch ( An integrator (1) integrating with a stepped waveform according to the switching; Output signal of the integrator 1 ) And analog ground voltage ( A comparator (2) for comparing) and outputting a comparison signal accordingly; The output signal of the comparator 2 is received and a clock signal ( A signal generator (3) for generating a count enable signal (EN) and a timing signal (TIMING SIGNALS) corresponding thereto in synchronization with; The clock signal ( (N + RB) -bit counter 6 for counting the count enable signal EN of the signal generator 3 and outputting a counting signal N + RB according to the active period of the signal generator 3; A (N + RB) -decoder 7 which receives the counting signal of the (N + RB) -bit counter 6 and decodes it; A latch unit 5 which receives the decoding signal of the (N + RB) -decoder 7 and latches it to generate a correction code will be described. The operation of the present invention will be described.

First, assuming that the allowable RC time constant change rate is W [%], the minimum An N-bit correction code is required to satisfy.

In this case, when each code is 100% of total possible time constant change, Different codes should be generated according to the change of RC time constant of [%].

Here, the peak voltage (integrated output according to the change of RC time constant) ) Is not distributed at regular intervals, so the number of internal bits for generating a correction code should be added by a predetermined bit RB to cover the smallest interval.

At this time, the smallest interval is the peak voltage generated by the time constant for the maximum time constant and the next code generation ( ), In other words , Is the interval between.

Here, the ratio occupied by the interval with respect to the total integrated output width is as shown in the following formula (where N is the number of correction bit codes).

= [%] ----- Equation (4)

Accordingly, the surplus bits RB added to prevent missing code from satisfying the following expression.

--------- Equation (5)

In order to implement the added redundant bit (RB), a voltage of a stepped waveform ( ) And the clock signal (Tck) value should be set anew. Replace the capacitor C1 with C1 / RB and replace the original clock signal (Tck) with Multiplying to obtain a clock signal Tck '.

then, Analog ground voltage The number of possible step waveforms up to It becomes a dog.

Thereafter, the increased stepped waveform is counted in the (N + RB) -bit counter 6, and the (N + RB) -decoder 7 sets the level and the preset value for the total integral width calculated in advance according to the rate of change. In order to map the number of stepped waveforms to the corresponding correction code, the counting signal of the (N + RB) -bit counter 6 is decoded and the final correction code is output through the latch 5.

Accordingly, the correction code operates in a form generated based on the actual integrated output level distribution to generate an accurate correction code.

Here, the integral output signal ( To generate the reference voltage ( ) Can be controlled outside the chip, so that the RC time constant of the filter where the fine adjustment and correction code is input can be programmed outside the chip.

In other words, the present invention uses the number of step waveforms to generate N-bit correction codes. Multiply by and increase to cover the difference between the minimum adjacent peak voltage.

That is, by reducing the values of the capacitor C1 and the clock signal Tck, the number of step waveforms for generating the existing correction code is reduced. Multiply by to increase the difference between the minimum adjacent peak voltages, which increases the number of bits in the counter and adds an (N + RB) -decoder to generate N-bit correction codes and also the RC time constant outside the chip. So that the value can be adjusted To create a reference voltage ( ) To the external pin to adjust the compensation code outside the chip.

9 shows generation of a correction code when N = 5 according to the present invention.

As described in detail above, the present invention enables the generation of an accurate correction code based on the actual integration level, and has the effect of automatically correcting the absolute value change due to environmental factors of the passive element by adjusting the time constant from the outside.

Claims (5)

An integrator that continuously integrates the reference voltage for a predetermined time after the initial reset, and integrates the step voltage in accordance with the switching of the switch after the predetermined time; A comparator for comparing the output signal of the integrator with an analog ground voltage and outputting a corresponding comparison signal; A signal generator which receives an output signal of the comparator and generates a count enable signal and a timing signal in synchronization with a clock signal; A (N + RB) -bit counter for counting the count enable signal of the signal generator in the active period of the clock signal and outputting a counting signal according thereto; A (N + RB) -decoder that receives the counting signal of the (N + RB) -bit counter and decodes it; And a latch unit configured to receive a decoding signal of the (N + RB) -decoder and latch it to generate a correction code. 2. The correction code generator of claim 1, wherein a reference voltage is assigned to an external pin to control the correction code external to the chip. The clock signal of claim 1, wherein the clock signal has an original number of step waveforms ( )on And a multiplication by increasing the correction code generator. The correction code generator according to claim 3, wherein the RB (surplus bit) satisfies the following expression so that a missing code is not generated. Excitation number, above Is the ratio of internal bit spacing to total integral output width. The correction code generator according to claim 1, wherein the (N + RB) -decoder maps the level of the total integral width calculated in advance according to the rate of change and the number of set step waveforms to a corresponding correction code.