KR100193119B1 - Power transistor and its manufacturing method - Google Patents

Abstract

The present invention relates to a semiconductor device for power, comprising: a drain electrode formed on the rear surface of a semiconductor substrate; A gate electrode having a plurality of holes vertically and horizontally disposed on the semiconductor substrate, the first electrode having an impurity region of a first conductivity type formed near a surface of the semiconductor substrate through contact holes formed in the plurality of holes, respectively; A source electrode in contact with the highly conductive first impurity region of the second conductivity type; And a high concentration second impurity region of a second conductivity type formed equidistantly in a diagonal direction with the high concentration second impurity regions of the second conductivity type.

Therefore, in the present invention, by forming additional P + regions so as to have a uniform distance from each other in the diagonal direction between adjacent cells, the electric field distribution inside the device can be made the same, and the reliability of the device can be improved.

Description

Power transistor and its manufacturing method

1 is a cross-sectional view showing the structure of a unit cell of a conventional power MOSFET.

2 is a layout showing unit cell arrangement of a typical power MOSFET.

3 is a graph showing electric field distribution of a silicon surface according to a horizontal distance and a diagonal distance between adjacent cells in a conventional power MOSFET.

4 is a layout diagram showing the unit cell arrangement of the power MOSFET according to the present invention.

5 is a cross-sectional view showing a cross-sectional structure of the A-A line of FIG.

6 to 12 are process flowcharts showing a manufacturing method of a preferred embodiment of the power transistor according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power transistor and a method of manufacturing the same, and more particularly, to a power transistor capable of uniformly making electric field distribution between unit cells of a metal oxide silicon field effect transistor (MOSFET). It is about a method.

Since the power MOSFET is a voltage driven type, the driving circuit is simpler and the input impedance is much higher than that of the current driven type bipolar transistor. In addition, since the power MOSFET is a multi-carrier element, there is no charge accumulation phenomenon compared to the power bipolar transistor, which is a minority carrier element, and the switching speed is very fast, which is suitable for high frequency applications.

In addition, since the power MOSFET has a negative temperature coefficient, secondary breakdown does not occur, and thus, high current rating can be realized by arranging the number of unit cells necessary for design.

1 shows a cross-sectional structure diagram of a power MOSFET according to the prior art. In the conventional power transistor, the N-epitaxial layer 14 is formed on the N ⁺ semiconductor substrate 10, and the P channel region 22 and the P + isolation region 21 are formed near the surface of the epitaxial layer 14. And the N source region 24 in the vicinity of the surface in the P channel region 22 and the P + isolation region 21. A polysilicon gate electrode layer 18 is formed on a portion of the N source region 24 and the surfaces of the P channel region 22 and the N-epitaxial layer 14 via the gate insulating film 16. The source electrode 28 is formed on the exposed part of the surface 24 and the exposed surface of the P + isolation region 21, and the drain electrode 30 is formed on the other side of the semiconductor substrate, i.

The above-described vertical double diffusion type power MOSFET device uses a double diffusion process using a polysilicon as a window as a basic process applied in its manufacture, and has hundreds or thousands of unit cells as shown in FIG. Each has a design structure that is simply arranged so that the distance between adjacent cells is equal to each other. 2 shows a unit cell arrangement of a typical power MOSFET in this regard. However, when the cells are arranged in this way, as the horizontal and vertical distances and the diagonal distances between adjacent cells are different from each other, when the high voltage is applied in the reverse direction, the internal electric field distribution may be different from each other. There was a problem that the reliability is impaired.

3 is a comparison of the electric field distribution on the silicon surface along a horizontal distance and a diagonal distance from an adjacent cell in the case of a typical power MOSFET having a breakdown voltage of 1,000V. As it becomes longer, the electric field is relatively higher than the horizontal distance.

Disclosure of Invention An object of the present invention is to provide a power transistor and a method of manufacturing the same, which can uniformly distribute the electric field inside the device by additionally providing an impurity region equidistantly in diagonal directions between cells in order to solve the problems of the prior art. There is.

In order to achieve the above object, the device of the present invention comprises a drain electrode formed on the back of the semiconductor substrate; A gate electrode having a plurality of openings disposed at equal intervals vertically and horizontally on the semiconductor substrate; A source electrode contacting the first conductivity type impurity region and the second conductivity type high impurity first impurity region formed near the surface of the semiconductor substrate through contact holes respectively formed in the plurality of openings; And a second high concentration second impurity region of a second conductivity type formed at an equidistant distance from the second high concentration second impurity regions of the second conductivity type.

The opening has a circular shape, and the radius of the concentric circle is greater than 1/2 of the horizontal distance from the center of the four high-concentration first impurity regions of the second conductivity-type high-concentration second impurity region of the second conductivity type. It is also characterized by an area that is not overlapped by concentric circles which are equal to and smaller than 1/2 of the diagonal distance.

In addition, the manufacturing method of the present invention comprises the steps of forming a low concentration of the first conductivity type epitaxial layer on the first conductivity type semiconductor substrate; After forming the epitaxial layer, forming a first mask pattern having a second opening disposed at an equidistant distance in the diagonal direction of four first openings adjacent to the first opening disposed at an equidistant distance perpendicularly and horizontally to the surface of the resultant. step; By using the first mask pattern as an impurity implantation mask on the first and second impurity regions of the second conductivity type with high concentration to a third depth deeper than the first depth from the surface of the epitaxial layer and on the impurity regions Simultaneously forming an oxide film; Forming an etch stop layer only on the oxide film corresponding to the first opening and removing the oxide film corresponding to the first mask pattern and the second opening; Removing an etch stop layer to leave an oxide layer only on the first impurity region of the second conductivity type having a high concentration; Forming a gate insulating film on a surface of the resultant product; Forming a gate electrode by covering polysilicon on the gate insulating layer and selectively etching polysilicon by a conventional photolithography process; By using the gate electrode and the oxide film as an impurity implantation mask, a dopant of a second conductivity type is doped to form a second conductivity type impurity region at a first depth so as to be self-aligned to the gate electrode and spaced apart from the buried insulating layer by a predetermined distance. Doing; Using the gate electrode and the oxide film as an impurity implantation mask to form an impurity region of a first conductivity type near the surface in the second impurity region at a second depth lower than the first depth and self-aligned to the gate electrode; step; Covering an interlayer insulating film on the resultant product; Forming a contact hole in a region where the gate electrode is not formed to expose a portion of the second conductivity type impurity region and a portion of the first conductivity type impurity region; Forming a source electrode by coating a metal on the resultant product; And forming a drain electrode on the back surface of the semiconductor substrate.

Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.

4 is a diagram showing a unit cell arrangement of a power MOSFET according to the present invention, wherein an additional P-type diffusion region is formed at a portion of the unit cell facing each other by drawing a concentric circle at the center of the circular first impurity region 21 of each unit cell. The arrangement shows that the diagonal distances are all designed to be the same.

When the unit cells of the power MOSFET are arranged as in the embodiment of the present invention, the non-uniformity of the electric field distribution as shown in FIG. 3 may be eliminated, thereby improving the reliability of the device.

Referring to FIG. 5, the power transistor according to the present invention is epitaxially grown on the first conductivity type semiconductor substrate 10 to have a much lower impurity concentration than the semiconductor substrate 10. From the edge of the gate layer 14, the gate oxide film 16, the polysilicon gate electrode 18, the interlayer insulating film 20, and the gate electrode 16 sequentially stacked on a predetermined region of the surface of the epitaxial layer 14, P + first impurity region 21 diffused near the surface of epitaxial layer 14 at a predetermined distance, and P channel region formed on epitaxial layer 14 so as to self-align to the edge of gate electrode 18. And the N impurity region 24 formed in the P channel region 22 to be self-aligned with the edge of the gate electrode 18, and the P + impurity adjacent to the P + impurity separation region 21 at a predetermined distance. Equal distances apart in the diagonal direction of the regions 21 And the P + second impurity region 32 formed near the surface of the epitaxial layer 14. Reference numeral 20 denotes an interlayer insulating film, 28 a source electrode, 29 a contact hole, and 30 a drain electrode.

That is, in the present invention, the basic shape of the first impurity region of the unit cell is first set to a circular shape when designing the mask drawing, and the basic size and unit of the unit cell according to the required electrical characteristics such as breakdown voltage and current capacity of the device. Determining the required number of cells and the like is the same as in the case of a normal power MOSFET. However, when such a determined element is actually placed on the drawing of the mask, the arrangement must be made so that all diagonal distances between adjacent cells are the same. As shown in FIG. After is determined, concentric circles are drawn at the midpoint of the P + region, each of which has a concentric circle whose radius is greater than or equal to 1/2 of the horizontal distance between adjacent P + regions, and less than 1/2 of the interline distance between adjacent P + regions. Designing to insert an additional P + region into the non-overlapping center region by drawing at the midpoint of the region ensures that the distance from each unit cell is the same, so that the other field characteristics are not penalized and the above-mentioned electric field distribution can be uniformed. Can be.

The manufacturing method of the present invention configured as described above will be described with reference to FIGS. 6 to 12.

Referring to FIG. 6, a low concentration N-epitaxial layer 14 is grown on a high concentration N-type semiconductor substrate 10, and then an oxide film is formed on the surface of the epitaxial layer 14, and a conventional photolithography is performed. The oxide film is selectively etched by the method to form the first mask pattern 34. Subsequently, the P + impurity is selectively injected into the vicinity of the surface of the epitaxial layer 14 using the mask pattern 34, and then the impurities implanted in the oxygen atmosphere are activated to form a third depth from the surface of the epitaxial layer 14. The high concentration second impurity regions 21 and 32 and the oxide film 36 are simultaneously formed on the impurity regions.

Referring to FIG. 7, an etch stop layer 38 formed of a photoresist is formed on the oxide film 36 of the P + impurity regions 21 by a conventional photolithography process, and then used as an etch mask. The oxide film 36 on the mask pattern 34 and the P + impurity region 32 in the center is removed. Referring to FIG. 8, the etch stop layer 52 is removed to leave the quenched film 36 only on the P + impurity region 21, and then the gate oxide film 16 is formed on the surface of the resultant substrate. ) To cover the polysilicon and selectively etch the polysilicon by a conventional photolithography process to form the gate electrode 18.

Referring to FIG. 9, when the P impurity is implanted using the gate electrode 18 and the oxide layer 38 as an impurity implantation mask and the implanted impurity is activated, the gate electrode 18 is self-aligned and the P + impurity. The P impurity region 22 is formed at a first depth to be spaced apart from the region 32 by a predetermined distance. Subsequently, referring to FIG. 10, when the gate electrode 18 and the oxide film 36 are used as an impurity implantation mask, N impurity is implanted and activated in the vicinity of the surface in the P impurity region 22. N impurity region 24 is self-aligned to 18 and is formed to a second depth shallower than the first depth.

Referring to FIG. 11, the interlayer insulating film 20 is covered on the resultant, and the photoresist pattern 40 is formed on the interlayer insulating film 20 by a normal photographic process. Referring to FIG. 12, the interlayer insulating film 20, the gate oxide film 16, and the oxide film may be exposed to expose portions of the P + impurity region 38 and the N impurity region 24 in regions where the gate electrode 14 is not formed. 36 is selectively etched to form a contact hole, and then a metal is deposited to form a source electrode 28, and a drain electrode 30 is formed on the back surface of the semiconductor substrate 10.

In the above embodiment, the mask pattern for the N impurity region 24 is formed in advance in forming the P + impurity region, but the present invention is not limited thereto, and the mask pattern 38 is formed immediately before the N impurity implantation of FIG. It is possible.

As described above, in the present invention, the P + impurity region 32 is additionally equidistant in the diagonal direction between the cells of the power transistor, so that the electric field distribution inside the device can be made uniform, thereby improving the reliability of the device. In addition, since the added P + impurity region may be added during fabrication of the mask for forming the P + impurity region, the P + impurity region may be manufactured by an existing process step without adding a separate mask step.

Claims (4)

A drain electrode formed on the rear surface of the semiconductor substrate; A gate electrode having a plurality of openings disposed at equal intervals vertically and horizontally on the semiconductor substrate; A source electrode contacting the first conductivity type impurity region and the second conductivity type high impurity first impurity region formed near the surface of the semiconductor substrate through contact holes respectively formed in the plurality of openings; And a second heavily doped second impurity region formed at an equidistant distance from the second heavily doped impurity regions in a diagonal direction. The power transistor of claim 1, wherein the opening is formed in a circular shape. The concentric circle of claim 1, wherein the size of the high concentration second impurity region of the second conductivity type is greater than 1/2 of the horizontal distance from the center of the four high concentration first impurity regions of the adjacent second conductivity type. A power transistor, characterized in that it is an area which is not overlapped by concentric circles which are equal to and smaller than 1/2 of the diagonal distance. Forming a low concentration first epitaxial layer on a high concentration first conductivity type semiconductor substrate; After the epitaxial layer is formed, a first mask pattern having a second opening disposed at an equidistant distance in the diagonal direction of four first openings adjacent to the first opening disposed at an equidistant distance perpendicularly and horizontally to the surface of the resultant is formed. Doing; By using the first mask pattern as an impurity implantation mask on the first and second impurity regions of the second conductivity type with high concentration to a third depth deeper than the first depth from the surface of the epitaxial layer and the impurity regions Simultaneously forming an oxide film; Forming an etch stop layer only on the oxide film corresponding to the first opening and removing the oxide film corresponding to the first mask pattern and the second opening; Removing the etch stop layer to leave an oxide layer only on the first impurity region of the second conductivity type with high concentration; Forming a gate insulating film on a surface of the resultant product; Forming a gate electrode by covering polysilicon on the gate insulating layer and selectively etching polysilicon by a conventional photolithography process; By using the gate electrode and the oxide film as an impurity implantation mask, a dopant of a second conductivity type is doped to form a second conductivity type impurity region at a first depth so as to be self-aligned to the gate electrode and spaced apart from the buried insulating layer by a predetermined distance. Doing; By using the gate electrode and the oxide film as an impurity implantation mask, a user self-aligns the gate electrode near the surface in the second impurity region and forms an impurity region of a first conductivity type at a second depth lower than the first depth. step; Covering an interlayer insulating film on the resultant product; Forming a contact hole in a region where the gate electrode is not formed to expose a portion of the second conductivity type impurity region and a portion of the first conductivity type impurity region; Forming a source electrode by coating a metal on the resultant product; And forming a drain electrode on the back surface of the semiconductor substrate.