KR100192942B1 - Multi-synchronizing signal control apparatus for projector - Google Patents

Abstract

An object of the present invention is to provide a multi-synchronous control device capable of properly realizing the image of the PC signal of various modes to the AMA device according to the number of horizontal lines of the input PC video signal, the PC image signal is A / D conversion unit (10) In the case of digital conversion, the line memory 12 adjusts the output ratio of the input data based on the detected current PC mode and outputs the analog data to the AMA device 16. The A converter 14 divides the horizontal synchronous signal extracted from the current PC video signal into a predetermined division ratio, so that the A / D converter 10 and the line memory 12 are used as sampling pulses and the write clock signal CLK 1. 1) the first PLL circuit unit 20, a counter 22 for counting the number of horizontal lines based on the vertical synchronous signal and the horizontal synchronous signal extracted from the current PC video signal, and the horizontal lines counted by the counter 22. The line according to the number A control unit 24 for adjusting the output ratio of the memory 12 and a second PLL circuit unit for providing a variable read clock signal CLK 2 with respect to the output ratio of the line memory 12 under the control of the control unit 24. It is composed of (26).

Description

Multi Synchronous Control

The present invention relates to a multi-synchronous control device, and more particularly, to a multi-synchronous control device that can easily adopt a PC image signal of various resolutions to the AMA projector.

As is well known, the image display device is roughly divided into a direct type display device represented as a CRT device and a projection display device represented as an LCD device, among which a CRT device as a direct display device is used on a fluorescent panel. When a fluorescent point is formed and the electron beam is focused on the R, G, B fluorescent point, the corresponding fluorescent point is emitted to enable display of a color image. However, in such a CRT apparatus, the R, G, B fluorescent point is formed for one pixel. In addition, the screen is not limited to the enlargement of the screen, and the manufacturing cost is increased due to the complicated manufacturing process.

On the other hand, in the LCD device which is a projection display device, a target image is displayed by applying a voltage corresponding to an image signal from the uniform arrangement of liquid crystals as a liquid crystal driving voltage and adjusting the arrangement direction of the liquid crystals with a polarizing plate, thereby making it a relatively light weight. Although thinning is possible, such LCD device has the disadvantage that the light loss is increased by the polarizing plate for adjusting the amount of light emitted relative to the total amount of incident light.

In view of this point, recently, a projection image display device using AMA (Actuated mirror array) has been proposed by Aura of the United States of America, and the image display device using the AMA is a scanning mirror with the AMA arranged in one dimension. It is composed of a one-dimensional structure in which M × 1 light beams are prescanned using a scanning mirror, or a two-dimensional structure in which M × N light beams are projected to represent an image having an array of M × N pixels.

1 is a view for explaining the principle of an AMA device applied to a projection type image display device according to a conventional example, wherein reference numeral 10 denotes the number of pixels to be driven to drive an AMA device having a one-dimensional or two-dimensional structure. A corresponding quantity of MOS transistors represents an active matrix substrate embedded in a matrix array form, and on the active matrix substrate 10 of each MOS transistor arranged in a matrix array form for applying a signal for driving an actuator of an AMA device. A plurality of signal electrode pads 12 derived from the source S side are formed. 20 denotes an actuator connected to the signal electrode pad 12 of the active matrix substrate 10 to adjust an optical path, and the actuator 20 represents the signal electrode pad of the active matrix substrate 10. A support member 22 formed to enclose 12, a membrane 24 formed of, for example, Si ₃ N ₄ so as to extend at a constant length on the support member 22, and a lower electrode above the membrane 24. And a deformable portion 28 formed of a piezoelectric material PZT and an upper electrode 30, respectively. The signal electrode 12 and the lower electrode 26 are electrically connected to each other by a plug 32 extending from the signal electrode pad 12 through the support member 22. As the driving voltage of the MOS transistor appearing on (12) is transmitted to the lower electrode 26, the inclination of the actuator 20 is determined, so that the path of light incident on the upper electrode 30 can be controlled. In addition, the path-adjusted light is transmitted to the projection lens to project the color image.

As such an AMA device has been proposed and put into practical use, a dedicated monitor can convert a PC (Personal Computer) video signal of any resolution (for example, one of 640 × 480, 800 × 600, 1024 × 768, 1280 × 1024 mode) In this case, most of the AMA projectors are fixed at 640 × 480, and since the PC is a higher resolution than the AMA projector, for example, a PC having a resolution of 1280 × 1024 mode is used. When the video signal is implemented with an AMA projector in 640 × 480 mode, the constraint is limited by the fixed number of pixels.

Accordingly, the present invention has been made in view of the above circumstances, and an object thereof is to provide a multi-synchronous control apparatus capable of properly realizing various types of PC signals in the AMA device according to the number of horizontal lines of the input PC image signals. .

According to a preferred embodiment of the present invention to achieve the above object, when the PC image signal is digitally converted by the A / D conversion unit, the input data is stored on the basis of the current PC mode detected by storing the input data. A line memory that outputs the output after adjusting the output ratio, a D / A converter that converts data from the line memory to an AMA device by analog conversion, and divides the horizontal synchronous signal extracted from the current PC video signal into a preset division ratio. A first PLL circuit section provided to the A / D converter and line memory as a sampling pulse and a write clock signal, and a current input PC video signal based on a vertical sync signal and a horizontal sync signal extracted from a currently input PC video signal. A counter for counting the number of horizontal lines for the controller, the controller for adjusting and controlling the output ratio of the line memory according to the number of horizontal lines counted by the counter; Provided is a multi-synchronous control device including a second PLL circuit portion for providing a variable read clock signal with respect to an output ratio of the line memory under the control of the controller.

According to the embodiment of the present invention configured as described above, when the PC video signal of any mode is digitally converted and stored in the line memory, the number of horizontal lines for the input PC video signal is detected and based on the detected number of horizontal lines. Since the control section controls the second PLL circuit section, the output ratio of the line memory is adjusted based on the read clock signal from the second PLL circuit section.

1 is a view for explaining the principle of an AMA apparatus (Actuated mirror array) employed as a projection type image display apparatus according to a conventional example;

2 is a block diagram of a multi-synchronous control device according to an embodiment of the present invention,

3 is a view showing the compression ratio of the horizontal line for each mode according to an embodiment of the present invention,

4 is a signal waveform diagram illustrating an example of a double speed conversion output in the line memory shown in FIG. 2;

5 is a signal waveform diagram for explaining the adjustment of the number of horizontal lines according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: A / D converter 12 --- line memory

14: D / A converter 16 --- AMA device

18: Synchronous separation circuit section 20--1 PLL circuit section

22: counter 24 --- control part

26: second PLL circuit section

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

2 is a block diagram of a multi-synchronous control device according to an embodiment of the present invention, an embodiment of the present invention is an A / D converter 10, a line memory 12, a D / A converter 14, An AMA device 16, a synchronous separation circuit section 18, a first PLL circuit section 20, a counter 22, a control section 24, and a second PLL circuit section 26 are provided.

In the figure, the A / D converter 10 performs sampling / holding on the basis of a sampling pulse (CLK 1 (also referred to as a write clock signal)) provided by the PLL circuit unit 20, which will be described later, with respect to a PC video signal currently input. Quantization is performed to output digital data.

The line memory 12 stores the digital data from the A / D converter 10 and outputs the input data based on the adjusted output ratio (that is, adjusted to the detected current PC mode). The line memory 12 is composed of an input buffer 12A, a write address pointer 12B, a memory 12C, a read address pointer 12D, and an output buffer 12E.

That is, the input buffer 12A temporarily buffers the digital data applied from the A / D conversion section 10 by the write clock signal CLK 1 from the PLL circuit section 20 described later.

The write address pointer 12B is temporarily stored in the buffer 12A by a write reset including N write clock signals CLK 1 and N write clock signals CLK 1 as one cycle. The buffered digital data is stored for each address.

Here, one write reset is made every time the N number of the write clock signals CLK 1 are counted by a counting means (or the first PLL circuit section 20 to be described later).

The memory 12C stores digital data from the buffer 12A for each storage address.

The read address pointer 12D includes N read clock signals CLK 2 and N read clock signals CLK 2 (which may be different from the duty ratio of the write clock signal CLK 1) in one cycle. By read reset, the digital data stored in the memory 12C is outputted for each address.

In this case, one read reset is made every time N counts of the read clock signals CLK 2 are performed by counting means (or the second PLL circuit unit 26 to be described later). The division ratio N2 for determining the read clock signal CLK 2 is determined by the compression ratio of the horizontal line for each mode shown in FIG. 3 (that is, preset in the controller 24 described later).

That is, in the case of 640 × 480 mode (that is, the number of horizontal lines is 480), the compression ratio of the current horizontal line is 1: 1, and in the case of 800 × 600 mode (that is, the number of horizontal lines is 600), The compression ratio of the horizontal line is 5: 4, and in the case of 1024 × 768 mode (that is, the number of horizontal lines is 768), the compression ratio of the current horizontal line is 7: 5, and in the 1280 × 1024 mode (that is, If the number of horizontal lines is 1024), the compression ratio of the current horizontal line is 32:15. For example, in the case of 800 × 600 mode, (480/600) = (4/5), N2 becomes 4 .

The output buffer 12E outputs digital data at a specified address in the memory 12C based on the read clock signal CLK 2 from the second PLL circuit section 26 described later.

On the other hand, the D / A converter 14 converts the digital data output from the buffer 12E in the line memory 12 to the AMA device 16 for analog conversion.

The synchronous separation circuit unit 18 separates the vertical synchronous signal Vsync and the horizontal synchronous signal Hsync from the currently input PC image signal (R / G / B signal).

The first PLL circuit unit 20 converts the pulse obtained by dividing the horizontal synchronous signal Hsync extracted from the synchronous separation circuit unit 18 into a predetermined division ratio N1 as the sampling pulse and the write clock signal as the A / D conversion. To the buffer 12A in the section 10 and the line memory 12.

The counter 22 receives the vertical synchronizing signal Vsync and the horizontal synchronizing signal Hsync output from the synchronizing separation circuit unit 18, and the horizontal synchronizing signal Vlow in the low section of the vertical synchronizing signal Vsync. Hsync) is counted to find the number of horizontal lines of the PC video signal currently being input.

The control unit 24 is a second PLL circuit unit 26 to be described later so that the output ratio (that is, the compression ratio of the horizontal line for each mode) in the line memory 12 in accordance with the number of horizontal lines counted by the counter 22 To control.

The second PLL circuit unit 26 provides a read clock signal CLK 2 that is variable with respect to the output ratio of the line memory 12 under the control of the controller 24.

4 is a signal waveform diagram illustrating the case of the double speed conversion output in the line memory 12 as an example, in which the write clock signal CLK 1 output from the first PLL circuit unit 20 is equal to (a). When the square pie is generated, the write reset becomes a square wave as shown in (b). Accordingly, the line memory 12 records digital data in a high section of the write reset. When the read clock signal CLK2 from the PLL circuit section 26 is input to the line memory 12 as a square wave of the form as shown in (c), for example, a read reset is made as shown in (d), for example. Since the square wave becomes, the line memory 12 has an output speed that is about twice as fast as the initial storage speed. In other words, the read reset becomes a square wave having a duty ratio of 50% for the write reset as one cycle, so that the double speed conversion output becomes possible.

Next, the operation of the multi-synchronous control device according to an embodiment of the present invention configured as described above is as follows.

In the description of the embodiment of the present invention, the AMA device 16 is set to have a structure of an array of 640 x 480 pixels.

First, a PC video signal of an arbitrary mode (for example, any one of 640 × 480, 800 × 600, 1024 × 768, and 1280 × 1024 modes) is transferred to the line memory 12 through the A / D converter 10. When applied to the memory 12C and stored in the memory 12C, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync extracted by the synchronization separation operation in the synchronization separation circuit unit 18 are applied to the counter 22. The counter 22 counts the horizontal synchronization signal Hsync during the low section of the vertical synchronization signal Vsync to obtain the number of horizontal lines for the current PC video signal.

The obtained horizontal line number is applied to the control unit 24. The control unit 24 grasps the mode of the currently input PC video signal based on the input horizontal line number, and the grasped mode (e.g., , The compression ratio (ie, 5: 4) for the 800x600 mode is provided to the second PLL circuit unit 26.

Accordingly, the second PLL circuit section 26 generates the most optimal read clock signal CLK 2 with respect to the current PC video signal based on the compression ratio, thereby reading the read address pointer 12D in the line memory 12. ) And the buffer 12E.

Then, the digital data (i.e., PC video signal) for the horizontal line of 800x600 mode stored in the memory 12C in the line memory 12 is added to the read reset generated by the read clock signal CLK2. Accordingly, the digital data is adjusted and output in accordance with the 640x480 mode, and the output digital data is analog-converted by the D / A converter 14 and applied to the AMA device 16.

That is, the digital data output from the line memory 12 is output according to the number of horizontal lines that are variably adjusted according to the mode of the input PC video signal, and may be reduced as illustrated in FIG. It may be stretched as illustrated in (b) of FIG. 5.

According to the present invention as described above, the number of horizontal lines is increased or decreased depending on the mode (640 x 480, 800 x 600, 1024 x 768, 1280 x 1024 modes) of the input PC video signal. Even in the normal 640 × 480 mode such as an AMA projector, normal screen realization can be performed without any restrictions.

Claims (1)

When the PC video signal is digitally converted by the A / D converter 10, the line memory 12 stores the input data and adjusts the output ratio of the input data based on the detected current PC mode. , A D / A converter 14 for analog-converting data from the line memory 12 to the AMA device 16, The horizontal synchronization signal extracted from the currently input PC video signal is divided at a predetermined division ratio and provided to the A / D converter 10 and the line memory 12 as a sampling pulse and a write clock signal CLK 1. 1 PLL circuit section 20, A counter 22 for counting the number of horizontal lines for the current input PC video signal based on the vertical synchronous signal and the horizontal synchronous signal extracted from the currently input PC video signal; A controller 24 for adjusting and controlling the output ratio of the line memory 12 according to the number of horizontal lines counted by the counter 22; And a second PLL circuit section (26) for providing a variable read clock signal (CLK 2) for the output ratio of said line memory (12) under the control of said control section (24).